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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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69
u-boot/arch/arm/include/asm/arch-tegra/ap.h Normal file
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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/types.h>
/* Stabilization delays, in usec */
#define PLL_STABILIZATION_DELAY (300)
#define IO_STABILIZATION_DELAY (1000)
#define PLLX_ENABLED (1 << 30)
#define CCLK_BURST_POLICY 0x20008888
#define SUPER_CCLK_DIVIDER 0x80000000
/* Calculate clock fractional divider value from ref and target frequencies */
#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
/* Calculate clock frequency value from reference and clock divider value */
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
/* AVP/CPU ID */
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
/* AP base physical address of internal SRAM */
#define NV_PA_BASE_SRAM 0x40000000
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
#define FLOW_MODE_STOP 2
#define HALT_COP_EVENT_JTAG (1 << 28)
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
/* This is the main entry into U-Boot, used by the Cortex-A9 */
extern void _start(void);
/**
* Works out the SOC/SKU type used for clocks settings
*
* @return SOC type - see TEGRA_SOC...
*/
int tegra_get_chip_sku(void);
/**
* Returns the pure SOC (chip ID) from the HIDREV register
*
* @return SOC ID - see CHIPID_TEGRAxx...
*/
int tegra_get_chip(void);
/**
* Returns the SKU ID from the sku_info register
*
* @return SKU ID - see SKU_ID_Txx...
*/
int tegra_get_sku_info(void);
/* Do any chip-specific cache config */
void config_cache(void);
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
bool tegra_cpu_is_non_secure(void);
#endif

22
u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h Normal file
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/*
* Copyright (c) 2012 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _GP_PADCTRL_H_
#define _GP_PADCTRL_H_
/* APB_MISC_PP registers */
struct apb_misc_pp_ctlr {
u32 reserved0[2];
u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
u32 reserved1[6]; /* 0x0c .. 0x20 */
u32 cfg_ctl; /* 0x24 */
};
/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
#define RAM_CODE_SHIFT 4
#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT)
#endif

34
u-boot/arch/arm/include/asm/arch-tegra/board.h Normal file
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/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_BOARD_H_
#define _TEGRA_BOARD_H_
/* Set up pinmux to make UART usable */
void gpio_early_init_uart(void);
/* Set up early UART output */
void board_init_uart_f(void);
/* Set up any early GPIOs the board might need for proper operation */
void gpio_early_init(void); /* overrideable GPIO config */
/*
* Hooks to allow boards to set up the pinmux for a specific function.
* Has to be implemented in the board files as we don't yet support pinmux
* setup from FTD. If a board file does not implement one of those functions
* an empty stub function will be called.
*/
void pinmux_init(void); /* overridable general pinmux setup */
void pin_mux_usb(void); /* overridable USB pinmux setup */
void pin_mux_spi(void); /* overridable SPI pinmux setup */
void pin_mux_nand(void); /* overridable NAND pinmux setup */
void pin_mux_mmc(void); /* overridable mmc pinmux setup */
void pin_mux_display(void); /* overridable DISPLAY pinmux setup */
#endif

452
u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h Normal file
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/*
* (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_CLK_RST_H_
#define _TEGRA_CLK_RST_H_
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_base; /* the control register */
/* pll_out[0] is output A control, pll_out[1] is output B control */
uint pll_out[2];
uint pll_misc; /* other misc things */
};
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll_simple {
uint pll_base; /* the control register */
uint pll_misc; /* other misc things */
};
struct clk_pllm {
uint pllm_base; /* the control register */
uint pllm_out; /* output control */
uint pllm_misc1; /* misc1 */
uint pllm_misc2; /* misc2 */
};
/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
struct clk_set_clr {
uint set;
uint clr;
};
/*
* Most PLLs use the clk_pll structure, but some have a simpler two-member
* structure for which we use clk_pll_simple. The reason for this non-
* othogonal setup is not stated.
*/
enum {
TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
struct clk_rst_ctlr {
uint crc_rst_src; /* _RST_SOURCE_0,0x00 */
uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
uint crc_reserved0; /* reserved_0, 0x1C */
uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
uint crc_reserved1; /* reserved_1, 0x3C */
uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */
uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */
uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */
uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */
uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */
struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
/* PLLs from 0xe0 to 0xf4 */
struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
uint crc_reserved10; /* _reserved_10, 0xF8 */
uint crc_reserved11; /* _reserved_11, 0xFC */
uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */
uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */
/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */
/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */
uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
/* Additional (T30) registers */
uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */
uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */
uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */
/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
/* Additional (T114+) registers */
uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
uint crc_reserved40[1]; /* _reserved_40, 0x474 */
uint crc_intstatus; /* __INTSTATUS_0, 0x478 */
uint crc_intmask; /* __INTMASK_0, 0x47C */
uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */
uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */
uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */
uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */
uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */
uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */
uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */
uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */
uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */
uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */
uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */
uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
uint crc_reserved51[1]; /* _reserved_51, 0x538 */
uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */
uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */
uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
uint crc_reserved52[1]; /* _reserved_52, 0x554 */
uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */
u32 _rsv32[4]; /* 0x560-0x56c */
u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
u32 _rsv32_1[7]; /* 0x574-58c */
struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
/* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
/* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
/*
* NOTE: PLLA1 regs are in the middle of this Y region. Break this in
* two later if PLLA1 is needed, but for now this is cleaner.
*/
uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
#define CPU3_CLK_STP_SHIFT 11
#define CPU2_CLK_STP_SHIFT 10
#define CPU1_CLK_STP_SHIFT 9
#define CPU0_CLK_STP_SHIFT 8
#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
#define PLL_BYPASS_SHIFT 31
#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT)
#define PLL_ENABLE_SHIFT 30
#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT)
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
#define PLL_LOCK_SHIFT 27
#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT)
/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
#define PLL_OUT_RSTN (1 << 0)
#define PLL_OUT_CLKEN (1 << 1)
#define PLL_OUT_OVRRIDE (1 << 2)
#define PLL_OUT_RATIO_SHIFT 8
#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
#define PLL_DCCON_SHIFT 20
#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
#define PLLP_OUT1_OVR (1 << 2)
#define PLLP_OUT2_OVR (1 << 18)
#define PLLP_OUT3_OVR (1 << 2)
#define PLLP_OUT4_OVR (1 << 18)
#define PLLP_OUT1_RATIO 8
#define PLLP_OUT2_RATIO 24
#define PLLP_OUT3_RATIO 8
#define PLLP_OUT4_RATIO 24
enum {
IN_408_OUT_204_DIVISOR = 2,
IN_408_OUT_102_DIVISOR = 6,
IN_408_OUT_48_DIVISOR = 15,
IN_408_OUT_9_6_DIVISOR = 83,
};
#define PLLP_OUT1_RSTN_DIS (1 << 0)
#define PLLP_OUT1_RSTN_EN (0 << 0)
#define PLLP_OUT1_CLKEN (1 << 1)
#define PLLP_OUT2_RSTN_DIS (1 << 16)
#define PLLP_OUT2_RSTN_EN (0 << 16)
#define PLLP_OUT2_CLKEN (1 << 17)
#define PLLP_OUT3_RSTN_DIS (1 << 0)
#define PLLP_OUT3_RSTN_EN (0 << 0)
#define PLLP_OUT3_CLKEN (1 << 1)
#define PLLP_OUT4_RSTN_DIS (1 << 16)
#define PLLP_OUT4_RSTN_EN (0 << 16)
#define PLLP_OUT4_CLKEN (1 << 17)
/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
#define PLLU_POWERDOWN (1 << 16)
#define PLL_ENABLE_POWERDOWN (1 << 14)
#define PLL_ACTIVE_POWERDOWN (1 << 12)
/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
#define OSC_XOE_SHIFT 0
#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT)
#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT)
#define OSC_XOBP_SHIFT 1
#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
#define OSC_XOFS_SHIFT 4
#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
#define OSC_DRIVE_STRENGTH 7
/*
* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
* but can be 16. We could use knowledge we have to restrict the mask in
* the 8-bit cases (the divider_bits value returned by
* get_periph_clock_source()) but it does not seem worth it since the code
* already checks the ranges of values it is writing, in clk_get_divider().
*/
#define OUT_CLK_DIVISOR_SHIFT 0
#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
#define OUT_CLK_SOURCE_31_30_SHIFT 30
#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
#define OUT_CLK_SOURCE_31_29_SHIFT 29
#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT)
/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
#define OUT_CLK_SOURCE_31_28_SHIFT 28
#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
#define SCLK_SYS_STATE_SHIFT 28U
#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
enum {
SCLK_SYS_STATE_STDBY,
SCLK_SYS_STATE_IDLE,
SCLK_SYS_STATE_RUN,
SCLK_SYS_STATE_IRQ = 4U,
SCLK_SYS_STATE_FIQ = 8U,
};
#define SCLK_COP_FIQ_MASK (1 << 27)
#define SCLK_CPU_FIQ_MASK (1 << 26)
#define SCLK_COP_IRQ_MASK (1 << 25)
#define SCLK_CPU_IRQ_MASK (1 << 24)
#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
#define SCLK_SWAKEUP_RUN_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
enum {
SCLK_SOURCE_CLKM,
SCLK_SOURCE_PLLC_OUT1,
SCLK_SOURCE_PLLP_OUT4,
SCLK_SOURCE_PLLP_OUT3,
SCLK_SOURCE_PLLP_OUT2,
SCLK_SOURCE_CLKD,
SCLK_SOURCE_CLKS,
SCLK_SOURCE_PLLM_OUT1,
};
#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
#define SUPER_SCLK_ENB_SHIFT 31U
#define SUPER_SCLK_ENB_MASK (1U << 31)
#define SUPER_SCLK_DIVIDEND_SHIFT 8
#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
#define SUPER_SCLK_DIVISOR_SHIFT 0
#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
#define CLK_SYS_RATE_APB_RATE_SHIFT 0
#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
#define CLR_CPURESET0 (1 << 0)
#define CLR_CPURESET1 (1 << 1)
#define CLR_CPURESET2 (1 << 2)
#define CLR_CPURESET3 (1 << 3)
#define CLR_DBGRESET0 (1 << 12)
#define CLR_DBGRESET1 (1 << 13)
#define CLR_DBGRESET2 (1 << 14)
#define CLR_DBGRESET3 (1 << 15)
#define CLR_CORERESET0 (1 << 16)
#define CLR_CORERESET1 (1 << 17)
#define CLR_CORERESET2 (1 << 18)
#define CLR_CORERESET3 (1 << 19)
#define CLR_CXRESET0 (1 << 20)
#define CLR_CXRESET1 (1 << 21)
#define CLR_CXRESET2 (1 << 22)
#define CLR_CXRESET3 (1 << 23)
#define CLR_L2RESET (1 << 24)
#define CLR_NONCPURESET (1 << 29)
#define CLR_PRESETDBG (1 << 30)
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
#define CLR_CPU0_CLK_STP (1 << 8)
#define CLR_CPU1_CLK_STP (1 << 9)
#define CLR_CPU2_CLK_STP (1 << 10)
#define CLR_CPU3_CLK_STP (1 << 11)
/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)
/* CRC_CLK_ENB_V_SET_0 0x440 */
#define SET_CLK_ENB_CPUG_ENABLE (1 << 0)
#define SET_CLK_ENB_CPULP_ENABLE (1 << 1)
#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3)
/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
#define PLL_ACTIVE_POWERDOWN (1 << 12)
#define PLL_ENABLE_POWERDOWN (1 << 14)
#define PLLU_POWERDOWN (1 << 16)
/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
#define PLLX_IDDQ_SHIFT 3
#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
/* CLK_RST_PLLDP_SS_CFG */
#define PLLDP_SS_CFG_CLAMP (1 << 22)
#define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24)
#define PLLDP_SS_CFG_DITHER (1 << 28)
/* CLK_RST_PLLD_MISC */
#define PLLD_CLKENABLE 30
#endif /* _TEGRA_CLK_RST_H_ */

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/*
* Copyright (c) 2011 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra clock control functions */
#ifndef _TEGRA_CLOCK_H_
#define _TEGRA_CLOCK_H_
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
/* All in MHz, so 13_0 is 13.0MHz */
CLOCK_OSC_FREQ_13_0,
CLOCK_OSC_FREQ_19_2,
CLOCK_OSC_FREQ_12_0,
CLOCK_OSC_FREQ_26_0,
CLOCK_OSC_FREQ_38_4,
CLOCK_OSC_FREQ_48_0,
CLOCK_OSC_FREQ_COUNT,
};
/*
* Note that no Tegra clock register actually uses all of bits 31:28 as
* the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
* those cases, nothing is stored in the bits about the mux field, so it's
* safe to pretend that the mux field extends all the way to the end of the
* register. As such, the U-Boot clock driver is currently a bit lazy, and
* doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
* them all together and pretends they're all 31:28.
*/
enum {
MASK_BITS_31_30,
MASK_BITS_31_29,
MASK_BITS_31_28,
};
#include <asm/arch/clock-tables.h>
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
/* return the current oscillator clock frequency */
enum clock_osc_freq clock_get_osc_freq(void);
/* return the clk_m frequency */
unsigned int clk_m_get_rate(unsigned int parent_rate);
/**
* Start PLL using the provided configuration parameters.
*
* @param id clock id
* @param divm input divider
* @param divn feedback divider
* @param divp post divider 2^n
* @param cpcon charge pump setup control
* @param lfcon loop filter setup control
*
* @returns monotonic time in us that the PLL will be stable
*/
unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon);
/**
* Set PLL output frequency
*
* @param clkid clock id
* @param pllout pll output id
* @param rate desired output rate
*
* @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
*/
int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
unsigned rate);
/**
* Read low-level parameters of a PLL.
*
* @param id clock id to read (note: USB is not supported)
* @param divm returns input divider
* @param divn returns feedback divider
* @param divp returns post divider 2^n
* @param cpcon returns charge pump setup control
* @param lfcon returns loop filter setup control
*
* @returns 0 if ok, -1 on error (invalid clock id)
*/
int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
u32 *divp, u32 *cpcon, u32 *lfcon);
/*
* Enable a clock
*
* @param id clock id
*/
void clock_enable(enum periph_id clkid);
/*
* Disable a clock
*
* @param id clock id
*/
void clock_disable(enum periph_id clkid);
/*
* Set whether a clock is enabled or disabled.
*
* @param id clock id
* @param enable 1 to enable, 0 to disable
*/
void clock_set_enable(enum periph_id clkid, int enable);
/**
* Reset a peripheral. This puts it in reset, waits for a delay, then takes
* it out of reset and waits for th delay again.
*
* @param periph_id peripheral to reset
* @param us_delay time to delay in microseconds
*/
void reset_periph(enum periph_id periph_id, int us_delay);
/**
* Put a peripheral into or out of reset.
*
* @param periph_id peripheral to reset
* @param enable 1 to put into reset, 0 to take out of reset
*/
void reset_set_enable(enum periph_id periph_id, int enable);
/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
enum crc_reset_id {
/* Things we can hold in reset for each CPU */
crc_rst_cpu = 1,
crc_rst_de = 1 << 4, /* What is de? */
crc_rst_watchdog = 1 << 8,
crc_rst_debug = 1 << 12,
};
/**
* Put parts of the CPU complex into or out of reset.\
*
* @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
* @param which which parts of the complex to affect (OR of crc_reset_id)
* @param reset 1 to assert reset, 0 to de-assert
*/
void reset_cmplx_set_enable(int cpu, int which, int reset);
/**
* Set the source for a peripheral clock. This plus the divisor sets the
* clock rate. You need to look up the datasheet to see the meaning of the
* source parameter as it changes for each peripheral.
*
* Warning: This function is only for use pre-relocation. Please use
* clock_start_periph_pll() instead.
*
* @param periph_id peripheral to adjust
* @param source source clock (0, 1, 2 or 3)
*/
void clock_ll_set_source(enum periph_id periph_id, unsigned source);
/**
* This function is similar to clock_ll_set_source() except that it can be
* used for clocks with more than 2 mux bits.
*
* @param periph_id peripheral to adjust
* @param mux_bits number of mux bits for the clock
* @param source source clock (0-15 depending on mux_bits)
*/
int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
unsigned source);
/**
* Set the source and divisor for a peripheral clock. This sets the
* clock rate. You need to look up the datasheet to see the meaning of the
* source parameter as it changes for each peripheral.
*
* Warning: This function is only for use pre-relocation. Please use
* clock_start_periph_pll() instead.
*
* @param periph_id peripheral to adjust
* @param source source clock (0, 1, 2 or 3)
* @param divisor divisor value to use
*/
void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
unsigned divisor);
/**
* Start a peripheral PLL clock at the given rate. This also resets the
* peripheral.
*
* @param periph_id peripheral to start
* @param parent PLL id of required parent clock
* @param rate Required clock rate in Hz
* @return rate selected in Hz, or -1U if something went wrong
*/
unsigned clock_start_periph_pll(enum periph_id periph_id,
enum clock_id parent, unsigned rate);
/**
* Returns the rate of a peripheral clock in Hz. Since the caller almost
* certainly knows the parent clock (having just set it) we require that
* this be passed in so we don't need to work it out.
*
* @param periph_id peripheral to start
* @param parent PLL id of parent clock (used to calculate rate, you
* must know this!)
* @return clock rate of peripheral in Hz
*/
unsigned long clock_get_periph_rate(enum periph_id periph_id,
enum clock_id parent);
/**
* Adjust peripheral PLL clock to the given rate. This does not reset the
* peripheral. If a second stage divisor is not available, pass NULL for
* extra_div. If it is available, then this parameter will return the
* divisor selected (which will be a power of 2 from 1 to 256).
*
* @param periph_id peripheral to start
* @param parent PLL id of required parent clock
* @param rate Required clock rate in Hz
* @param extra_div value for the second-stage divisor (NULL if one is
not available)
* @return rate selected in Hz, or -1U if something went wrong
*/
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
enum clock_id parent, unsigned rate, int *extra_div);
/**
* Returns the clock rate of a specified clock, in Hz.
*
* @param parent PLL id of clock to check
* @return rate of clock in Hz
*/
unsigned clock_get_rate(enum clock_id clkid);
/**
* Start up a UART using low-level calls
*
* Prior to relocation clock_start_periph_pll() cannot be called. This
* function provides a way to set up a UART using low-level calls which
* do not require BSS.
*
* @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
*/
void clock_ll_start_uart(enum periph_id periph_id);
/**
* Decode a peripheral ID from a device tree node.
*
* This works by looking up the peripheral's 'clocks' node and reading out
* the second cell, which is the clock number / peripheral ID.
*
* @param blob FDT blob to use
* @param node Node to look at
* @return peripheral ID, or PERIPH_ID_NONE if none
*/
enum periph_id clock_decode_periph_id(const void *blob, int node);
/**
* Checks if the oscillator bypass is enabled (XOBP bit)
*
* @return 1 if bypass is enabled, 0 if not
*/
int clock_get_osc_bypass(void);
/*
* Checks that clocks are valid and prints a warning if not
*
* @return 0 if ok, -1 on error
*/
int clock_verify(void);
/* Initialize the clocks */
void clock_init(void);
/* Initialize the PLLs */
void clock_early_init(void);
/* Returns a pointer to the clock source register for a peripheral */
u32 *get_periph_source_reg(enum periph_id periph_id);
/* Returns a pointer to the given 'simple' PLL */
struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
*
* There is special code here to handle the one source type with 5 sources.
*
* @param periph_id peripheral to start
* @param source PLL id of required parent clock
* @param mux_bits Set to number of bits in mux register: 2 or 4
* @param divider_bits Set to number of divider bits (8 or 16)
* @return mux value (0-4, or -1 if not found)
*/
int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits);
/*
* Convert a device tree clock ID to our peripheral ID. They are mostly
* the same but we are very cautious so we check that a valid clock ID is
* provided.
*
* @param clk_id Clock ID according to tegra30 device tree binding
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
*/
enum periph_id clk_id_to_periph_id(int clk_id);
/**
* Set the output frequency you want for each PLL clock.
* PLL output frequencies are programmed by setting their N, M and P values.
* The governing equations are:
* VCO = (Fi / m) * n, Fo = VCO / (2^p)
* where Fo is the output frequency from the PLL.
* Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
* 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
* Please see Tegra TRM section 5.3 to get the detail for PLL Programming
*
* @param n PLL feedback divider(DIVN)
* @param m PLL input divider(DIVN)
* @param p post divider(DIVP)
* @param cpcon base PLL charge pump(CPCON)
* @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
* be overriden), 1 if PLL is already correct
*/
int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
/* return 1 if a peripheral ID is in range */
#define clock_type_id_isvalid(id) ((id) >= 0 && \
(id) < CLOCK_TYPE_COUNT)
/* return 1 if a periphc_internal_id is in range */
#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
(id) < PERIPHC_COUNT)
/* SoC-specific TSC init */
void arch_timer_init(void);
void tegra30_set_up_pllp(void);
/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3)
struct clk_pll_info {
u32 m_shift:5; /* DIVM_SHIFT */
u32 n_shift:5; /* DIVN_SHIFT */
u32 p_shift:5; /* DIVP_SHIFT */
u32 kcp_shift:5; /* KCP/cpcon SHIFT */
u32 kvco_shift:5; /* KVCO/lfcon SHIFT */
u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */
u32 rsvd:1;
u32 m_mask:10; /* DIVM_MASK */
u32 n_mask:12; /* DIVN_MASK */
u32 p_mask:10; /* DIVP_MASK or VCO_MASK */
u32 kcp_mask:10; /* KCP/CPCON MASK */
u32 kvco_mask:10; /* KVCO/LFCON MASK */
u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */
u32 rsvd2:6;
};
extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
/**
* Enable output clock for external peripherals
*
* @param clk_id Clock ID to output (1, 2 or 3)
* @return 0 if OK. -ve on error
*/
int clock_external_output(int clk_id);
#endif /* _TEGRA_CLOCK_H_ */

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/*
* (C) Copyright 2010
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_TEGRA_DC_H
#define __ASM_ARCH_TEGRA_DC_H
/* Register definitions for the Tegra display controller */
/* CMD register 0x000 ~ 0x43 */
struct dc_cmd_reg {
/* Address 0x000 ~ 0x002 */
uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */
uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
uint reserved0[5]; /* reserved_0[5] */
/* Address 0x008 ~ 0x00a */
uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */
uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
uint reserved1[5]; /* reserved_1[5] */
/* Address 0x010 ~ 0x012 */
uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */
uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
uint reserved2[5]; /* reserved_2[5] */
/* Address 0x018 ~ 0x01a */
uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */
uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
uint reserved3[13]; /* reserved_3[13] */
/* Address 0x028 */
uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */
uint reserved4[7]; /* reserved_4[7] */
/* Address 0x030 ~ 0x033 */
uint ctxsw; /* _CMD_CTXSW_0 */
uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */
uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */
uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */
uint reserved5[2]; /* reserved_0[2] */
/* Address 0x036 ~ 0x03e */
uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */
uint int_stat; /* _CMD_INT_STATUS_0 */
uint int_mask; /* _CMD_INT_MASK_0 */
uint int_enb; /* _CMD_INT_ENABLE_0 */
uint int_type; /* _CMD_INT_TYPE_0 */
uint int_polarity; /* _CMD_INT_POLARITY_0 */
uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */
uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */
uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */
uint reserved6; /* reserved_6 */
/* Address 0x040 ~ 0x043 */
uint state_access; /* _CMD_STATE_ACCESS_0 */
uint state_ctrl; /* _CMD_STATE_CONTROL_0 */
uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */
uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */
};
enum {
PIN_REG_COUNT = 4,
PIN_OUTPUT_SEL_COUNT = 7,
};
/* COM register 0x300 ~ 0x329 */
struct dc_com_reg {
/* Address 0x300 ~ 0x301 */
uint crc_ctrl; /* _COM_CRC_CONTROL_0 */
uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */
/* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
uint pin_output_enb[PIN_REG_COUNT];
/* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
uint pin_output_polarity[PIN_REG_COUNT];
/* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
uint pin_output_data[PIN_REG_COUNT];
/* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
uint pin_input_enb[PIN_REG_COUNT];
/* Address 0x312 ~ 0x313 */
uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */
uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */
/* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
/* Address 0x31b ~ 0x329 */
uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */
uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */
uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */
uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */
uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */
uint spi_ctrl; /* _COM_SPI_CONTROL_0 */
uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */
uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */
uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */
uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */
uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */
uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */
uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */
uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */
};
enum dc_disp_h_pulse_pos {
H_PULSE0_POSITION_A,
H_PULSE0_POSITION_B,
H_PULSE0_POSITION_C,
H_PULSE0_POSITION_D,
H_PULSE0_POSITION_COUNT,
};
struct _disp_h_pulse {
/* _DISP_H_PULSE0/1/2_CONTROL_0 */
uint h_pulse_ctrl;
/* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
};
enum dc_disp_v_pulse_pos {
V_PULSE0_POSITION_A,
V_PULSE0_POSITION_B,
V_PULSE0_POSITION_C,
V_PULSE0_POSITION_COUNT,
};
struct _disp_v_pulse0 {
/* _DISP_H_PULSE0/1_CONTROL_0 */
uint v_pulse_ctrl;
/* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
};
struct _disp_v_pulse2 {
/* _DISP_H_PULSE2/3_CONTROL_0 */
uint v_pulse_ctrl;
/* _DISP_H_PULSE2/3_POSITION_A_0 */
uint v_pulse_pos_a;
};
enum dc_disp_h_pulse_reg {
H_PULSE0,
H_PULSE1,
H_PULSE2,
H_PULSE_COUNT,
};
enum dc_disp_pp_select {
PP_SELECT_A,
PP_SELECT_B,
PP_SELECT_C,
PP_SELECT_D,
PP_SELECT_COUNT,
};
/* DISP register 0x400 ~ 0x4c1 */
struct dc_disp_reg {
/* Address 0x400 ~ 0x40a */
uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */
uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */
uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */
uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */
uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */
uint sync_width; /* _DISP_SYNC_WIDTH_0 */
uint back_porch; /* _DISP_BACK_PORCH_0 */
uint disp_active; /* _DISP_DISP_ACTIVE_0 */
uint front_porch; /* _DISP_FRONT_PORCH_0 */
/* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */
struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
/* Address 0x41a ~ 0x421 */
struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
/* Address 0x422 ~ 0x425 */
struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
/* Address 0x426 ~ 0x429 */
uint m0_ctrl; /* _DISP_M0_CONTROL_0 */
uint m1_ctrl; /* _DISP_M1_CONTROL_0 */
uint di_ctrl; /* _DISP_DI_CONTROL_0 */
uint pp_ctrl; /* _DISP_PP_CONTROL_0 */
/* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
uint pp_select[PP_SELECT_COUNT];
/* Address 0x42e ~ 0x435 */
uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */
uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */
uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */
uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */
uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */
uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */
uint border_color; /* _DISP_BORDER_COLOR_0 */
/* Address 0x436 ~ 0x439 */
uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */
uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */
uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */
uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */
uint reserved0[2]; /* reserved_0[2] */
/* Address 0x43c ~ 0x442 */
uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */
uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */
uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */
uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */
uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */
uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */
uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */
/* Address 0x443 ~ 0x446 */
uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */
uint reserved1[0x39]; /* reserved1[0x39], */
/* Address 0x480 ~ 0x484 */
uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */
uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */
uint reserved2[0x3b]; /* reserved2[0x3b] */
/* Address 0x4c0 ~ 0x4c1 */
uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */
uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */
u32 rsvd_4c2[34]; /* 4c2 - 4e3 */
/* Address 0x4e4 */
u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */
};
enum dc_winc_filter_p {
WINC_FILTER_COUNT = 0x10,
};
/* Window A/B/C register 0x500 ~ 0x628 */
struct dc_winc_reg {
/* Address 0x500 */
uint color_palette; /* _WINC_COLOR_PALETTE_0 */
uint reserved0[0xff]; /* reserved_0[0xff] */
/* Address 0x600 */
uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */
/* _WINC_H_FILTER_P00~0F_0 */
/* Address 0x601 ~ 0x610 */
uint h_filter_p[WINC_FILTER_COUNT];
/* Address 0x611 ~ 0x618 */
uint csc_yof; /* _WINC_CSC_YOF_0 */
uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */
uint csc_kur; /* _WINC_CSC_KUR_0 */
uint csc_kvr; /* _WINC_CSC_KVR_0 */
uint csc_kug; /* _WINC_CSC_KUG_0 */
uint csc_kvg; /* _WINC_CSC_KVG_0 */
uint csc_kub; /* _WINC_CSC_KUB_0 */
uint csc_kvb; /* _WINC_CSC_KVB_0 */
/* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
uint v_filter_p[WINC_FILTER_COUNT];
};
/* WIN A/B/C Register 0x700 ~ 0x719*/
struct dc_win_reg {
/* Address 0x700 ~ 0x719 */
uint win_opt; /* _WIN_WIN_OPTIONS_0 */
uint byte_swap; /* _WIN_BYTE_SWAP_0 */
uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */
uint color_depth; /* _WIN_COLOR_DEPTH_0 */
uint pos; /* _WIN_POSITION_0 */
uint size; /* _WIN_SIZE_0 */
uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */
uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */
uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */
uint dda_increment; /* _WIN_DDA_INCREMENT_0 */
uint line_stride; /* _WIN_LINE_STRIDE_0 */
uint buf_stride; /* _WIN_BUF_STRIDE_0 */
uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */
uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */
uint dv_ctrl; /* _WIN_DV_CONTROL_0 */
uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */
uint blend_1win; /* _WIN_BLEND_1WIN_0 */
uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */
uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */
uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */
uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */
uint global_alpha; /* _WIN_GLOBAL_ALPHA */
uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */
uint blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */
uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */
uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */
};
/* WINBUF A/B/C Register 0x800 ~ 0x80d */
struct dc_winbuf_reg {
/* Address 0x800 ~ 0x80d */
uint start_addr; /* _WINBUF_START_ADDR_0 */
uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */
uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */
uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */
uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */
uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */
uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */
uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */
uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */
uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */
uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */
uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */
uint rsvd_80c;
uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */
};
/* Display Controller (DC_) regs */
struct dc_ctlr {
struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */
uint reserved0[0x2bc];
struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */
uint reserved1[0xd6];
struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */
uint reserved2[0x1b];
struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */
uint reserved3[0xd7];
struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/
uint reserved4[0xe6];
struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */
};
/* DC_CMD_DISPLAY_COMMAND 0x032 */
#define CTRL_MODE_SHIFT 5
#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
enum {
CTRL_MODE_STOP,
CTRL_MODE_C_DISPLAY,
CTRL_MODE_NC_DISPLAY,
};
/* _WIN_COLOR_DEPTH_0 */
enum win_color_depth_id {
COLOR_DEPTH_P1,
COLOR_DEPTH_P2,
COLOR_DEPTH_P4,
COLOR_DEPTH_P8,
COLOR_DEPTH_B4G4R4A4,
COLOR_DEPTH_B5G5R5A,
COLOR_DEPTH_B5G6R5,
COLOR_DEPTH_AB5G5R5,
COLOR_DEPTH_B8G8R8A8 = 12,
COLOR_DEPTH_R8G8B8A8,
COLOR_DEPTH_B6x2G6x2R6x2A8,
COLOR_DEPTH_R6x2G6x2B6x2A8,
COLOR_DEPTH_YCbCr422,
COLOR_DEPTH_YUV422,
COLOR_DEPTH_YCbCr420P,
COLOR_DEPTH_YUV420P,
COLOR_DEPTH_YCbCr422P,
COLOR_DEPTH_YUV422P,
COLOR_DEPTH_YCbCr422R,
COLOR_DEPTH_YUV422R,
COLOR_DEPTH_YCbCr422RA,
COLOR_DEPTH_YUV422RA,
};
/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
#define PW0_ENABLE BIT(0)
#define PW1_ENABLE BIT(2)
#define PW2_ENABLE BIT(4)
#define PW3_ENABLE BIT(6)
#define PW4_ENABLE BIT(8)
#define PM0_ENABLE BIT(16)
#define PM1_ENABLE BIT(18)
#define SPI_ENABLE BIT(24)
#define HSPI_ENABLE BIT(25)
/* DC_CMD_STATE_ACCESS 0x040 */
#define READ_MUX_ASSEMBLY (0 << 0)
#define READ_MUX_ACTIVE (1 << 0)
#define WRITE_MUX_ASSEMBLY (0 << 2)
#define WRITE_MUX_ACTIVE (1 << 2)
/* DC_CMD_STATE_CONTROL 0x041 */
#define GENERAL_ACT_REQ BIT(0)
#define WIN_A_ACT_REQ BIT(1)
#define WIN_B_ACT_REQ BIT(2)
#define WIN_C_ACT_REQ BIT(3)
#define WIN_D_ACT_REQ BIT(4)
#define WIN_H_ACT_REQ BIT(5)
#define CURSOR_ACT_REQ BIT(7)
#define GENERAL_UPDATE BIT(8)
#define WIN_A_UPDATE BIT(9)
#define WIN_B_UPDATE BIT(10)
#define WIN_C_UPDATE BIT(11)
#define WIN_D_UPDATE BIT(12)
#define WIN_H_UPDATE BIT(13)
#define CURSOR_UPDATE BIT(15)
#define NC_HOST_TRIG BIT(24)
/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
#define WINDOW_A_SELECT BIT(4)
#define WINDOW_B_SELECT BIT(5)
#define WINDOW_C_SELECT BIT(6)
#define WINDOW_D_SELECT BIT(7)
#define WINDOW_H_SELECT BIT(8)
/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
#define CURSOR_ENABLE BIT(16)
#define SOR_ENABLE BIT(25)
#define TVO_ENABLE BIT(28)
#define DSI_ENABLE BIT(29)
#define HDMI_ENABLE BIT(30)
/* DC_DISP_DISP_TIMING_OPTIONS 0x405 */
#define VSYNC_H_POSITION(x) ((x) & 0xfff)
/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
#define SHIFT_CLK_DIVIDER_SHIFT 0
#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT)
#define PIXEL_CLK_DIVIDER_SHIFT 8
#define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT)
enum {
PIXEL_CLK_DIVIDER_PCD1,
PIXEL_CLK_DIVIDER_PCD1H,
PIXEL_CLK_DIVIDER_PCD2,
PIXEL_CLK_DIVIDER_PCD3,
PIXEL_CLK_DIVIDER_PCD4,
PIXEL_CLK_DIVIDER_PCD6,
PIXEL_CLK_DIVIDER_PCD8,
PIXEL_CLK_DIVIDER_PCD9,
PIXEL_CLK_DIVIDER_PCD12,
PIXEL_CLK_DIVIDER_PCD16,
PIXEL_CLK_DIVIDER_PCD18,
PIXEL_CLK_DIVIDER_PCD24,
PIXEL_CLK_DIVIDER_PCD13,
};
/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
#define DATA_FORMAT_SHIFT 0
#define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT)
enum {
DATA_FORMAT_DF1P1C,
DATA_FORMAT_DF1P2C24B,
DATA_FORMAT_DF1P2C18B,
DATA_FORMAT_DF1P2C16B,
DATA_FORMAT_DF2S,
DATA_FORMAT_DF3S,
DATA_FORMAT_DFSPI,
DATA_FORMAT_DF1P3C24B,
DATA_FORMAT_DF1P3C18B,
};
#define DATA_ALIGNMENT_SHIFT 8
enum {
DATA_ALIGNMENT_MSB,
DATA_ALIGNMENT_LSB,
};
#define DATA_ORDER_SHIFT 9
enum {
DATA_ORDER_RED_BLUE,
DATA_ORDER_BLUE_RED,
};
/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
#define DE_SELECT_SHIFT 0
#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
#define DE_SELECT_ACTIVE_BLANK 0x0
#define DE_SELECT_ACTIVE 0x1
#define DE_SELECT_ACTIVE_IS 0x2
#define DE_CONTROL_SHIFT 2
#define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT)
enum {
DE_CONTROL_ONECLK,
DE_CONTROL_NORMAL,
DE_CONTROL_EARLY_EXT,
DE_CONTROL_EARLY,
DE_CONTROL_ACTIVE_BLANK,
};
/* DC_WIN_WIN_OPTIONS 0x700 */
#define H_DIRECTION BIT(0)
enum {
H_DIRECTION_INCREMENT,
H_DIRECTION_DECREMENT,
};
#define V_DIRECTION BIT(2)
enum {
V_DIRECTION_INCREMENT,
V_DIRECTION_DECREMENT,
};
#define COLOR_EXPAND BIT(6)
#define CP_ENABLE BIT(16)
#define DV_ENABLE BIT(20)
#define WIN_ENABLE BIT(30)
/* DC_WIN_BYTE_SWAP 0x701 */
#define BYTE_SWAP_SHIFT 0
#define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT)
enum {
BYTE_SWAP_NOSWAP,
BYTE_SWAP_SWAP2,
BYTE_SWAP_SWAP4,
BYTE_SWAP_SWAP4HW
};
/* DC_WIN_POSITION 0x704 */
#define H_POSITION_SHIFT 0
#define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT)
#define V_POSITION_SHIFT 16
#define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT)
/* DC_WIN_SIZE 0x705 */
#define H_SIZE_SHIFT 0
#define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT)
#define V_SIZE_SHIFT 16
#define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT)
/* DC_WIN_PRESCALED_SIZE 0x706 */
#define H_PRESCALED_SIZE_SHIFT 0
#define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE)
#define V_PRESCALED_SIZE_SHIFT 16
#define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE)
/* DC_WIN_DDA_INCREMENT 0x709 */
#define H_DDA_INC_SHIFT 0
#define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT)
#define V_DDA_INC_SHIFT 16
#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
#define DC_POLL_TIMEOUT_MS 50
#define DC_N_WINDOWS 5
#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
#endif /* __ASM_ARCH_TEGRA_DC_H */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
/* Tegra high-level function multiplexing */
#ifndef _TEGRA_FUNCMUX_H_
#define _TEGRA_FUNCMUX_H_
/**
* Select a config for a particular peripheral.
*
* Each peripheral can operate through a number of configurations,
* which are sets of pins that it uses to bring out its signals.
* The basic config is 0, and higher numbers indicate different
* pinmux settings to bring the peripheral out on other pins,
*
* This function also disables tristate for the function's pins,
* so that they operate in normal mode.
*
* @param id Peripheral id
* @param config Configuration to use (FUNCMUX_...), 0 for default
* @return 0 if ok, -1 on error (e.g. incorrect id or config)
*/
int funcmux_select(enum periph_id id, int config);
#endif /* _TEGRA_FUNCMUX_H_ */

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/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _FUSE_H_
#define _FUSE_H_
/* FUSE registers */
struct fuse_regs {
u32 reserved0[64]; /* 0x00 - 0xFC: */
u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */
u32 reserved1[3]; /* 0x104 - 0x10c: */
u32 sku_info; /* 0x110 */
u32 reserved2[13]; /* 0x114 - 0x144: */
u32 fa; /* 0x148: FUSE_FA */
u32 reserved3[21]; /* 0x14C - 0x19C: */
u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
};
#endif /* ifndef _FUSE_H_ */

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_GP_PADCTRL_H_
#define _TEGRA_GP_PADCTRL_H_
#define GP_HIDREV 0x804
/* bit fields definitions for APB_MISC_GP_HIDREV register */
#define HIDREV_CHIPID_SHIFT 8
#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
#define HIDREV_MAJORPREV_SHIFT 4
#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
/* CHIPID field returned from APB_MISC_GP_HIDREV register */
#define CHIPID_TEGRA20 0x20
#define CHIPID_TEGRA30 0x30
#define CHIPID_TEGRA114 0x35
#define CHIPID_TEGRA124 0x40
#define CHIPID_TEGRA210 0x21
#endif /* _TEGRA_GP_PADCTRL_H_ */

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u-boot/arch/arm/include/asm/arch-tegra/gpio.h Normal file
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/*
* Copyright (c) 2011, Google Inc. All rights reserved.
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_GPIO_H_
#define _TEGRA_GPIO_H_
#include <dt-bindings/gpio/tegra-gpio.h>
#define TEGRA_GPIOS_PER_PORT 8
#define TEGRA_PORTS_PER_BANK 4
#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
#define GPIO_BANK(x) ((x) >> 5)
#define GPIO_PORT(x) (((x) >> 3) & 0x3)
#define GPIO_FULLPORT(x) ((x) >> 3)
#define GPIO_BIT(x) ((x) & 0x7)
enum tegra_gpio_init {
TEGRA_GPIO_INIT_IN,
TEGRA_GPIO_INIT_OUT0,
TEGRA_GPIO_INIT_OUT1,
};
struct tegra_gpio_config {
u32 gpio:16;
u32 init:2;
};
/**
* Configure a list of GPIOs
*
* @param config List of GPIO configurations
* @param len Number of config items in list
*/
void gpio_config_table(const struct tegra_gpio_config *config, int len);
#endif /* TEGRA_GPIO_H_ */

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/*
* (C) Copyright 2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_TEGRA_GPU_H
#define __ASM_ARCH_TEGRA_GPU_H
#if defined(CONFIG_TEGRA_GPU)
void tegra_gpu_config(void);
#else /* CONFIG_TEGRA_GPU */
static inline void tegra_gpu_config(void)
{
}
#endif /* CONFIG_TEGRA_GPU */
#if defined(CONFIG_OF_LIBFDT)
int tegra_gpu_enable_node(void *blob, const char *gpupath);
#else /* CONFIG_OF_LIBFDT */
static inline int tegra_gpu_enable_node(void *blob, const char *compat)
{
return 0;
}
#endif /* CONFIG_OF_LIBFDT */
#endif /* __ASM_ARCH_TEGRA_GPU_H */

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u-boot/arch/arm/include/asm/arch-tegra/mmc.h Normal file
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/*
* Copyright (c) 2011, Google Inc. All rights reserved.
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_MMC_H_
#define _TEGRA_MMC_H_
void tegra_mmc_init(void);
#endif /* _TEGRA_MMC_H_ */

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/*
* (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_PINMUX_H_
#define _TEGRA_PINMUX_H_
#include <linux/types.h>
#include <asm/arch/tegra.h>
/* The pullup/pulldown state of a pin group */
enum pmux_pull {
PMUX_PULL_NORMAL = 0,
PMUX_PULL_DOWN,
PMUX_PULL_UP,
};
/* Defines whether a pin group is tristated or in normal operation */
enum pmux_tristate {
PMUX_TRI_NORMAL = 0,
PMUX_TRI_TRISTATE = 1,
};
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
PMUX_PIN_NONE,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
enum pmux_pin_lock {
PMUX_PIN_LOCK_DEFAULT = 0,
PMUX_PIN_LOCK_DISABLE,
PMUX_PIN_LOCK_ENABLE,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
enum pmux_pin_od {
PMUX_PIN_OD_DEFAULT = 0,
PMUX_PIN_OD_DISABLE,
PMUX_PIN_OD_ENABLE,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
enum pmux_pin_ioreset {
PMUX_PIN_IO_RESET_DEFAULT = 0,
PMUX_PIN_IO_RESET_DISABLE,
PMUX_PIN_IO_RESET_ENABLE,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
enum pmux_pin_rcv_sel {
PMUX_PIN_RCV_SEL_DEFAULT = 0,
PMUX_PIN_RCV_SEL_NORMAL,
PMUX_PIN_RCV_SEL_HIGH,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
enum pmux_pin_e_io_hv {
PMUX_PIN_E_IO_HV_DEFAULT = 0,
PMUX_PIN_E_IO_HV_NORMAL,
PMUX_PIN_E_IO_HV_HIGH,
};
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
/* Defines a pin group cfg's low-power mode select */
enum pmux_lpmd {
PMUX_LPMD_X8 = 0,
PMUX_LPMD_X4,
PMUX_LPMD_X2,
PMUX_LPMD_X,
PMUX_LPMD_NONE = -1,
};
#endif
#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pmux_schmt {
PMUX_SCHMT_DISABLE = 0,
PMUX_SCHMT_ENABLE = 1,
PMUX_SCHMT_NONE = -1,
};
#endif
#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pmux_hsm {
PMUX_HSM_DISABLE = 0,
PMUX_HSM_ENABLE = 1,
PMUX_HSM_NONE = -1,
};
#endif
/*
* This defines the configuration for a pin, including the function assigned,
* pull up/down settings and tristate settings. Having set up one of these
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
* available is pinmux_config_table() to configure a list of pins.
*/
struct pmux_pingrp_config {
u32 pingrp:16; /* pin group PMUX_PINGRP_... */
u32 func:8; /* function to assign PMUX_FUNC_... */
u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
u32 tristate:2; /* tristate or normal PMUX_TRI_... */
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
u32 io:2; /* input or output PMUX_PIN_... */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
u32 lock:2; /* lock enable/disable PMUX_PIN... */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
u32 od:2; /* open-drain or push-pull driver */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
u32 ioreset:2; /* input/output reset PMUX_PIN... */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
u32 rcv_sel:2; /* select between High and Normal */
/* VIL/VIH receivers */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
u32 e_io_hv:2; /* select 3.3v tolerant receivers */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
u32 schmt:2; /* schmitt enable */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_HSM
u32 hsm:2; /* high-speed mode enable */
#endif
};
#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
void pinmux_set_tristate_input_clamping(void);
void pinmux_clear_tristate_input_clamping(void);
#endif
/* Set the mux function for a pin group */
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* Set the pull up/down feature for a pin group */
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
/* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pingrp pin);
/* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pingrp pin);
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
/* Set a pin group as input or output */
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
#endif
/**
* Configure a list of pin groups
*
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len);
struct pmux_pingrp_desc {
u8 funcs[4];
#if defined(CONFIG_TEGRA20)
u8 ctl_id;
u8 pull_id;
#endif /* CONFIG_TEGRA20 */
};
extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
#define PMUX_SLWF_MIN 0
#define PMUX_SLWF_MAX 3
#define PMUX_SLWF_NONE -1
#define PMUX_SLWR_MIN 0
#define PMUX_SLWR_MAX 3
#define PMUX_SLWR_NONE -1
#define PMUX_DRVUP_MIN 0
#define PMUX_DRVUP_MAX 127
#define PMUX_DRVUP_NONE -1
#define PMUX_DRVDN_MIN 0
#define PMUX_DRVDN_MAX 127
#define PMUX_DRVDN_NONE -1
/*
* This defines the configuration for a pin group's pad control config
*/
struct pmux_drvgrp_config {
u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */
u32 slwf:3; /* falling edge slew */
u32 slwr:3; /* rising edge slew */
u32 drvup:8; /* pull-up drive strength */
u32 drvdn:8; /* pull-down drive strength */
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
u32 lpmd:3; /* low-power mode selection */
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
u32 schmt:2; /* schmidt enable */
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
u32 hsm:2; /* high-speed mode enable */
#endif
};
/**
* Set the GP pad configs
*
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
int len);
#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
struct pmux_mipipadctrlgrp_config {
u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */
u32 func:8; /* function to assign PMUX_FUNC_... */
};
void pinmux_config_mipipadctrlgrp_table(
const struct pmux_mipipadctrlgrp_config *config, int len);
struct pmux_mipipadctrlgrp_desc {
u8 funcs[2];
};
extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
#endif /* _TEGRA_PINMUX_H_ */

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PMC_H_
#define _PMC_H_
/* Power Management Controller (APBDEV_PMC_) registers */
struct pmc_ctlr {
uint pmc_cntrl; /* _CNTRL_0, offset 00 */
uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */
#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */
#else
uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */
#endif
uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */
uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */
uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */
uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */
uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */
uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */
uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */
uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */
uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */
uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */
uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */
uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */
uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */
uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */
uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */
uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */
uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */
uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */
uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */
uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */
uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */
uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */
uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */
uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */
uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */
uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */
uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */
uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */
uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */
uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */
uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */
uint pmc_scratch23; /* _SCRATCH23_0, offset AC */
uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */
uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */
uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */
uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */
uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */
uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */
uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */
uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */
uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */
uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */
uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */
uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */
uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */
uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */
uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */
uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */
uint pmc_usb_ao; /* _USB_AO_0, offset F0 */
uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */
uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */
uint pmc_scratch24; /* _SCRATCH24_0, offset FC */
uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */
uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */
uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */
uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */
uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */
uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */
uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */
uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */
uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */
uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */
uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */
uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */
uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */
uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */
uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */
uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */
uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */
uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */
uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */
uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */
uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */
uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */
uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
uint pmc_gate; /* _GATE_0, offset 15C */
/* The following fields are in Tegra124 and later only */
uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */
uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */
uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */
uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */
uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */
uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */
uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */
uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */
uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */
uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */
uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */
uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */
uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */
uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */
uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */
uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */
uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */
uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */
uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */
uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */
uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */
uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */
uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */
uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */
uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */
uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */
uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */
uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */
uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */
uint pmc_reserved0; /* _RESERVED, offset 1D8 */
uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */
uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */
uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */
uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */
uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
uint pmc_todo_0[9]; /* offset 200-220 */
uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */
uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */
uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */
uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */
uint pmc_scratch45;
uint pmc_scratch46;
uint pmc_scratch47;
uint pmc_scratch48;
uint pmc_scratch49;
uint pmc_scratch50;
uint pmc_scratch51;
uint pmc_scratch52;
uint pmc_scratch53;
uint pmc_scratch54;
uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */
uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */
uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */
uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */
uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */
uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */
uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */
uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */
uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */
uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */
uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */
uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */
uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */
uint pmc_secure_scratch9;
uint pmc_secure_scratch10;
uint pmc_secure_scratch11;
uint pmc_secure_scratch12;
uint pmc_secure_scratch13;
uint pmc_secure_scratch14;
uint pmc_secure_scratch15;
uint pmc_secure_scratch16;
uint pmc_secure_scratch17;
uint pmc_secure_scratch18;
uint pmc_secure_scratch19;
uint pmc_secure_scratch20;
uint pmc_secure_scratch21;
uint pmc_secure_scratch22;
uint pmc_secure_scratch23;
uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */
uint pmc_secure_scratch25;
uint pmc_secure_scratch26;
uint pmc_secure_scratch27;
uint pmc_secure_scratch28;
uint pmc_secure_scratch29;
uint pmc_secure_scratch30;
uint pmc_secure_scratch31;
uint pmc_secure_scratch32;
uint pmc_secure_scratch33;
uint pmc_secure_scratch34;
uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */
uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */
uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */
uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */
uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */
uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */
uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */
uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */
uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */
uint pmc_scratch57;
uint pmc_scratch58;
uint pmc_scratch59;
uint pmc_scratch60;
uint pmc_scratch61;
uint pmc_scratch62;
uint pmc_scratch63;
uint pmc_scratch64;
uint pmc_scratch65;
uint pmc_scratch66;
uint pmc_scratch67;
uint pmc_scratch68;
uint pmc_scratch69;
uint pmc_scratch70;
uint pmc_scratch71;
uint pmc_scratch72;
uint pmc_scratch73;
uint pmc_scratch74;
uint pmc_scratch75;
uint pmc_scratch76;
uint pmc_scratch77;
uint pmc_scratch78;
uint pmc_scratch79;
uint pmc_scratch80;
uint pmc_scratch81;
uint pmc_scratch82;
uint pmc_scratch83;
uint pmc_scratch84;
uint pmc_scratch85;
uint pmc_scratch86;
uint pmc_scratch87;
uint pmc_scratch88;
uint pmc_scratch89;
uint pmc_scratch90;
uint pmc_scratch91;
uint pmc_scratch92;
uint pmc_scratch93;
uint pmc_scratch94;
uint pmc_scratch95;
uint pmc_scratch96;
uint pmc_scratch97;
uint pmc_scratch98;
uint pmc_scratch99;
uint pmc_scratch100;
uint pmc_scratch101;
uint pmc_scratch102;
uint pmc_scratch103;
uint pmc_scratch104;
uint pmc_scratch105;
uint pmc_scratch106;
uint pmc_scratch107;
uint pmc_scratch108;
uint pmc_scratch109;
uint pmc_scratch110;
uint pmc_scratch111;
uint pmc_scratch112;
uint pmc_scratch113;
uint pmc_scratch114;
uint pmc_scratch115;
uint pmc_scratch116;
uint pmc_scratch117;
uint pmc_scratch118;
uint pmc_scratch119;
uint pmc_scratch1_eco; /* offset 700 */
};
#define CPU_PWRED 1
#define CPU_CLMP 1
#define PARTID_CP 0xFFFFFFF8
#define START_CP (1 << 8)
#define CPUPWRREQ_OE (1 << 16)
#define CPUPWRREQ_POL (1 << 15)
#define CRAIL 0
#define CE0 14
#define C0NC 15
#define SOR 17
#define PMC_XOFS_SHIFT 1
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
#if defined(CONFIG_TEGRA114)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 2
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 3
#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT)
#endif
#define MULT_1 0
#define MULT_2 1
#define MULT_4 2
#define MULT_8 3
#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define MULT_16 4
#endif
#define AMAP_WRITE_SHIFT 20
#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
/* SEC_DISABLE_0, 0x04 */
#define SEC_DISABLE_WRITE0_ON (1 << 4)
#define SEC_DISABLE_READ0_ON (1 << 5)
#define SEC_DISABLE_WRITE1_ON (1 << 6)
#define SEC_DISABLE_READ1_ON (1 << 7)
#define SEC_DISABLE_WRITE2_ON (1 << 8)
#define SEC_DISABLE_READ2_ON (1 << 9)
#define SEC_DISABLE_WRITE3_ON (1 << 10)
#define SEC_DISABLE_READ3_ON (1 << 11)
#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20)
/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
#define PWRGATE_TOGGLE_PARTID_CRAIL 0
#define PWRGATE_TOGGLE_PARTID_TD 1
#define PWRGATE_TOGGLE_PARTID_VE 2
#define PWRGATE_TOGGLE_PARTID_PCX 3
#define PWRGATE_TOGGLE_PARTID_VDE 4
#define PWRGATE_TOGGLE_PARTID_L2C 5
#define PWRGATE_TOGGLE_PARTID_MPE 6
#define PWRGATE_TOGGLE_PARTID_HEG 7
#define PWRGATE_TOGGLE_PARTID_SAX 8
#define PWRGATE_TOGGLE_PARTID_CE1 9
#define PWRGATE_TOGGLE_PARTID_CE2 10
#define PWRGATE_TOGGLE_PARTID_CE3 11
#define PWRGATE_TOGGLE_PARTID_CELP 12
#define PWRGATE_TOGGLE_PARTID_CE0 14
#define PWRGATE_TOGGLE_PARTID_C0NC 15
#define PWRGATE_TOGGLE_PARTID_C1NC 16
#define PWRGATE_TOGGLE_PARTID_SOR 17
#define PWRGATE_TOGGLE_PARTID_DIS 18
#define PWRGATE_TOGGLE_PARTID_DISB 19
#define PWRGATE_TOGGLE_PARTID_XUSBA 20
#define PWRGATE_TOGGLE_PARTID_XUSBB 21
#define PWRGATE_TOGGLE_PARTID_XUSBC 22
#define PWRGATE_TOGGLE_PARTID_VIC 23
#define PWRGATE_TOGGLE_PARTID_IRAM 24
#define PWRGATE_TOGGLE_START (1 << 8)
/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0)
#define PWRGATE_STATUS_TD_ENABLE (1 << 1)
#define PWRGATE_STATUS_VE_ENABLE (1 << 2)
#define PWRGATE_STATUS_PCX_ENABLE (1 << 3)
#define PWRGATE_STATUS_VDE_ENABLE (1 << 4)
#define PWRGATE_STATUS_L2C_ENABLE (1 << 5)
#define PWRGATE_STATUS_MPE_ENABLE (1 << 6)
#define PWRGATE_STATUS_HEG_ENABLE (1 << 7)
#define PWRGATE_STATUS_SAX_ENABLE (1 << 8)
#define PWRGATE_STATUS_CE1_ENABLE (1 << 9)
#define PWRGATE_STATUS_CE2_ENABLE (1 << 10)
#define PWRGATE_STATUS_CE3_ENABLE (1 << 11)
#define PWRGATE_STATUS_CELP_ENABLE (1 << 12)
#define PWRGATE_STATUS_CE0_ENABLE (1 << 14)
#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15)
#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16)
#define PWRGATE_STATUS_SOR_ENABLE (1 << 17)
#define PWRGATE_STATUS_DIS_ENABLE (1 << 18)
#define PWRGATE_STATUS_DISB_ENABLE (1 << 19)
#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20)
#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21)
#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22)
#define PWRGATE_STATUS_VIC_ENABLE (1 << 23)
#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24)
/* APBDEV_PMC_CNTRL2_0 0x440 */
#define HOLD_CKE_LOW_EN (1 << 12)
#endif /* PMC_H */

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#ifndef _TEGRA_POWERGATE_H_
#define _TEGRA_POWERGATE_H_
#include <asm/arch/clock.h>
enum tegra_powergate {
TEGRA_POWERGATE_CPU,
TEGRA_POWERGATE_3D,
TEGRA_POWERGATE_VENC,
TEGRA_POWERGATE_PCIE,
TEGRA_POWERGATE_VDEC,
TEGRA_POWERGATE_L2,
TEGRA_POWERGATE_MPE,
TEGRA_POWERGATE_HEG,
TEGRA_POWERGATE_SATA,
TEGRA_POWERGATE_CPU1,
TEGRA_POWERGATE_CPU2,
TEGRA_POWERGATE_CPU3,
TEGRA_POWERGATE_CELP,
TEGRA_POWERGATE_3D1,
TEGRA_POWERGATE_CPU0,
TEGRA_POWERGATE_C0NC,
TEGRA_POWERGATE_C1NC,
TEGRA_POWERGATE_SOR,
TEGRA_POWERGATE_DIS,
TEGRA_POWERGATE_DISB,
TEGRA_POWERGATE_XUSBA,
TEGRA_POWERGATE_XUSBB,
TEGRA_POWERGATE_XUSBC,
TEGRA_POWERGATE_VIC,
TEGRA_POWERGATE_IRAM,
};
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph);
int tegra_powergate_power_on(enum tegra_powergate id);
int tegra_powergate_power_off(enum tegra_powergate id);
#endif

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/*
* Tegra pulse width frequency modulator definitions
*
* Copyright (c) 2011 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_TEGRA_PWM_H
#define __ASM_ARCH_TEGRA_PWM_H
/* This is a single PWM channel */
struct pwm_ctlr {
uint control; /* Control register */
uint reserved[3]; /* Space space */
};
#define PWM_NUM_CHANNELS 4
/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
#define PWM_ENABLE_SHIFT 31
#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT)
#define PWM_WIDTH_SHIFT 16
#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT)
#define PWM_DIVIDER_SHIFT 0
#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT)
#endif /* __ASM_ARCH_TEGRA_PWM_H */

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/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SCU_H_
#define _SCU_H_
/* ARM Snoop Control Unit (SCU) registers */
struct scu_ctlr {
uint scu_ctrl; /* SCU Control Register, offset 00 */
uint scu_cfg; /* SCU Config Register, offset 04 */
uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
uint scu_reserved0[12]; /* reserved, offset 10-3C */
uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
uint scu_reserved1[2]; /* reserved, offset 48-4C */
uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
};
#define SCU_CTRL_ENABLE (1 << 0)
#endif /* SCU_H */

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/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
void invalidate_dcache(void);
/**
* tegra_board_id() - Get the board iD
*
* @return a board ID, or -ve on error
*/
int tegra_board_id(void);
/**
* tegra_lcd_pmic_init() - Set up the PMIC for a board
*
* @board_id: Board ID which may be used to select LCD type
* @return 0 if OK, -ve on error
*/
int tegra_lcd_pmic_init(int board_id);
/**
* nvidia_board_init() - perform any board-specific init
*
* @return 0 if OK, -ve on error
*/
int nvidia_board_init(void);
#endif

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_H_
#define _TEGRA_H_
#define NV_PA_ARM_PERIPHBASE 0x50040000
#define NV_PA_PG_UP_BASE 0x60000000
#define NV_PA_TMRUS_BASE 0x60005010
#define NV_PA_TMR5_BASE 0x60005060
#define NV_PA_TMRWDT0_BASE 0x60005100
#define NV_PA_CLK_RST_BASE 0x60006000
#define NV_PA_FLOW_BASE 0x60007000
#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x70000000
#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
defined(CONFIG_TEGRA114)
#define NV_PA_CSITE_BASE 0x70040000
#else
#define NV_PA_CSITE_BASE 0x70800000
#endif
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
#define PG_UP_TAG_AVP 0xAAAAAAAA
#ifndef __ASSEMBLY__
struct timerus {
unsigned int cntr_1us;
};
/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
#define NV_WB_RUN_ADDRESS 0x40020000
#define NVBOOTTYPE_RECOVERY 2 /* BR entered RCM */
#define NVBOOTINFOTABLE_BOOTTYPE 0xC /* Boot type in BIT in IRAM */
#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
/* These are the available SKUs (product types) for Tegra */
enum {
SKU_ID_T20_7 = 0x7,
SKU_ID_T20 = 0x8,
SKU_ID_T25SE = 0x14,
SKU_ID_AP25 = 0x17,
SKU_ID_T25 = 0x18,
SKU_ID_AP25E = 0x1b,
SKU_ID_T25E = 0x1c,
SKU_ID_T33 = 0x80,
SKU_ID_T30 = 0x81, /* Cardhu value */
SKU_ID_TM30MQS_P_A3 = 0xb1,
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
SKU_ID_T210_ENG = 0x00, /* unfused value TBD */
};
/*
* These are used to distinguish SOC types for setting up clocks. Mostly
* we can tell the clocking required by looking at the SOC sku_id, but
* for T30 it is a user option as to whether to run PLLP in fast or slow
* mode, so we have two options there.
*/
enum {
TEGRA_SOC_T20,
TEGRA_SOC_T25,
TEGRA_SOC_T30,
TEGRA_SOC_T114,
TEGRA_SOC_T124,
TEGRA_SOC_T210,
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
};
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL NV_PA_PMC_BASE
#endif
#endif /* TEGRA_H */

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/*
* NVIDIA Tegra I2C controller
*
* Copyright 2010-2011 NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA_I2C_H_
#define _TEGRA_I2C_H_
#include <asm/types.h>
enum {
I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */
I2C_FIFO_DEPTH = 8, /* I2C fifo depth */
};
enum i2c_transaction_flags {
I2C_IS_WRITE = 0x1, /* for I2C write operation */
I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */
I2C_USE_REPEATED_START = 0x4, /* for repeat start */
I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */
I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
I2C_NO_STOP = 0x20,
};
/* Contians the I2C transaction details */
struct i2c_trans_info {
/* flags to indicate the transaction details */
enum i2c_transaction_flags flags;
u32 address; /* I2C slave device address */
u32 num_bytes; /* number of bytes to be transferred */
/*
* Send/receive buffer. For the I2C send operation this buffer should
* be filled with the data to be sent to the slave device. For the I2C
* receive operation this buffer is filled with the data received from
* the slave device.
*/
u8 *buf;
int is_10bit_address;
};
struct i2c_control {
u32 tx_fifo;
u32 rx_fifo;
u32 packet_status;
u32 fifo_control;
u32 fifo_status;
u32 int_mask;
u32 int_status;
};
struct dvc_ctlr {
u32 ctrl1; /* 00: DVC_CTRL_REG1 */
u32 ctrl2; /* 04: DVC_CTRL_REG2 */
u32 ctrl3; /* 08: DVC_CTRL_REG3 */
u32 status; /* 0C: DVC_STATUS_REG */
u32 ctrl; /* 10: DVC_I2C_CTRL_REG */
u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */
u32 reserved_0[2]; /* 18: */
u32 req; /* 20: DVC_REQ_REGISTER */
u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */
u32 reserved_1[6]; /* 28: */
u32 cnfg; /* 40: DVC_I2C_CNFG */
u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */
u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */
u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */
u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */
u32 reserved_2[2]; /* 54: */
u32 i2c_status; /* 5C: DVC_I2C_STATUS */
struct i2c_control control; /* 60 ~ 78 */
};
struct i2c_ctlr {
u32 cnfg; /* 00: I2C_I2C_CNFG */
u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */
u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */
u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */
u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */
u32 reserved_0[2]; /* 14: */
u32 status; /* 1C: I2C_I2C_STATUS */
u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */
u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */
u32 sl_status; /* 28: I2C_I2C_SL_STATUS */
u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */
u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */
u32 reserved_1[2]; /* 34: */
u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
u32 reserved_2[4]; /* 40: */
struct i2c_control control; /* 50 ~ 68 */
u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */
};
/* bit fields definitions for IO Packet Header 1 format */
#define PKT_HDR1_PROTOCOL_SHIFT 4
#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT)
#define PKT_HDR1_CTLR_ID_SHIFT 12
#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT)
#define PKT_HDR1_PKT_ID_SHIFT 16
#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT)
#define PROTOCOL_TYPE_I2C 1
/* bit fields definitions for IO Packet Header 2 format */
#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0
#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
/* bit fields definitions for IO Packet Header 3 format */
#define PKT_HDR3_READ_MODE_SHIFT 19
#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT)
#define PKT_HDR3_REPEAT_START_SHIFT 16
#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT)
#define PKT_HDR3_SLAVE_ADDR_SHIFT 0
#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26
#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \
(1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
/* I2C_CNFG */
#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11
#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
#define I2C_CNFG_PACKET_MODE_SHIFT 10
#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT)
/* I2C_SL_CNFG */
#define I2C_SL_CNFG_NEWSL_SHIFT 2
#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT)
/* I2C_FIFO_STATUS */
#define TX_FIFO_FULL_CNT_SHIFT 0
#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT)
#define TX_FIFO_EMPTY_CNT_SHIFT 4
#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
/* I2C_INTERRUPT_STATUS */
#define I2C_INT_XFER_COMPLETE_SHIFT 7
#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT)
#define I2C_INT_NO_ACK_SHIFT 3
#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT)
#define I2C_INT_ARBITRATION_LOST_SHIFT 2
#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
/* I2C_CLK_DIVISOR_REGISTER */
#define CLK_DIV_STD_FAST_MODE 0x19
#define CLK_DIV_HS_MODE 1
#define CLK_MULT_STD_FAST_MODE 8
/**
* Returns the bus number of the DVC controller
*
* @return number of bus, or -1 if there is no DVC active
*/
int tegra_i2c_get_dvc_bus(struct udevice **busp);
#endif /* _TEGRA_I2C_H_ */

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/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Portions Copyright (C) 2011-2012 NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __TEGRA_MMC_H_
#define __TEGRA_MMC_H_
#include <fdtdec.h>
#include <asm/gpio.h>
/* for mmc_config definition */
#include <mmc.h>
#ifndef __ASSEMBLY__
struct tegra_mmc {
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
unsigned int argument; /* _ARGUMENT_0 */
unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
unsigned int prnsts; /* _PRESENT_STATE_0 */
unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
unsigned char swrst; /* _SW_RESET_ 31:24 */
unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
unsigned char res1[2]; /* _RESERVED 31:16 */
unsigned int capareg; /* _CAPABILITIES_0 */
unsigned char res2[4]; /* RESERVED, offset 44h-47h */
unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
unsigned short setacmd12err; /* offset 50h */
unsigned short setinterr; /* offset 52h */
unsigned char admaerr; /* offset 54h */
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
unsigned long admaaddr; /* offset 58h-5Fh */
unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
unsigned short slotintstatus; /* offset FCh */
unsigned short hcver; /* HOST Version */
unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */
unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */
unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */
unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */
unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */
unsigned int res6[47]; /* 0x124 ~ 0x1DC */
unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */
unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */
unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */
unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */
};
#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0)
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1)
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1)
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1)
#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
/* SDMMC1/3 settings from section 24.6 of T30 TRM */
#define MEMCOMP_PADCTRL_VREF 7
#define AUTO_CAL_ENABLED (1 << 29)
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
struct mmc_host {
struct tegra_mmc *reg;
int id; /* device id/number, 0-3 */
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
#ifndef CONFIG_TEGRA186
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
#endif
struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct gpio_desc pwr_gpio; /* Power GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
struct mmc_config cfg; /* mmc configuration */
};
void pad_init_mmc(struct mmc_host *host);
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */

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/*
* Copyright (c) 2011 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra20 timer functions */
#ifndef _TEGRA_TIMER_H
#define _TEGRA_TIMER_H
/* returns the current monotonic timer value in microseconds */
unsigned long timer_get_us(void);
#endif

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/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _UART_H_
#define _UART_H_
/* UART registers */
struct uart_ctlr {
uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */
uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */
uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */
uint uart_lcr; /* UART_LCR_0, offset 0C */
uint uart_mcr; /* UART_MCR_0, offset 10 */
uint uart_lsr; /* UART_LSR_0, offset 14 */
uint uart_msr; /* UART_MSR_0, offset 18 */
uint uart_spr; /* UART_SPR_0, offset 1C */
uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */
uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/
uint uart_asr; /* UART_ASR_0, offset 3C */
};
#define NVRM_PLLP_FIXED_FREQ_KHZ 216000
#define NV_DEFAULT_DEBUG_BAUD 115200
#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */
#endif /* UART_H */

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/*
* Copyright (c) 2011 The Chromium OS Authors.
* Copyright (c) 2013 NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_USB_H_
#define _TEGRA_USB_H_
/* USB Controller (USBx_CONTROLLER_) regs */
struct usb_ctlr {
/* 0x000 */
uint id;
uint reserved0;
uint host;
uint device;
/* 0x010 */
uint txbuf;
uint rxbuf;
uint reserved1[2];
/* 0x020 */
uint reserved2[56];
/* 0x100 */
u16 cap_length;
u16 hci_version;
uint hcs_params;
uint hcc_params;
uint reserved3[5];
/* 0x120 */
uint dci_version;
uint dcc_params;
uint reserved4[2];
#ifdef CONFIG_TEGRA20
/* 0x130 */
uint reserved4_2[4];
/* 0x140 */
uint usb_cmd;
uint usb_sts;
uint usb_intr;
uint frindex;
/* 0x150 */
uint reserved5;
uint periodic_list_base;
uint async_list_addr;
uint async_tt_sts;
/* 0x160 */
uint burst_size;
uint tx_fill_tuning;
uint reserved6; /* is this port_sc1 on some controllers? */
uint icusb_ctrl;
/* 0x170 */
uint ulpi_viewport;
uint reserved7;
uint endpt_nak;
uint endpt_nak_enable;
/* 0x180 */
uint reserved;
uint port_sc1;
uint reserved8[6];
/* 0x1a0 */
uint reserved9;
uint otgsc;
uint usb_mode;
uint endpt_setup_stat;
/* 0x1b0 */
uint reserved10[20];
/* 0x200 */
uint reserved11[0x80];
#else
/* 0x130 */
uint usb_cmd;
uint usb_sts;
uint usb_intr;
uint frindex;
/* 0x140 */
uint reserved5;
uint periodic_list_base;
uint async_list_addr;
uint reserved5_1;
/* 0x150 */
uint burst_size;
uint tx_fill_tuning;
uint reserved6;
uint icusb_ctrl;
/* 0x160 */
uint ulpi_viewport;
uint reserved7[3];
/* 0x170 */
uint reserved;
uint port_sc1;
uint reserved8[6];
/* 0x190 */
uint reserved9[8];
/* 0x1b0 */
uint reserved10;
uint hostpc1_devlc;
uint reserved10_1[2];
/* 0x1c0 */
uint reserved10_2[4];
/* 0x1d0 */
uint reserved10_3[4];
/* 0x1e0 */
uint reserved10_4[4];
/* 0x1f0 */
uint reserved10_5;
uint otgsc;
uint usb_mode;
uint reserved10_6;
/* 0x200 */
uint endpt_nak;
uint endpt_nak_enable;
uint endpt_setup_stat;
uint reserved11_1[0x7D];
#endif
/* 0x400 */
uint susp_ctrl;
uint phy_vbus_sensors;
uint phy_vbus_wakeup_id;
uint phy_alt_vbus_sys;
#ifdef CONFIG_TEGRA20
/* 0x410 */
uint usb1_legacy_ctrl;
uint reserved12[4];
/* 0x424 */
uint ulpi_timing_ctrl_0;
uint ulpi_timing_ctrl_1;
uint reserved13[53];
#else
/* 0x410 */
uint usb1_legacy_ctrl;
uint reserved12[3];
/* 0x420 */
uint reserved13[56];
#endif
/* 0x500 */
uint reserved14[64 * 3];
/* 0x800 */
uint utmip_pll_cfg0;
uint utmip_pll_cfg1;
uint utmip_xcvr_cfg0;
uint utmip_bias_cfg0;
/* 0x810 */
uint utmip_hsrx_cfg0;
uint utmip_hsrx_cfg1;
uint utmip_fslsrx_cfg0;
uint utmip_fslsrx_cfg1;
/* 0x820 */
uint utmip_tx_cfg0;
uint utmip_misc_cfg0;
uint utmip_misc_cfg1;
uint utmip_debounce_cfg0;
/* 0x830 */
uint utmip_bat_chrg_cfg0;
uint utmip_spare_cfg0;
uint utmip_xcvr_cfg1;
uint utmip_bias_cfg1;
};
/* USB1_LEGACY_CTRL */
#define USB1_NO_LEGACY_MODE 1
#define VBUS_SENSE_CTL_SHIFT 1
#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
#define VBUS_SENSE_CTL_AB_SESS_VLD 2
#define VBUS_SENSE_CTL_A_SESS_VLD 3
/* USBx_IF_USB_SUSP_CTRL_0 */
#define UTMIP_PHY_ENB (1 << 12)
#define UTMIP_RESET (1 << 11)
#define USB_PHY_CLK_VALID (1 << 7)
#define USB_SUSP_CLR (1 << 5)
#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
/* USB2_IF_USB_SUSP_CTRL_0 */
#define ULPI_PHY_ENB (1 << 13)
/* USB2_IF_ULPI_TIMING_CTRL_0 */
#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
/* USB2_IF_ULPI_TIMING_CTRL_1 */
#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
#endif
/* USBx_UTMIP_MISC_CFG0 */
#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
/* USBx_UTMIP_MISC_CFG1 */
#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
/*
* Tegra 3 and later: Moved to Clock and Reset register space, see
* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
*/
#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
#define UTMIP_PLLU_STABLE_COUNT_MASK \
(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
/*
* Tegra 3 and later: Moved to Clock and Reset register space, see
* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
*/
#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
/* USBx_UTMIP_PLL_CFG1_0 */
/* Tegra 3 and later: Moved to Clock and Reset register space */
#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
/* USBx_UTMIP_BIAS_CFG0_0 */
#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
#define UTMIP_OTGPD (1 << 11)
#define UTMIP_BIASPD (1 << 10)
#define UTMIP_HSDISCON_LEVEL_SHIFT 2
#define UTMIP_HSDISCON_LEVEL_MASK \
(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
#define UTMIP_HSSQUELCH_LEVEL_MASK \
(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
/* USBx_UTMIP_BIAS_CFG1_0 */
#define UTMIP_FORCE_PDTRK_POWERDOWN 1
#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8
#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \
(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
#define UTMIP_BIAS_PDTRK_COUNT_MASK \
(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
/* USBx_UTMIP_TX_CFG0_0 */
#define UTMIP_FS_PREAMBLE_J (1 << 19)
/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
#define UTMIP_PD_CHRG 1
/* USBx_UTMIP_SPARE_CFG0_0 */
#define FUSE_SETUP_SEL (1 << 3)
/* USBx_UTMIP_HSRX_CFG0_0 */
#define UTMIP_IDLE_WAIT_SHIFT 15
#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
#define UTMIP_ELASTIC_LIMIT_SHIFT 10
#define UTMIP_ELASTIC_LIMIT_MASK \
(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
/* USBx_UTMIP_HSRX_CFG1_0 */
#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
#define UTMIP_HS_SYNC_START_DLY_MASK \
(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
#define IC_ENB1 (1 << 3)
#ifdef CONFIG_TEGRA20
/* PORTSC1, USB1 */
#define PTS1_SHIFT 31
#define PTS1_MASK (1 << PTS1_SHIFT)
#define STS1 (1 << 30)
/* PORTSC, USB2, USB3 */
#define PTS_SHIFT 30
#define PTS_MASK (3U << PTS_SHIFT)
#define STS (1 << 29)
#else
/* USB2D_HOSTPC1_DEVLC_0 */
#define PTS_SHIFT 29
#define PTS_MASK (0x7U << PTS_SHIFT)
#define STS (1 << 28)
#endif
#define PTS_UTMI 0
#define PTS_RESERVED 1
#define PTS_ULPI 2
#define PTS_ICUSB_SER 3
#define PTS_HSIC 4
/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
#define WKOC (1 << 22)
#define WKDS (1 << 21)
#define WKCN (1 << 20)
/* USBx_UTMIP_XCVR_CFG0_0 */
#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
#define UTMIP_XCVR_HSSLEW_MSB_MASK \
(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
#define UTMIP_XCVR_SETUP_SHIFT 0
#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
/* USBx_UTMIP_XCVR_CFG1_0 */
#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
#define VBUS_VLD_STS (1 << 26)
#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12)
#define VBUS_B_SESS_VLD_SW_EN (1 << 11)
/* Setup USB on the board */
int usb_process_devicetree(const void *blob);
#endif /* _TEGRA_USB_H_ */

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/*
* (C) Copyright 2010, 2011
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _WARM_BOOT_H_
#define _WARM_BOOT_H_
#define STRAP_OPT_A_RAM_CODE_SHIFT 4
#define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
/* Defines the supported operating modes */
enum fuse_operating_mode {
MODE_PRODUCTION = 3,
MODE_UNDEFINED,
};
/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
enum {
HASH_LENGTH = 4
};
/* Defines the storage for a hash value (128 bits) */
struct hash {
u32 hash[HASH_LENGTH];
};
/*
* Defines the code header information for the boot rom.
*
* The code immediately follows the code header.
*
* Note that the code header needs to be 16 bytes aligned to preserve
* the alignment of relevant data for hash and decryption computations without
* requiring extra copies to temporary memory areas.
*/
struct wb_header {
u32 length_insecure; /* length of the code header */
u32 reserved[3];
struct hash hash; /* hash of header+code, starts next field*/
struct hash random_aes_block; /* a data block to aid security. */
u32 length_secure; /* length of the code header */
u32 destination; /* destination address to put the wb code */
u32 entry_point; /* execution address of the wb code */
u32 code_length; /* length of the code */
};
/*
* The warm boot code needs direct access to these registers since it runs in
* SRAM and cannot call other U-Boot code.
*/
union osc_ctrl_reg {
struct {
u32 xoe:1;
u32 xobp:1;
u32 reserved0:2;
u32 xofs:6;
u32 reserved1:2;
u32 xods:5;
u32 reserved2:3;
u32 oscfi_spare:8;
u32 pll_ref_div:2;
u32 osc_freq:2;
};
u32 word;
};
union pllx_base_reg {
struct {
u32 divm:5;
u32 reserved0:3;
u32 divn:10;
u32 reserved1:2;
u32 divp:3;
u32 reserved2:4;
u32 lock:1;
u32 reserved3:1;
u32 ref_dis:1;
u32 enable:1;
u32 bypass:1;
};
u32 word;
};
union pllx_misc_reg {
struct {
u32 vcocon:4;
u32 lfcon:4;
u32 cpcon:4;
u32 lock_sel:6;
u32 reserved0:1;
u32 lock_enable:1;
u32 reserved1:1;
u32 dccon:1;
u32 pts:2;
u32 reserved2:6;
u32 out1_div_byp:1;
u32 out1_inv_clk:1;
};
u32 word;
};
/*
* TODO: This register is not documented in the TRM yet. We could move this
* into the EMC and give it a proper interface, but not while it is
* undocumented.
*/
union scratch3_reg {
struct {
u32 pllx_base_divm:5;
u32 pllx_base_divn:10;
u32 pllx_base_divp:3;
u32 pllx_misc_lfcon:4;
u32 pllx_misc_cpcon:4;
};
u32 word;
};
/**
* Save warmboot memory settings for a later resume
*
* @return 0 if ok, -1 on error
*/
int warmboot_save_sdram_params(void);
int warmboot_prepare_code(u32 seg_address, u32 seg_length);
int sign_data_block(u8 *source, u32 length, u8 *signature);
void wb_start(void); /* Start of WB assembly code */
void wb_end(void); /* End of WB assembly code */
#endif

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/*
* Copyright 2016 Avionic Design GmbH
* Copyright 2016 Julian Scheel <julian@jusst.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_WDT_H_
#define _TEGRA_WDT_H_
struct wdt_ctrl {
u32 config;
u32 status;
u32 command;
u32 unlock;
};
#define WDT_CFG_SOURCE_MASK 0xf
#define WDT_CFG_PERIOD_SHIFT 4
#define WDT_CFG_PERIOD_MASK (0xff << WDT_CFG_PERIOD_SHIFT)
#define WDT_CFG_PMC2CAR_RST_EN (1 << 15)
#define WDT_STS_COUNT_SHIFT 4
#define WDT_STS_COUNT_MASK (0xff << WDT_STS_COUNT_SHIFT)
#define WDT_CMD_START_COUNTER (1 << 0)
#define WDT_CMD_DISABLE_COUNTER (1 << 1)
#define WDT_UNLOCK_PATTERN 0xc45a
/* Timer registers */
struct timer_ctrl {
u32 ptv;
};
#define TIMER_PTV_EN (1 << 31)
#define TIMER_PTV_PERIODIC (1 << 30)
#endif /* _TEGRA_WDT_H_ */

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#ifndef _TEGRA_XUSB_PADCTL_H_
#define _TEGRA_XUSB_PADCTL_H_
struct tegra_xusb_phy;
/**
* tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
* @type: the type of PHY to obtain
*
* The type of PHY varies between SoC generations. Typically there are XUSB,
* PCIe and SATA PHYs, though not all generations support all of them. The
* value of type can usually be directly parsed from a device tree.
*
* Return: a pointer to the PHY or NULL if no such PHY exists
*/
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
void tegra_xusb_padctl_init(const void *fdt);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);
#endif