avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
70
u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h
Normal file
70
u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h
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@@ -0,0 +1,70 @@
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/*
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* am35x_def.h - TI's AM35x specific definitions.
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*
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* Based on arch/arm/include/asm/arch-omap3/cpu.h
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*
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* Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
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*
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* Copyright (c) 2010 Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _AM35X_DEF_H_
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#define _AM35X_DEF_H_
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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/* LVL_INTR_CLEAR bits */
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#define USBOTGSS_INT_CLR (1 << 4)
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/* IP_SW_RESET bits */
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#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */
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#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */
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/* DEVCONF2 bits */
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#define CONF2_PHY_GPIOMODE (1 << 23)
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#define CONF2_OTGMODE (3 << 14)
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#define CONF2_NO_OVERRIDE (0 << 14)
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#define CONF2_FORCE_HOST (1 << 14)
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#define CONF2_FORCE_DEVICE (2 << 14)
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#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
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#define CONF2_SESENDEN (1 << 13)
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#define CONF2_VBDTCTEN (1 << 12)
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#define CONF2_REFFREQ_24MHZ (2 << 8)
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#define CONF2_REFFREQ_26MHZ (7 << 8)
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#define CONF2_REFFREQ_13MHZ (6 << 8)
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#define CONF2_REFFREQ (0xf << 8)
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#define CONF2_PHYCLKGD (1 << 7)
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#define CONF2_VBUSSENSE (1 << 6)
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#define CONF2_PHY_PLLON (1 << 5)
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#define CONF2_RESET (1 << 4)
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#define CONF2_PHYPWRDN (1 << 3)
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#define CONF2_OTGPWRDN (1 << 2)
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#define CONF2_DATPOL (1 << 1)
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/* General register mappings of system control module */
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#define AM35X_SCM_GEN_BASE 0x48002270
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struct am35x_scm_general {
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u32 res1[0xC4]; /* 0x000 - 0x30C */
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u32 devconf2; /* 0x310 */
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u32 devconf3; /* 0x314 */
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u32 res2[0x2]; /* 0x318 - 0x31C */
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u32 cba_priority; /* 0x320 */
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u32 lvl_intr_clr; /* 0x324 */
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u32 ip_sw_reset; /* 0x328 */
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u32 ipss_clk_ctrl; /* 0x32C */
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};
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#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
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#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
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#endif /*__ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#endif /* _AM35X_DEF_H_ */
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64
u-boot/arch/arm/include/asm/arch-omap3/clock.h
Normal file
64
u-boot/arch/arm/include/asm/arch-omap3/clock.h
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@@ -0,0 +1,64 @@
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCKS_H_
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#define _CLOCKS_H_
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#define LDELAY 12000000
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#define S12M 12000000
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#define S13M 13000000
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#define S19_2M 19200000
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#define S24M 24000000
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#define S26M 26000000
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#define S38_4M 38400000
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#define FCK_IVA2_ON 0x00000001
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#define FCK_CORE1_ON 0x03fffe29
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#define ICK_CORE1_ON 0x3ffffffb
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#define ICK_CORE2_ON 0x0000001f
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#define FCK_WKUP_ON 0x000000e9
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#define ICK_WKUP_ON 0x0000003f
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#define FCK_DSS_ON 0x00000005
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#define ICK_DSS_ON 0x00000001
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#define FCK_CAM_ON 0x00000001
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#define ICK_CAM_ON 0x00000001
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/* Used to index into DPLL parameter tables */
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typedef struct {
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unsigned int m;
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unsigned int n;
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unsigned int fsel;
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unsigned int m2;
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} dpll_param;
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struct dpll_per_36x_param {
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unsigned int sys_clk;
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unsigned int m;
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unsigned int n;
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unsigned int m2;
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unsigned int m3;
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unsigned int m4;
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unsigned int m5;
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unsigned int m6;
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unsigned int m2div;
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};
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/* Following functions are exported from lowlevel_init.S */
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extern dpll_param *get_mpu_dpll_param(void);
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extern dpll_param *get_iva_dpll_param(void);
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extern dpll_param *get_core_dpll_param(void);
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extern dpll_param *get_per_dpll_param(void);
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extern dpll_param *get_per2_dpll_param(void);
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extern dpll_param *get_36x_mpu_dpll_param(void);
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extern dpll_param *get_36x_iva_dpll_param(void);
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extern dpll_param *get_36x_core_dpll_param(void);
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extern dpll_param *get_36x_per_dpll_param(void);
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extern dpll_param *get_36x_per2_dpll_param(void);
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#endif
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348
u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h
Normal file
348
u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h
Normal file
@@ -0,0 +1,348 @@
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCKS_OMAP3_H_
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#define _CLOCKS_OMAP3_H_
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#define PLL_STOP 1 /* PER & IVA */
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#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
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#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
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#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
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/*
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* The following configurations are OPP and SysClk value independant
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* and hence are defined here. All the other DPLL related values are
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* tabulated in lowlevel_init.S.
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*/
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/* CORE DPLL */
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#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
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#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
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#define CORE_FUSB_DIV 2 /* 41.5MHz: */
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#define CORE_L4_DIV 2 /* 83MHz : L4 */
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#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
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#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
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#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */
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#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
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/* PER DPLL */
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#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
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#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
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#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
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#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
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#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
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/* MPU DPLL */
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#define MPU_M_12_ES1 0x0FE
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#define MPU_N_12_ES1 0x07
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#define MPU_FSEL_12_ES1 0x05
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#define MPU_M2_12_ES1 0x01
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#define MPU_M_12_ES2 0x0FA
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#define MPU_N_12_ES2 0x05
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#define MPU_FSEL_12_ES2 0x07
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#define MPU_M2_ES2 0x01
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#define MPU_M_12 0x085
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#define MPU_N_12 0x05
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#define MPU_FSEL_12 0x07
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#define MPU_M2_12 0x01
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#define MPU_M_13_ES1 0x17D
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#define MPU_N_13_ES1 0x0C
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#define MPU_FSEL_13_ES1 0x03
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#define MPU_M2_13_ES1 0x01
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#define MPU_M_13_ES2 0x258
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#define MPU_N_13_ES2 0x0C
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#define MPU_FSEL_13_ES2 0x03
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#define MPU_M2_13_ES2 0x01
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#define MPU_M_13 0x10A
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#define MPU_N_13 0x0C
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#define MPU_FSEL_13 0x03
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#define MPU_M2_13 0x01
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#define MPU_M_19P2_ES1 0x179
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#define MPU_N_19P2_ES1 0x12
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#define MPU_FSEL_19P2_ES1 0x04
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#define MPU_M2_19P2_ES1 0x01
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#define MPU_M_19P2_ES2 0x271
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#define MPU_N_19P2_ES2 0x17
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#define MPU_FSEL_19P2_ES2 0x03
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#define MPU_M2_19P2_ES2 0x01
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#define MPU_M_19P2 0x14C
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#define MPU_N_19P2 0x17
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#define MPU_FSEL_19P2 0x03
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#define MPU_M2_19P2 0x01
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#define MPU_M_26_ES1 0x17D
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#define MPU_N_26_ES1 0x19
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#define MPU_FSEL_26_ES1 0x03
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#define MPU_M2_26_ES1 0x01
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#define MPU_M_26_ES2 0x0FA
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#define MPU_N_26_ES2 0x0C
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#define MPU_FSEL_26_ES2 0x07
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#define MPU_M2_26_ES2 0x01
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#define MPU_M_26 0x085
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#define MPU_N_26 0x0C
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#define MPU_FSEL_26 0x07
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#define MPU_M2_26 0x01
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#define MPU_M_38P4_ES1 0x1FA
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#define MPU_N_38P4_ES1 0x32
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#define MPU_FSEL_38P4_ES1 0x03
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#define MPU_M2_38P4_ES1 0x01
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#define MPU_M_38P4_ES2 0x271
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#define MPU_N_38P4_ES2 0x2F
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#define MPU_FSEL_38P4_ES2 0x03
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#define MPU_M2_38P4_ES2 0x01
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#define MPU_M_38P4 0x14C
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#define MPU_N_38P4 0x2F
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#define MPU_FSEL_38P4 0x03
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#define MPU_M2_38P4 0x01
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/* IVA DPLL */
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#define IVA_M_12_ES1 0x07D
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#define IVA_N_12_ES1 0x05
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#define IVA_FSEL_12_ES1 0x07
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#define IVA_M2_12_ES1 0x01
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#define IVA_M_12_ES2 0x0B4
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#define IVA_N_12_ES2 0x05
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#define IVA_FSEL_12_ES2 0x07
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#define IVA_M2_12_ES2 0x01
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#define IVA_M_12 0x085
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#define IVA_N_12 0x05
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#define IVA_FSEL_12 0x07
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#define IVA_M2_12 0x01
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#define IVA_M_13_ES1 0x0FA
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#define IVA_N_13_ES1 0x0C
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#define IVA_FSEL_13_ES1 0x03
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#define IVA_M2_13_ES1 0x01
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#define IVA_M_13_ES2 0x168
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#define IVA_N_13_ES2 0x0C
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#define IVA_FSEL_13_ES2 0x03
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#define IVA_M2_13_ES2 0x01
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#define IVA_M_13 0x10A
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#define IVA_N_13 0x0C
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#define IVA_FSEL_13 0x03
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#define IVA_M2_13 0x01
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#define IVA_M_19P2_ES1 0x082
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#define IVA_N_19P2_ES1 0x09
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#define IVA_FSEL_19P2_ES1 0x07
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#define IVA_M2_19P2_ES1 0x01
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#define IVA_M_19P2_ES2 0x0E1
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#define IVA_N_19P2_ES2 0x0B
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#define IVA_FSEL_19P2_ES2 0x06
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#define IVA_M2_19P2_ES2 0x01
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#define IVA_M_19P2 0x14C
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#define IVA_N_19P2 0x17
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#define IVA_FSEL_19P2 0x03
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#define IVA_M2_19P2 0x01
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|
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#define IVA_M_26_ES1 0x07D
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#define IVA_N_26_ES1 0x0C
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#define IVA_FSEL_26_ES1 0x07
|
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#define IVA_M2_26_ES1 0x01
|
||||
|
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#define IVA_M_26_ES2 0x0B4
|
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#define IVA_N_26_ES2 0x0C
|
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#define IVA_FSEL_26_ES2 0x07
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#define IVA_M2_26_ES2 0x01
|
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|
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#define IVA_M_26 0x085
|
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#define IVA_N_26 0x0C
|
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#define IVA_FSEL_26 0x07
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#define IVA_M2_26 0x01
|
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|
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#define IVA_M_38P4_ES1 0x13F
|
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#define IVA_N_38P4_ES1 0x30
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#define IVA_FSEL_38P4_ES1 0x03
|
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#define IVA_M2_38P4_ES1 0x01
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|
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#define IVA_M_38P4_ES2 0x0E1
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#define IVA_N_38P4_ES2 0x17
|
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#define IVA_FSEL_38P4_ES2 0x06
|
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#define IVA_M2_38P4_ES2 0x01
|
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|
||||
#define IVA_M_38P4 0x14C
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#define IVA_N_38P4 0x2F
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||||
#define IVA_FSEL_38P4 0x03
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||||
#define IVA_M2_38P4 0x01
|
||||
|
||||
/* CORE DPLL */
|
||||
|
||||
#define CORE_M_12 0xA6
|
||||
#define CORE_N_12 0x05
|
||||
#define CORE_FSEL_12 0x07
|
||||
#define CORE_M2_12 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_12_ES1 0x19F
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||||
#define CORE_N_12_ES1 0x0E
|
||||
#define CORE_FSL_12_ES1 0x03
|
||||
#define CORE_M2_12_ES1 0x1 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_13 0x14C
|
||||
#define CORE_N_13 0x0C
|
||||
#define CORE_FSEL_13 0x03
|
||||
#define CORE_M2_13 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_13_ES1 0x1B2
|
||||
#define CORE_N_13_ES1 0x10
|
||||
#define CORE_FSL_13_ES1 0x03
|
||||
#define CORE_M2_13_ES1 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_19P2 0x19F
|
||||
#define CORE_N_19P2 0x17
|
||||
#define CORE_FSEL_19P2 0x03
|
||||
#define CORE_M2_19P2 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_19P2_ES1 0x19F
|
||||
#define CORE_N_19P2_ES1 0x17
|
||||
#define CORE_FSL_19P2_ES1 0x03
|
||||
#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_26 0xA6
|
||||
#define CORE_N_26 0x0C
|
||||
#define CORE_FSEL_26 0x07
|
||||
#define CORE_M2_26 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_26_ES1 0x1B2
|
||||
#define CORE_N_26_ES1 0x21
|
||||
#define CORE_FSL_26_ES1 0x03
|
||||
#define CORE_M2_26_ES1 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_38P4 0x19F
|
||||
#define CORE_N_38P4 0x2F
|
||||
#define CORE_FSEL_38P4 0x03
|
||||
#define CORE_M2_38P4 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_38P4_ES1 0x19F
|
||||
#define CORE_N_38P4_ES1 0x2F
|
||||
#define CORE_FSL_38P4_ES1 0x03
|
||||
#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
|
||||
|
||||
/* PER DPLL */
|
||||
|
||||
#define PER_M_12 0xD8
|
||||
#define PER_N_12 0x05
|
||||
#define PER_FSEL_12 0x07
|
||||
#define PER_M2_12 0x09
|
||||
|
||||
#define PER_M_13 0x1B0
|
||||
#define PER_N_13 0x0C
|
||||
#define PER_FSEL_13 0x03
|
||||
#define PER_M2_13 0x09
|
||||
|
||||
#define PER_M_19P2 0xE1
|
||||
#define PER_N_19P2 0x09
|
||||
#define PER_FSEL_19P2 0x07
|
||||
#define PER_M2_19P2 0x09
|
||||
|
||||
#define PER_M_26 0xD8
|
||||
#define PER_N_26 0x0C
|
||||
#define PER_FSEL_26 0x07
|
||||
#define PER_M2_26 0x09
|
||||
|
||||
#define PER_M_38P4 0xE1
|
||||
#define PER_N_38P4 0x13
|
||||
#define PER_FSEL_38P4 0x07
|
||||
#define PER_M2_38P4 0x09
|
||||
|
||||
/* PER2 DPLL */
|
||||
#define PER2_M_12 0x78
|
||||
#define PER2_N_12 0x0B
|
||||
#define PER2_FSEL_12 0x03
|
||||
#define PER2_M2_12 0x01
|
||||
|
||||
#define PER2_M_13 0x78
|
||||
#define PER2_N_13 0x0C
|
||||
#define PER2_FSEL_13 0x03
|
||||
#define PER2_M2_13 0x01
|
||||
|
||||
#define PER2_M_19P2 0x2EE
|
||||
#define PER2_N_19P2 0x0B
|
||||
#define PER2_FSEL_19P2 0x06
|
||||
#define PER2_M2_19P2 0x0A
|
||||
|
||||
#define PER2_M_26 0x78
|
||||
#define PER2_N_26 0x0C
|
||||
#define PER2_FSEL_26 0x03
|
||||
#define PER2_M2_26 0x01
|
||||
|
||||
#define PER2_M_38P4 0x2EE
|
||||
#define PER2_N_38P4 0x0B
|
||||
#define PER2_FSEL_38P4 0x06
|
||||
#define PER2_M2_38P4 0x0A
|
||||
|
||||
/* 36XX PER DPLL */
|
||||
|
||||
#define PER_36XX_M_12 0x1B0
|
||||
#define PER_36XX_N_12 0x05
|
||||
#define PER_36XX_FSEL_12 0x07
|
||||
#define PER_36XX_M2_12 0x09
|
||||
|
||||
#define PER_36XX_M_13 0x360
|
||||
#define PER_36XX_N_13 0x0C
|
||||
#define PER_36XX_FSEL_13 0x03
|
||||
#define PER_36XX_M2_13 0x09
|
||||
|
||||
#define PER_36XX_M_19P2 0x1C2
|
||||
#define PER_36XX_N_19P2 0x09
|
||||
#define PER_36XX_FSEL_19P2 0x07
|
||||
#define PER_36XX_M2_19P2 0x09
|
||||
|
||||
#define PER_36XX_M_26 0x1B0
|
||||
#define PER_36XX_N_26 0x0C
|
||||
#define PER_36XX_FSEL_26 0x07
|
||||
#define PER_36XX_M2_26 0x09
|
||||
|
||||
#define PER_36XX_M_38P4 0x1C2
|
||||
#define PER_36XX_N_38P4 0x13
|
||||
#define PER_36XX_FSEL_38P4 0x07
|
||||
#define PER_36XX_M2_38P4 0x09
|
||||
|
||||
/* 36XX PER2 DPLL */
|
||||
|
||||
#define PER2_36XX_M_12 0x50
|
||||
#define PER2_36XX_N_12 0x00
|
||||
#define PER2_36XX_M2_12 0x08
|
||||
|
||||
#define PER2_36XX_M_13 0x1BB
|
||||
#define PER2_36XX_N_13 0x05
|
||||
#define PER2_36XX_M2_13 0x08
|
||||
|
||||
#define PER2_36XX_M_19P2 0x32
|
||||
#define PER2_36XX_N_19P2 0x00
|
||||
#define PER2_36XX_M2_19P2 0x08
|
||||
|
||||
#define PER2_36XX_M_26 0x1BB
|
||||
#define PER2_36XX_N_26 0x0B
|
||||
#define PER2_36XX_M2_26 0x08
|
||||
|
||||
#define PER2_36XX_M_38P4 0x19
|
||||
#define PER2_36XX_N_38P4 0x00
|
||||
#define PER2_36XX_M2_38P4 0x08
|
||||
|
||||
#endif /* endif _CLOCKS_OMAP3_H_ */
|
||||
505
u-boot/arch/arm/include/asm/arch-omap3/cpu.h
Normal file
505
u-boot/arch/arm/include/asm/arch-omap3/cpu.h
Normal file
@@ -0,0 +1,505 @@
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _CPU_H
|
||||
#define _CPU_H
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
|
||||
|
||||
/* Register offsets of common modules */
|
||||
/* Control */
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct ctrl {
|
||||
u8 res1[0xC0];
|
||||
u16 gpmc_nadv_ale; /* 0xC0 */
|
||||
u16 gpmc_noe; /* 0xC2 */
|
||||
u16 gpmc_nwe; /* 0xC4 */
|
||||
u8 res2[0x22A];
|
||||
u32 status; /* 0x2F0 */
|
||||
u32 gpstatus; /* 0x2F4 */
|
||||
u8 res3[0x08];
|
||||
u32 rpubkey_0; /* 0x300 */
|
||||
u32 rpubkey_1; /* 0x304 */
|
||||
u32 rpubkey_2; /* 0x308 */
|
||||
u32 rpubkey_3; /* 0x30C */
|
||||
u32 rpubkey_4; /* 0x310 */
|
||||
u8 res4[0x04];
|
||||
u32 randkey_0; /* 0x318 */
|
||||
u32 randkey_1; /* 0x31C */
|
||||
u32 randkey_2; /* 0x320 */
|
||||
u32 randkey_3; /* 0x324 */
|
||||
u8 res5[0x124];
|
||||
u32 ctrl_omap_stat; /* 0x44C */
|
||||
};
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define CONTROL_STATUS 0x2F0
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct ctrl_id {
|
||||
u8 res1[0x4];
|
||||
u32 idcode; /* 0x04 */
|
||||
u32 prod_id; /* 0x08 */
|
||||
u32 sku_id; /* 0x0c */
|
||||
u8 res2[0x08];
|
||||
u32 die_id_0; /* 0x18 */
|
||||
u32 die_id_1; /* 0x1C */
|
||||
u32 die_id_2; /* 0x20 */
|
||||
u32 die_id_3; /* 0x24 */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
/* boot pin mask */
|
||||
#define SYSBOOT_MASK 0x1F
|
||||
|
||||
/* device speed */
|
||||
#define SKUID_CLK_MASK 0xf
|
||||
#define SKUID_CLK_600MHZ 0x0
|
||||
#define SKUID_CLK_720MHZ 0x8
|
||||
|
||||
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
|
||||
#define GPMC_CONFIG_CS0 0x60
|
||||
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifdef __ASSEMBLY__
|
||||
#define GPMC_CONFIG1 0x00
|
||||
#define GPMC_CONFIG2 0x04
|
||||
#define GPMC_CONFIG3 0x08
|
||||
#define GPMC_CONFIG4 0x0C
|
||||
#define GPMC_CONFIG5 0x10
|
||||
#define GPMC_CONFIG6 0x14
|
||||
#define GPMC_CONFIG7 0x18
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
/* GPMC Mapping */
|
||||
#define FLASH_BASE 0x10000000 /* NOR flash, */
|
||||
/* aligned to 256 Meg */
|
||||
#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
|
||||
/* aligned to 64 Meg */
|
||||
#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
|
||||
/* aligned to 256 Meg */
|
||||
#define DEBUG_BASE 0x08000000 /* debug board */
|
||||
#define NAND_BASE 0x30000000 /* NAND addr */
|
||||
/* (actual size small port) */
|
||||
#define ONENAND_MAP 0x20000000 /* OneNand addr */
|
||||
/* (actual size small port) */
|
||||
/* SMS */
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct sms {
|
||||
u8 res1[0x10];
|
||||
u32 sysconfig; /* 0x10 */
|
||||
u8 res2[0x34];
|
||||
u32 rg_att0; /* 0x48 */
|
||||
u8 res3[0x84];
|
||||
u32 class_arb0; /* 0xD0 */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
|
||||
|
||||
/* SDRC */
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct sdrc_cs {
|
||||
u32 mcfg; /* 0x80 || 0xB0 */
|
||||
u32 mr; /* 0x84 || 0xB4 */
|
||||
u8 res1[0x4];
|
||||
u32 emr2; /* 0x8C || 0xBC */
|
||||
u8 res2[0x14];
|
||||
u32 rfr_ctrl; /* 0x84 || 0xD4 */
|
||||
u32 manual; /* 0xA8 || 0xD8 */
|
||||
u8 res3[0x4];
|
||||
};
|
||||
|
||||
struct sdrc_actim {
|
||||
u32 ctrla; /* 0x9C || 0xC4 */
|
||||
u32 ctrlb; /* 0xA0 || 0xC8 */
|
||||
};
|
||||
|
||||
struct sdrc {
|
||||
u8 res1[0x10];
|
||||
u32 sysconfig; /* 0x10 */
|
||||
u32 status; /* 0x14 */
|
||||
u8 res2[0x28];
|
||||
u32 cs_cfg; /* 0x40 */
|
||||
u32 sharing; /* 0x44 */
|
||||
u8 res3[0x18];
|
||||
u32 dlla_ctrl; /* 0x60 */
|
||||
u32 dlla_status; /* 0x64 */
|
||||
u32 dllb_ctrl; /* 0x68 */
|
||||
u32 dllb_status; /* 0x6C */
|
||||
u32 power; /* 0x70 */
|
||||
u8 res4[0xC];
|
||||
struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
|
||||
};
|
||||
|
||||
/* EMIF4 */
|
||||
typedef struct emif4 {
|
||||
unsigned int emif_mod_id_rev;
|
||||
unsigned int sdram_sts;
|
||||
unsigned int sdram_config;
|
||||
unsigned int res1;
|
||||
unsigned int sdram_refresh_ctrl;
|
||||
unsigned int sdram_refresh_ctrl_shdw;
|
||||
unsigned int sdram_time1;
|
||||
unsigned int sdram_time1_shdw;
|
||||
unsigned int sdram_time2;
|
||||
unsigned int sdram_time2_shdw;
|
||||
unsigned int sdram_time3;
|
||||
unsigned int sdram_time3_shdw;
|
||||
unsigned char res2[8];
|
||||
unsigned int sdram_pwr_mgmt;
|
||||
unsigned int sdram_pwr_mgmt_shdw;
|
||||
unsigned char res3[32];
|
||||
unsigned int sdram_iodft_tlgc;
|
||||
unsigned char res4[128];
|
||||
unsigned int ddr_phyctrl1;
|
||||
unsigned int ddr_phyctrl1_shdw;
|
||||
unsigned int ddr_phyctrl2;
|
||||
} emif4_t;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#define DLLPHASE_90 (0x1 << 1)
|
||||
#define LOADDLL (0x1 << 2)
|
||||
#define ENADLL (0x1 << 3)
|
||||
#define DLL_DELAY_MASK 0xFF00
|
||||
#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
|
||||
|
||||
#define PAGEPOLICY_HIGH (0x1 << 0)
|
||||
#define SRFRONRESET (0x1 << 7)
|
||||
#define PWDNEN (0x1 << 2)
|
||||
#define WAKEUPPROC (0x1 << 26)
|
||||
|
||||
#define DDR_SDRAM (0x1 << 0)
|
||||
#define DEEPPD (0x1 << 3)
|
||||
#define B32NOT16 (0x1 << 4)
|
||||
#define BANKALLOCATION (0x2 << 6)
|
||||
#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
|
||||
#define ADDRMUXLEGACY (0x1 << 19)
|
||||
#define CASWIDTH_10BITS (0x5 << 20)
|
||||
#define RASWIDTH_13BITS (0x2 << 24)
|
||||
#define BURSTLENGTH4 (0x2 << 0)
|
||||
#define CASL3 (0x3 << 4)
|
||||
#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
|
||||
#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
|
||||
#define ARE_ARCV_1 (0x1 << 0)
|
||||
#define ARCV (0x4e2 << 8) /* Autorefresh count */
|
||||
#define OMAP34XX_SDRC_CS0 0x80000000
|
||||
#define OMAP34XX_SDRC_CS1 0xA0000000
|
||||
#define CMD_NOP 0x0
|
||||
#define CMD_PRECHARGE 0x1
|
||||
#define CMD_AUTOREFRESH 0x2
|
||||
#define CMD_ENTR_PWRDOWN 0x3
|
||||
#define CMD_EXIT_PWRDOWN 0x4
|
||||
#define CMD_ENTR_SRFRSH 0x5
|
||||
#define CMD_CKE_HIGH 0x6
|
||||
#define CMD_CKE_LOW 0x7
|
||||
#define SOFTRESET (0x1 << 1)
|
||||
#define SMART_IDLE (0x2 << 3)
|
||||
#define REF_ON_IDLE (0x1 << 6)
|
||||
|
||||
/* DMA */
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct dma4_chan {
|
||||
u32 ccr;
|
||||
u32 clnk_ctrl;
|
||||
u32 cicr;
|
||||
u32 csr;
|
||||
u32 csdp;
|
||||
u32 cen;
|
||||
u32 cfn;
|
||||
u32 cssa;
|
||||
u32 cdsa;
|
||||
u32 csel;
|
||||
u32 csfl;
|
||||
u32 cdel;
|
||||
u32 cdfl;
|
||||
u32 csac;
|
||||
u32 cdac;
|
||||
u32 ccen;
|
||||
u32 ccfn;
|
||||
u32 color;
|
||||
};
|
||||
|
||||
struct dma4 {
|
||||
u32 revision;
|
||||
u8 res1[0x4];
|
||||
u32 irqstatus_l[0x4];
|
||||
u32 irqenable_l[0x4];
|
||||
u32 sysstatus;
|
||||
u32 ocp_sysconfig;
|
||||
u8 res2[0x34];
|
||||
u32 caps_0;
|
||||
u8 res3[0x4];
|
||||
u32 caps_2;
|
||||
u32 caps_3;
|
||||
u32 caps_4;
|
||||
u32 gcr;
|
||||
u8 res4[0x4];
|
||||
struct dma4_chan chan[32];
|
||||
};
|
||||
|
||||
#endif /*__ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
/* timer regs offsets (32 bit regs) */
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gptimer {
|
||||
u32 tidr; /* 0x00 r */
|
||||
u8 res[0xc];
|
||||
u32 tiocp_cfg; /* 0x10 rw */
|
||||
u32 tistat; /* 0x14 r */
|
||||
u32 tisr; /* 0x18 rw */
|
||||
u32 tier; /* 0x1c rw */
|
||||
u32 twer; /* 0x20 rw */
|
||||
u32 tclr; /* 0x24 rw */
|
||||
u32 tcrr; /* 0x28 rw */
|
||||
u32 tldr; /* 0x2c rw */
|
||||
u32 ttgr; /* 0x30 rw */
|
||||
u32 twpc; /* 0x34 r*/
|
||||
u32 tmar; /* 0x38 rw*/
|
||||
u32 tcar1; /* 0x3c r */
|
||||
u32 tcicr; /* 0x40 rw */
|
||||
u32 tcar2; /* 0x44 r */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
/* enable sys_clk NO-prescale /1 */
|
||||
#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
|
||||
|
||||
/* Watchdog */
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct watchdog {
|
||||
u8 res1[0x34];
|
||||
u32 wwps; /* 0x34 r */
|
||||
u8 res2[0x10];
|
||||
u32 wspr; /* 0x48 rw */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#define WD_UNLOCK1 0xAAAA
|
||||
#define WD_UNLOCK2 0x5555
|
||||
|
||||
/* PRCM */
|
||||
#define PRCM_BASE 0x48004000
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct prcm {
|
||||
u32 fclken_iva2; /* 0x00 */
|
||||
u32 clken_pll_iva2; /* 0x04 */
|
||||
u8 res1[0x1c];
|
||||
u32 idlest_pll_iva2; /* 0x24 */
|
||||
u8 res2[0x18];
|
||||
u32 clksel1_pll_iva2 ; /* 0x40 */
|
||||
u32 clksel2_pll_iva2; /* 0x44 */
|
||||
u8 res3[0x8bc];
|
||||
u32 clken_pll_mpu; /* 0x904 */
|
||||
u8 res4[0x1c];
|
||||
u32 idlest_pll_mpu; /* 0x924 */
|
||||
u8 res5[0x18];
|
||||
u32 clksel1_pll_mpu; /* 0x940 */
|
||||
u32 clksel2_pll_mpu; /* 0x944 */
|
||||
u8 res6[0xb8];
|
||||
u32 fclken1_core; /* 0xa00 */
|
||||
u32 res_fclken2_core;
|
||||
u32 fclken3_core; /* 0xa08 */
|
||||
u8 res7[0x4];
|
||||
u32 iclken1_core; /* 0xa10 */
|
||||
u32 iclken2_core; /* 0xa14 */
|
||||
u32 iclken3_core; /* 0xa18 */
|
||||
u8 res8[0x24];
|
||||
u32 clksel_core; /* 0xa40 */
|
||||
u8 res9[0xbc];
|
||||
u32 fclken_gfx; /* 0xb00 */
|
||||
u8 res10[0xc];
|
||||
u32 iclken_gfx; /* 0xb10 */
|
||||
u8 res11[0x2c];
|
||||
u32 clksel_gfx; /* 0xb40 */
|
||||
u8 res12[0xbc];
|
||||
u32 fclken_wkup; /* 0xc00 */
|
||||
u8 res13[0xc];
|
||||
u32 iclken_wkup; /* 0xc10 */
|
||||
u8 res14[0xc];
|
||||
u32 idlest_wkup; /* 0xc20 */
|
||||
u8 res15[0x1c];
|
||||
u32 clksel_wkup; /* 0xc40 */
|
||||
u8 res16[0xbc];
|
||||
u32 clken_pll; /* 0xd00 */
|
||||
u32 clken2_pll; /* 0xd04 */
|
||||
u8 res17[0x18];
|
||||
u32 idlest_ckgen; /* 0xd20 */
|
||||
u32 idlest2_ckgen; /* 0xd24 */
|
||||
u8 res18[0x18];
|
||||
u32 clksel1_pll; /* 0xd40 */
|
||||
u32 clksel2_pll; /* 0xd44 */
|
||||
u32 clksel3_pll; /* 0xd48 */
|
||||
u32 clksel4_pll; /* 0xd4c */
|
||||
u32 clksel5_pll; /* 0xd50 */
|
||||
u8 res19[0xac];
|
||||
u32 fclken_dss; /* 0xe00 */
|
||||
u8 res20[0xc];
|
||||
u32 iclken_dss; /* 0xe10 */
|
||||
u8 res21[0x2c];
|
||||
u32 clksel_dss; /* 0xe40 */
|
||||
u8 res22[0xbc];
|
||||
u32 fclken_cam; /* 0xf00 */
|
||||
u8 res23[0xc];
|
||||
u32 iclken_cam; /* 0xf10 */
|
||||
u8 res24[0x2c];
|
||||
u32 clksel_cam; /* 0xf40 */
|
||||
u8 res25[0xbc];
|
||||
u32 fclken_per; /* 0x1000 */
|
||||
u8 res26[0xc];
|
||||
u32 iclken_per; /* 0x1010 */
|
||||
u8 res27[0x2c];
|
||||
u32 clksel_per; /* 0x1040 */
|
||||
u8 res28[0xfc];
|
||||
u32 clksel1_emu; /* 0x1140 */
|
||||
u8 res29[0x2bc];
|
||||
u32 fclken_usbhost; /* 0x1400 */
|
||||
u8 res30[0xc];
|
||||
u32 iclken_usbhost; /* 0x1410 */
|
||||
};
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define CM_CLKSEL_CORE 0x48004a40
|
||||
#define CM_CLKSEL_GFX 0x48004b40
|
||||
#define CM_CLKSEL_WKUP 0x48004c40
|
||||
#define CM_CLKEN_PLL 0x48004d00
|
||||
#define CM_CLKSEL1_PLL 0x48004d40
|
||||
#define CM_CLKSEL1_EMU 0x48005140
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#define PRM_BASE 0x48306000
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct prm {
|
||||
u8 res1[0xd40];
|
||||
u32 clksel; /* 0xd40 */
|
||||
u8 res2[0x50c];
|
||||
u32 rstctrl; /* 0x1250 */
|
||||
u8 res3[0x1c];
|
||||
u32 clksrc_ctrl; /* 0x1270 */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#define PRM_RSTCTRL 0x48307250
|
||||
#define PRM_RSTCTRL_RESET 0x04
|
||||
#define PRM_RSTST 0x48307258
|
||||
#define PRM_RSTST_WARM_RESET_MASK 0x7D2
|
||||
#define SYSCLKDIV_1 (0x1 << 6)
|
||||
#define SYSCLKDIV_2 (0x1 << 7)
|
||||
|
||||
#define CLKSEL_GPT1 (0x1 << 0)
|
||||
|
||||
#define EN_GPT1 (0x1 << 0)
|
||||
#define EN_32KSYNC (0x1 << 2)
|
||||
|
||||
#define ST_WDT2 (0x1 << 5)
|
||||
|
||||
#define ST_MPU_CLK (0x1 << 0)
|
||||
|
||||
#define ST_CORE_CLK (0x1 << 0)
|
||||
|
||||
#define ST_PERIPH_CLK (0x1 << 1)
|
||||
|
||||
#define ST_IVA2_CLK (0x1 << 0)
|
||||
|
||||
#define RESETDONE (0x1 << 0)
|
||||
|
||||
#define TCLR_ST (0x1 << 0)
|
||||
#define TCLR_AR (0x1 << 1)
|
||||
#define TCLR_PRE (0x1 << 5)
|
||||
|
||||
/* SMX-APE */
|
||||
#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
|
||||
#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
|
||||
#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
|
||||
#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct pm {
|
||||
u8 res1[0x48];
|
||||
u32 req_info_permission_0; /* 0x48 */
|
||||
u8 res2[0x4];
|
||||
u32 read_permission_0; /* 0x50 */
|
||||
u8 res3[0x4];
|
||||
u32 wirte_permission_0; /* 0x58 */
|
||||
u8 res4[0x4];
|
||||
u32 addr_match_1; /* 0x58 */
|
||||
u8 res5[0x4];
|
||||
u32 req_info_permission_1; /* 0x68 */
|
||||
u8 res6[0x14];
|
||||
u32 addr_match_2; /* 0x80 */
|
||||
};
|
||||
#endif /*__ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
/* Permission values for registers -Full fledged permissions to all */
|
||||
#define UNLOCK_1 0xFFFFFFFF
|
||||
#define UNLOCK_2 0x00000000
|
||||
#define UNLOCK_3 0x0000FFFF
|
||||
|
||||
#define NOT_EARLY 0
|
||||
|
||||
/* I2C base */
|
||||
#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
|
||||
#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
|
||||
#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
|
||||
|
||||
/* MUSB base */
|
||||
#define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
|
||||
|
||||
/* OMAP3 GPIO registers */
|
||||
#define OMAP_GPIO_REVISION 0x0000
|
||||
#define OMAP_GPIO_SYSCONFIG 0x0010
|
||||
#define OMAP_GPIO_SYSSTATUS 0x0014
|
||||
#define OMAP_GPIO_IRQSTATUS1 0x0018
|
||||
#define OMAP_GPIO_IRQSTATUS2 0x0028
|
||||
#define OMAP_GPIO_IRQENABLE2 0x002c
|
||||
#define OMAP_GPIO_IRQENABLE1 0x001c
|
||||
#define OMAP_GPIO_WAKE_EN 0x0020
|
||||
#define OMAP_GPIO_CTRL 0x0030
|
||||
#define OMAP_GPIO_OE 0x0034
|
||||
#define OMAP_GPIO_DATAIN 0x0038
|
||||
#define OMAP_GPIO_DATAOUT 0x003c
|
||||
#define OMAP_GPIO_LEVELDETECT0 0x0040
|
||||
#define OMAP_GPIO_LEVELDETECT1 0x0044
|
||||
#define OMAP_GPIO_RISINGDETECT 0x0048
|
||||
#define OMAP_GPIO_FALLINGDETECT 0x004c
|
||||
#define OMAP_GPIO_DEBOUNCE_EN 0x0050
|
||||
#define OMAP_GPIO_DEBOUNCE_VAL 0x0054
|
||||
#define OMAP_GPIO_CLEARIRQENABLE1 0x0060
|
||||
#define OMAP_GPIO_SETIRQENABLE1 0x0064
|
||||
#define OMAP_GPIO_CLEARWKUENA 0x0080
|
||||
#define OMAP_GPIO_SETWKUENA 0x0084
|
||||
#define OMAP_GPIO_CLEARDATAOUT 0x0090
|
||||
#define OMAP_GPIO_SETDATAOUT 0x0094
|
||||
|
||||
#endif /* _CPU_H */
|
||||
64
u-boot/arch/arm/include/asm/arch-omap3/dma.h
Normal file
64
u-boot/arch/arm/include/asm/arch-omap3/dma.h
Normal file
@@ -0,0 +1,64 @@
|
||||
#ifndef __SDMA_H
|
||||
#define __SDMA_H
|
||||
|
||||
/* Copyright (C) 2011
|
||||
* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/* Functions */
|
||||
void omap3_dma_init(void);
|
||||
int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
|
||||
uint32_t sze);
|
||||
int omap3_dma_start_transfer(uint32_t chan);
|
||||
int omap3_dma_wait_for_transfer(uint32_t chan);
|
||||
int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
|
||||
int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
|
||||
|
||||
/* Register settings */
|
||||
#define CSDP_DATA_TYPE_8BIT 0x0
|
||||
#define CSDP_DATA_TYPE_16BIT 0x1
|
||||
#define CSDP_DATA_TYPE_32BIT 0x2
|
||||
#define CSDP_SRC_BURST_SINGLE (0x0 << 7)
|
||||
#define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7)
|
||||
#define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7)
|
||||
#define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7)
|
||||
#define CSDP_DST_BURST_SINGLE (0x0 << 14)
|
||||
#define CSDP_DST_BURST_EN_16BYTES (0x1 << 14)
|
||||
#define CSDP_DST_BURST_EN_32BYTES (0x2 << 14)
|
||||
#define CSDP_DST_BURST_EN_64BYTES (0x3 << 14)
|
||||
#define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18)
|
||||
#define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18)
|
||||
#define CSDP_DST_ENDIAN_LITTLE (0x0 << 19)
|
||||
#define CSDP_DST_ENDIAN_BIG (0x1 << 19)
|
||||
#define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20)
|
||||
#define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20)
|
||||
#define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21)
|
||||
#define CSDP_SRC_ENDIAN_BIG (0x1 << 21)
|
||||
|
||||
#define CCR_READ_PRIORITY_LOW (0x0 << 6)
|
||||
#define CCR_READ_PRIORITY_HIGH (0x1 << 6)
|
||||
#define CCR_ENABLE_DISABLED (0x0 << 7)
|
||||
#define CCR_ENABLE_ENABLE (0x1 << 7)
|
||||
#define CCR_SRC_AMODE_CONSTANT (0x0 << 12)
|
||||
#define CCR_SRC_AMODE_POST_INC (0x1 << 12)
|
||||
#define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12)
|
||||
#define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12)
|
||||
#define CCR_DST_AMODE_CONSTANT (0x0 << 14)
|
||||
#define CCR_DST_AMODE_POST_INC (0x1 << 14)
|
||||
#define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14)
|
||||
#define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14)
|
||||
|
||||
#define CCR_RD_ACTIVE_MASK (1 << 9)
|
||||
#define CCR_WR_ACTIVE_MASK (1 << 10)
|
||||
|
||||
#define CSR_TRANS_ERR (1 << 8)
|
||||
#define CSR_SUPERVISOR_ERR (1 << 10)
|
||||
#define CSR_MISALIGNED_ADRS_ERR (1 << 11)
|
||||
|
||||
/* others */
|
||||
#define CHAN_NR_MIN 0
|
||||
#define CHAN_NR_MAX 31
|
||||
|
||||
#endif /* __SDMA_H */
|
||||
233
u-boot/arch/arm/include/asm/arch-omap3/dss.h
Normal file
233
u-boot/arch/arm/include/asm/arch-omap3/dss.h
Normal file
@@ -0,0 +1,233 @@
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* Referred to Linux Kernel DSS driver files for OMAP3 by
|
||||
* Tomi Valkeinen from drivers/video/omap2/dss/
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation's version 2 and any
|
||||
* later version the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef DSS_H
|
||||
#define DSS_H
|
||||
|
||||
/* DSS Base Registers */
|
||||
#define OMAP3_DSS_BASE 0x48050000
|
||||
#define OMAP3_DISPC_BASE 0x48050400
|
||||
#define OMAP3_VENC_BASE 0x48050C00
|
||||
|
||||
/* DSS Registers */
|
||||
struct dss_regs {
|
||||
u32 revision; /* 0x00 */
|
||||
u8 res1[12]; /* 0x04 */
|
||||
u32 sysconfig; /* 0x10 */
|
||||
u32 sysstatus; /* 0x14 */
|
||||
u32 irqstatus; /* 0x18 */
|
||||
u8 res2[36]; /* 0x1C */
|
||||
u32 control; /* 0x40 */
|
||||
u32 sdi_control; /* 0x44 */
|
||||
u32 pll_control; /* 0x48 */
|
||||
};
|
||||
|
||||
/* DISPC Registers */
|
||||
struct dispc_regs {
|
||||
u32 revision; /* 0x00 */
|
||||
u8 res1[12]; /* 0x04 */
|
||||
u32 sysconfig; /* 0x10 */
|
||||
u32 sysstatus; /* 0x14 */
|
||||
u32 irqstatus; /* 0x18 */
|
||||
u32 irqenable; /* 0x1C */
|
||||
u8 res2[32]; /* 0x20 */
|
||||
u32 control; /* 0x40 */
|
||||
u32 config; /* 0x44 */
|
||||
u32 reserve_2; /* 0x48 */
|
||||
u32 default_color0; /* 0x4C */
|
||||
u32 default_color1; /* 0x50 */
|
||||
u32 trans_color0; /* 0x54 */
|
||||
u32 trans_color1; /* 0x58 */
|
||||
u32 line_status; /* 0x5C */
|
||||
u32 line_number; /* 0x60 */
|
||||
u32 timing_h; /* 0x64 */
|
||||
u32 timing_v; /* 0x68 */
|
||||
u32 pol_freq; /* 0x6C */
|
||||
u32 divisor; /* 0x70 */
|
||||
u32 global_alpha; /* 0x74 */
|
||||
u32 size_dig; /* 0x78 */
|
||||
u32 size_lcd; /* 0x7C */
|
||||
u32 gfx_ba0; /* 0x80 */
|
||||
u32 gfx_ba1; /* 0x84 */
|
||||
u32 gfx_position; /* 0x88 */
|
||||
u32 gfx_size; /* 0x8C */
|
||||
u8 unused[16]; /* 0x90 */
|
||||
u32 gfx_attributes; /* 0xA0 */
|
||||
u32 gfx_fifo_threshold; /* 0xA4 */
|
||||
u32 gfx_fifo_size_status; /* 0xA8 */
|
||||
u32 gfx_row_inc; /* 0xAC */
|
||||
u32 gfx_pixel_inc; /* 0xB0 */
|
||||
u32 gfx_window_skip; /* 0xB4 */
|
||||
u32 gfx_table_ba; /* 0xB8 */
|
||||
};
|
||||
|
||||
/* VENC Registers */
|
||||
struct venc_regs {
|
||||
u32 rev_id; /* 0x00 */
|
||||
u32 status; /* 0x04 */
|
||||
u32 f_control; /* 0x08 */
|
||||
u32 reserve_1; /* 0x0C */
|
||||
u32 vidout_ctrl; /* 0x10 */
|
||||
u32 sync_ctrl; /* 0x14 */
|
||||
u32 reserve_2; /* 0x18 */
|
||||
u32 llen; /* 0x1C */
|
||||
u32 flens; /* 0x20 */
|
||||
u32 hfltr_ctrl; /* 0x24 */
|
||||
u32 cc_carr_wss_carr; /* 0x28 */
|
||||
u32 c_phase; /* 0x2C */
|
||||
u32 gain_u; /* 0x30 */
|
||||
u32 gain_v; /* 0x34 */
|
||||
u32 gain_y; /* 0x38 */
|
||||
u32 black_level; /* 0x3C */
|
||||
u32 blank_level; /* 0x40 */
|
||||
u32 x_color; /* 0x44 */
|
||||
u32 m_control; /* 0x48 */
|
||||
u32 bstamp_wss_data; /* 0x4C */
|
||||
u32 s_carr; /* 0x50 */
|
||||
u32 line21; /* 0x54 */
|
||||
u32 ln_sel; /* 0x58 */
|
||||
u32 l21__wc_ctl; /* 0x5C */
|
||||
u32 htrigger_vtrigger; /* 0x60 */
|
||||
u32 savid__eavid; /* 0x64 */
|
||||
u32 flen__fal; /* 0x68 */
|
||||
u32 lal__phase_reset; /* 0x6C */
|
||||
u32 hs_int_start_stop_x; /* 0x70 */
|
||||
u32 hs_ext_start_stop_x; /* 0x74 */
|
||||
u32 vs_int_start_x; /* 0x78 */
|
||||
u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */
|
||||
u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */
|
||||
u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */
|
||||
u32 vs_ext_stop_y; /* 0x88 */
|
||||
u32 reserve_3; /* 0x8C */
|
||||
u32 avid_start_stop_x; /* 0x90 */
|
||||
u32 avid_start_stop_y; /* 0x94 */
|
||||
u32 reserve_4; /* 0x98 */
|
||||
u32 reserve_5; /* 0x9C */
|
||||
u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */
|
||||
u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */
|
||||
u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */
|
||||
u32 reserve_6; /* 0xAC */
|
||||
u32 tvdetgp_int_start_stop_x; /* 0xB0 */
|
||||
u32 tvdetgp_int_start_stop_y; /* 0xB4 */
|
||||
u32 gen_ctrl; /* 0xB8 */
|
||||
u32 reserve_7; /* 0xBC */
|
||||
u32 reserve_8; /* 0xC0 */
|
||||
u32 output_control; /* 0xC4 */
|
||||
u32 dac_b__dac_c; /* 0xC8 */
|
||||
u32 height_width; /* 0xCC */
|
||||
};
|
||||
|
||||
/* Few Register Offsets */
|
||||
#define TFTSTN_SHIFT 3
|
||||
#define DATALINES_SHIFT 8
|
||||
|
||||
#define GFX_ENABLE 1
|
||||
#define GFX_FORMAT_SHIFT 1
|
||||
#define LOADMODE_SHIFT 1
|
||||
|
||||
#define DSS_SOFTRESET (1 << 1)
|
||||
#define DSS_RESETDONE 1
|
||||
|
||||
/* Enabling Display controller */
|
||||
#define LCD_ENABLE 1
|
||||
#define DIG_ENABLE (1 << 1)
|
||||
#define GO_LCD (1 << 5)
|
||||
#define GO_DIG (1 << 6)
|
||||
#define GP_OUT0 (1 << 15)
|
||||
#define GP_OUT1 (1 << 16)
|
||||
|
||||
/* Configure VENC DSS Params */
|
||||
#define VENC_CLK_ENABLE (1 << 3)
|
||||
#define DAC_DEMEN (1 << 4)
|
||||
#define DAC_POWERDN (1 << 5)
|
||||
#define VENC_OUT_SEL (1 << 6)
|
||||
#define DIG_LPP_SHIFT 16
|
||||
|
||||
/* LCD display type */
|
||||
#define PASSIVE_DISPLAY 0
|
||||
#define ACTIVE_DISPLAY 1
|
||||
|
||||
/* TFTDATALINES */
|
||||
#define LCD_INTERFACE_12_BIT 0
|
||||
#define LCD_INTERFACE_16_BIT 1
|
||||
#define LCD_INTERFACE_18_BIT 2
|
||||
#define LCD_INTERFACE_24_BIT 3
|
||||
|
||||
/* Polarity */
|
||||
#define DSS_IVS (1 << 12)
|
||||
#define DSS_IHS (1 << 13)
|
||||
#define DSS_IPC (1 << 14)
|
||||
#define DSS_IEO (1 << 15)
|
||||
#define DSS_ONOFF (1 << 17)
|
||||
|
||||
/* GFX format */
|
||||
#define GFXFORMAT_BITMAP1 (0x0 << 1)
|
||||
#define GFXFORMAT_BITMAP2 (0x1 << 1)
|
||||
#define GFXFORMAT_BITMAP4 (0x2 << 1)
|
||||
#define GFXFORMAT_BITMAP8 (0x3 << 1)
|
||||
#define GFXFORMAT_RGB12 (0x4 << 1)
|
||||
#define GFXFORMAT_ARGB16 (0x5 << 1)
|
||||
#define GFXFORMAT_RGB16 (0x6 << 1)
|
||||
#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1)
|
||||
#define GFXFORMAT_RGB24_PACKED (0x9 << 1)
|
||||
#define GFXFORMAT_ARGB32 (0xC << 1)
|
||||
#define GFXFORMAT_RGBA32 (0xD << 1)
|
||||
#define GFXFORMAT_RGBx32 (0xE << 1)
|
||||
|
||||
/* Panel Configuration */
|
||||
struct panel_config {
|
||||
u32 timing_h;
|
||||
u32 timing_v;
|
||||
u32 pol_freq;
|
||||
u32 divisor;
|
||||
u32 lcd_size;
|
||||
u32 panel_type;
|
||||
u32 data_lines;
|
||||
u32 load_mode;
|
||||
u32 panel_color;
|
||||
u32 gfx_format;
|
||||
void *frame_buffer;
|
||||
};
|
||||
|
||||
#define DSS_HBP(bp) (((bp) - 1) << 20)
|
||||
#define DSS_HFP(fp) (((fp) - 1) << 8)
|
||||
#define DSS_HSW(sw) ((sw) - 1)
|
||||
#define DSS_VBP(bp) ((bp) << 20)
|
||||
#define DSS_VFP(fp) ((fp) << 8)
|
||||
#define DSS_VSW(sw) ((sw) - 1)
|
||||
|
||||
#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
|
||||
#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
|
||||
#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
|
||||
|
||||
/* Generic DSS Functions */
|
||||
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
|
||||
u32 height, u32 width);
|
||||
void omap3_dss_panel_config(const struct panel_config *panel_cfg);
|
||||
void omap3_dss_enable(void);
|
||||
|
||||
#endif /* DSS_H */
|
||||
39
u-boot/arch/arm/include/asm/arch-omap3/ehci.h
Normal file
39
u-boot/arch/arm/include/asm/arch-omap3/ehci.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Alexander Holler <holler@ahsoftware.de>
|
||||
*
|
||||
* Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37
|
||||
*
|
||||
* See there for additional Copyrights.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _OMAP3_EHCI_H_
|
||||
#define _OMAP3_EHCI_H_
|
||||
|
||||
/* USB/EHCI registers */
|
||||
#define OMAP_USBTLL_BASE 0x48062000UL
|
||||
#define OMAP_UHH_BASE 0x48064000UL
|
||||
#define OMAP_EHCI_BASE 0x48064800UL
|
||||
|
||||
/* TLL Register Set */
|
||||
#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
|
||||
#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
|
||||
#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
|
||||
#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
|
||||
#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1
|
||||
|
||||
/* UHH Register Set */
|
||||
#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
|
||||
#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
|
||||
#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
|
||||
#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
|
||||
#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
|
||||
#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2)
|
||||
|
||||
#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_CACTIVITY | \
|
||||
OMAP_UHH_SYSCONFIG_SIDLEMODE | \
|
||||
OMAP_UHH_SYSCONFIG_ENAWAKEUP | \
|
||||
OMAP_UHH_SYSCONFIG_MIDLEMODE)
|
||||
|
||||
#endif /* _OMAP3_EHCI_H_ */
|
||||
42
u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h
Normal file
42
u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Based on:
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* dm644x_emac.h
|
||||
*
|
||||
* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
|
||||
*
|
||||
* Copyright (C) 2005 Texas Instruments.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Modifications:
|
||||
* ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
|
||||
*/
|
||||
|
||||
#ifndef _AM3517_EMAC_H_
|
||||
#define _AM3517_EMAC_H_
|
||||
|
||||
#define EMAC_BASE_ADDR 0x5C010000
|
||||
#define EMAC_WRAPPER_BASE_ADDR 0x5C000000
|
||||
#define EMAC_WRAPPER_RAM_ADDR 0x5C020000
|
||||
#define EMAC_MDIO_BASE_ADDR 0x5C030000
|
||||
#define EMAC_HW_RAM_ADDR 0x01E20000
|
||||
|
||||
#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */
|
||||
#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */
|
||||
|
||||
/* SOFTRESET macro definition interferes with emac_regs structure definition */
|
||||
#undef SOFTRESET
|
||||
|
||||
typedef volatile unsigned int dv_reg;
|
||||
typedef volatile unsigned int *dv_reg_p;
|
||||
|
||||
#define DAVINCI_EMAC_VERSION2
|
||||
|
||||
#endif /* _AM3517_EMAC_H_ */
|
||||
66
u-boot/arch/arm/include/asm/arch-omap3/emif4.h
Normal file
66
u-boot/arch/arm/include/asm/arch-omap3/emif4.h
Normal file
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Auther:
|
||||
* Vaibhav Hiremath <hvaibhav@ti.com>
|
||||
*
|
||||
* Copyright (C) 2010
|
||||
* Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _EMIF_H_
|
||||
#define _EMIF_H_
|
||||
|
||||
/*
|
||||
* Configuration values
|
||||
*/
|
||||
#define EMIF4_TIM1_T_RP (0x3 << 25)
|
||||
#define EMIF4_TIM1_T_RCD (0x3 << 21)
|
||||
#define EMIF4_TIM1_T_WR (0x3 << 17)
|
||||
#define EMIF4_TIM1_T_RAS (0x8 << 12)
|
||||
#define EMIF4_TIM1_T_RC (0xA << 6)
|
||||
#define EMIF4_TIM1_T_RRD (0x2 << 3)
|
||||
#define EMIF4_TIM1_T_WTR (0x2)
|
||||
|
||||
#define EMIF4_TIM2_T_XP (0x2 << 28)
|
||||
#define EMIF4_TIM2_T_ODT (0x0 << 25)
|
||||
#define EMIF4_TIM2_T_XSNR (0x1C << 16)
|
||||
#define EMIF4_TIM2_T_XSRD (0xC8 << 6)
|
||||
#define EMIF4_TIM2_T_RTP (0x1 << 3)
|
||||
#define EMIF4_TIM2_T_CKE (0x2)
|
||||
|
||||
#define EMIF4_TIM3_T_RFC (0x25 << 4)
|
||||
#define EMIF4_TIM3_T_RAS_MAX (0x7)
|
||||
|
||||
#define EMIF4_PWR_IDLE_MODE (0x2 << 30)
|
||||
#define EMIF4_PWR_DPD_DIS (0x0 << 10)
|
||||
#define EMIF4_PWR_DPD_EN (0x1 << 10)
|
||||
#define EMIF4_PWR_LP_MODE (0x0 << 8)
|
||||
#define EMIF4_PWR_PM_TIM (0x0)
|
||||
|
||||
#define EMIF4_INITREF_DIS (0x0 << 31)
|
||||
#define EMIF4_REFRESH_RATE (0x50F)
|
||||
|
||||
#define EMIF4_CFG_SDRAM_TYP (0x2 << 29)
|
||||
#define EMIF4_CFG_IBANK_POS (0x0 << 27)
|
||||
#define EMIF4_CFG_DDR_TERM (0x0 << 24)
|
||||
#define EMIF4_CFG_DDR2_DDQS (0x1 << 23)
|
||||
#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20)
|
||||
#define EMIF4_CFG_SDR_DRV (0x0 << 18)
|
||||
#define EMIF4_CFG_NARROW_MD (0x0 << 14)
|
||||
#define EMIF4_CFG_CL (0x5 << 10)
|
||||
#define EMIF4_CFG_ROWSIZE (0x0 << 7)
|
||||
#define EMIF4_CFG_IBANK (0x3 << 4)
|
||||
#define EMIF4_CFG_EBANK (0x0 << 3)
|
||||
#define EMIF4_CFG_PGSIZE (0x2)
|
||||
|
||||
/*
|
||||
* EMIF4 PHY Control 1 register configuration
|
||||
*/
|
||||
#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7)
|
||||
#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7)
|
||||
#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6)
|
||||
#define EMIF4_DDR1_PWRDN_EN (0x1 << 6)
|
||||
#define EMIF4_DDR1_READ_LAT (0x6 << 0)
|
||||
|
||||
#endif /* endif _EMIF_H_ */
|
||||
35
u-boot/arch/arm/include/asm/arch-omap3/gpio.h
Normal file
35
u-boot/arch/arm/include/asm/arch-omap3/gpio.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) 2009 Wind River Systems, Inc.
|
||||
* Tom Rix <Tom.Rix@windriver.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* This work is derived from the linux 2.6.27 kernel source
|
||||
* To fetch, use the kernel repository
|
||||
* git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
|
||||
* Use the v2.6.27 tag.
|
||||
*
|
||||
* Below is the original's header including its copyright
|
||||
*
|
||||
* linux/arch/arm/plat-omap/gpio.c
|
||||
*
|
||||
* Support functions for OMAP GPIO
|
||||
*
|
||||
* Copyright (C) 2003-2005 Nokia Corporation
|
||||
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
|
||||
*/
|
||||
#ifndef _GPIO_OMAP3_H
|
||||
#define _GPIO_OMAP3_H
|
||||
|
||||
#include <asm/omap_gpio.h>
|
||||
|
||||
#define OMAP_MAX_GPIO 192
|
||||
|
||||
#define OMAP34XX_GPIO1_BASE 0x48310000
|
||||
#define OMAP34XX_GPIO2_BASE 0x49050000
|
||||
#define OMAP34XX_GPIO3_BASE 0x49052000
|
||||
#define OMAP34XX_GPIO4_BASE 0x49054000
|
||||
#define OMAP34XX_GPIO5_BASE 0x49056000
|
||||
#define OMAP34XX_GPIO6_BASE 0x49058000
|
||||
|
||||
#endif /* _GPIO_OMAP3_H */
|
||||
48
u-boot/arch/arm/include/asm/arch-omap3/i2c.h
Normal file
48
u-boot/arch/arm/include/asm/arch-omap3/i2c.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _OMAP3_I2C_H_
|
||||
#define _OMAP3_I2C_H_
|
||||
|
||||
#define I2C_BUS_MAX 3
|
||||
#define I2C_DEFAULT_BASE I2C_BASE1
|
||||
|
||||
struct i2c {
|
||||
unsigned short rev; /* 0x00 */
|
||||
unsigned short res1;
|
||||
unsigned short ie; /* 0x04 */
|
||||
unsigned short res2;
|
||||
unsigned short stat; /* 0x08 */
|
||||
unsigned short res3;
|
||||
unsigned short iv; /* 0x0C */
|
||||
unsigned short res4;
|
||||
unsigned short syss; /* 0x10 */
|
||||
unsigned short res4a;
|
||||
unsigned short buf; /* 0x14 */
|
||||
unsigned short res5;
|
||||
unsigned short cnt; /* 0x18 */
|
||||
unsigned short res6;
|
||||
unsigned short data; /* 0x1C */
|
||||
unsigned short res7;
|
||||
unsigned short sysc; /* 0x20 */
|
||||
unsigned short res8;
|
||||
unsigned short con; /* 0x24 */
|
||||
unsigned short res9;
|
||||
unsigned short oa; /* 0x28 */
|
||||
unsigned short res10;
|
||||
unsigned short sa; /* 0x2C */
|
||||
unsigned short res11;
|
||||
unsigned short psc; /* 0x30 */
|
||||
unsigned short res12;
|
||||
unsigned short scll; /* 0x34 */
|
||||
unsigned short res13;
|
||||
unsigned short sclh; /* 0x38 */
|
||||
unsigned short res14;
|
||||
unsigned short systest; /* 0x3c */
|
||||
unsigned short res15;
|
||||
};
|
||||
|
||||
#endif /* _OMAP3_I2C_H_ */
|
||||
489
u-boot/arch/arm/include/asm/arch-omap3/mem.h
Normal file
489
u-boot/arch/arm/include/asm/arch-omap3/mem.h
Normal file
@@ -0,0 +1,489 @@
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _MEM_H_
|
||||
#define _MEM_H_
|
||||
|
||||
#define CS0 0x0
|
||||
#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
enum {
|
||||
STACKED = 0,
|
||||
IP_DDR = 1,
|
||||
COMBO_DDR = 2,
|
||||
IP_SDR = 3,
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define EARLY_INIT 1
|
||||
|
||||
/*
|
||||
* For a full explanation of these registers and values please see
|
||||
* the Technical Reference Manual (TRM) for any of the processors in
|
||||
* this family.
|
||||
*/
|
||||
|
||||
/* Slower full frequency range default timings for x32 operation*/
|
||||
#define SDRC_SHARING 0x00000100
|
||||
#define SDRC_MR_0_SDR 0x00000031
|
||||
|
||||
/*
|
||||
* SDRC autorefresh control values. This register consists of autorefresh
|
||||
* enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
|
||||
* counter is a result of ( tREFI / tCK ) - 50.
|
||||
*/
|
||||
#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
|
||||
#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
|
||||
#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
|
||||
#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
|
||||
|
||||
#define DLL_OFFSET 0
|
||||
#define DLL_WRITEDDRCLKX2DIS 1
|
||||
#define DLL_ENADLL 1
|
||||
#define DLL_LOCKDLL 0
|
||||
#define DLL_DLLPHASE_72 0
|
||||
#define DLL_DLLPHASE_90 1
|
||||
|
||||
/* rkw - need to find of 90/72 degree recommendation for speed like before */
|
||||
#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
|
||||
(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
|
||||
|
||||
/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
|
||||
#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
|
||||
#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
|
||||
#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
|
||||
#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
|
||||
#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
|
||||
#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
|
||||
#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
|
||||
#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
|
||||
|
||||
#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \
|
||||
ACTIM_CTRLA_TRFC(trfc) | \
|
||||
ACTIM_CTRLA_TRC(trc) | \
|
||||
ACTIM_CTRLA_TRAS(tras) | \
|
||||
ACTIM_CTRLA_TRP(trp) | \
|
||||
ACTIM_CTRLA_TRCD(trcd) | \
|
||||
ACTIM_CTRLA_TRRD(trrd) | \
|
||||
ACTIM_CTRLA_TDPL(tdpl) | \
|
||||
ACTIM_CTRLA_TDAL(tdal)
|
||||
|
||||
/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
|
||||
#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
|
||||
#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
|
||||
#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
|
||||
#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
|
||||
|
||||
#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \
|
||||
ACTIM_CTRLB_TWTR(twtr) | \
|
||||
ACTIM_CTRLB_TCKE(tcke) | \
|
||||
ACTIM_CTRLB_TXP(txp) | \
|
||||
ACTIM_CTRLB_TXSR(txsr)
|
||||
|
||||
/*
|
||||
* Values used in the MCFG register. Only values we use today
|
||||
* are defined and the rest can be found in the TRM. Unless otherwise
|
||||
* noted all fields are one bit.
|
||||
*/
|
||||
#define V_MCFG_RAMTYPE_DDR (0x1)
|
||||
#define V_MCFG_DEEPPD_EN (0x1 << 3)
|
||||
#define V_MCFG_B32NOT16_32 (0x1 << 4)
|
||||
#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
|
||||
#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */
|
||||
#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
|
||||
#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */
|
||||
#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10)
|
||||
#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */
|
||||
|
||||
/* Macro to construct MCFG */
|
||||
#define MCFG(ramsize, raswidth) \
|
||||
V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \
|
||||
V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \
|
||||
V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \
|
||||
V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
|
||||
|
||||
/* Hynix part of Overo (165MHz optimized) 6.06ns */
|
||||
#define HYNIX_TDAL_165 6
|
||||
#define HYNIX_TDPL_165 3
|
||||
#define HYNIX_TRRD_165 2
|
||||
#define HYNIX_TRCD_165 3
|
||||
#define HYNIX_TRP_165 3
|
||||
#define HYNIX_TRAS_165 7
|
||||
#define HYNIX_TRC_165 10
|
||||
#define HYNIX_TRFC_165 21
|
||||
#define HYNIX_V_ACTIMA_165 \
|
||||
ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
|
||||
HYNIX_TRAS_165, HYNIX_TRP_165, \
|
||||
HYNIX_TRCD_165, HYNIX_TRRD_165, \
|
||||
HYNIX_TDPL_165, HYNIX_TDAL_165)
|
||||
|
||||
#define HYNIX_TWTR_165 1
|
||||
#define HYNIX_TCKE_165 1
|
||||
#define HYNIX_TXP_165 2
|
||||
#define HYNIX_XSR_165 24
|
||||
#define HYNIX_V_ACTIMB_165 \
|
||||
ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
|
||||
HYNIX_TXP_165, HYNIX_XSR_165)
|
||||
|
||||
#define HYNIX_RASWIDTH_165 13
|
||||
#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
|
||||
|
||||
/* Hynix part of AM/DM37xEVM (200MHz optimized) */
|
||||
#define HYNIX_TDAL_200 6
|
||||
#define HYNIX_TDPL_200 3
|
||||
#define HYNIX_TRRD_200 2
|
||||
#define HYNIX_TRCD_200 4
|
||||
#define HYNIX_TRP_200 3
|
||||
#define HYNIX_TRAS_200 8
|
||||
#define HYNIX_TRC_200 11
|
||||
#define HYNIX_TRFC_200 18
|
||||
#define HYNIX_V_ACTIMA_200 \
|
||||
ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
|
||||
HYNIX_TRAS_200, HYNIX_TRP_200, \
|
||||
HYNIX_TRCD_200, HYNIX_TRRD_200, \
|
||||
HYNIX_TDPL_200, HYNIX_TDAL_200)
|
||||
|
||||
#define HYNIX_TWTR_200 2
|
||||
#define HYNIX_TCKE_200 1
|
||||
#define HYNIX_TXP_200 1
|
||||
#define HYNIX_XSR_200 28
|
||||
#define HYNIX_V_ACTIMB_200 \
|
||||
ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
|
||||
HYNIX_TXP_200, HYNIX_XSR_200)
|
||||
|
||||
#define HYNIX_RASWIDTH_200 14
|
||||
#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
|
||||
|
||||
/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
|
||||
#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
|
||||
/* 15/6 + 18/6 = 5.5 -> 6 */
|
||||
#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
|
||||
#define INFINEON_TRRD_165 2 /* 12/6 = 2 */
|
||||
#define INFINEON_TRCD_165 3 /* 18/6 = 3 */
|
||||
#define INFINEON_TRP_165 3 /* 18/6 = 3 */
|
||||
#define INFINEON_TRAS_165 7 /* 42/6 = 7 */
|
||||
#define INFINEON_TRC_165 10 /* 60/6 = 10 */
|
||||
#define INFINEON_TRFC_165 12 /* 72/6 = 12 */
|
||||
|
||||
#define INFINEON_V_ACTIMA_165 \
|
||||
ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
|
||||
INFINEON_TRAS_165, INFINEON_TRP_165, \
|
||||
INFINEON_TRCD_165, INFINEON_TRRD_165, \
|
||||
INFINEON_TDPL_165, INFINEON_TDAL_165)
|
||||
|
||||
#define INFINEON_TWTR_165 1
|
||||
#define INFINEON_TCKE_165 2
|
||||
#define INFINEON_TXP_165 2
|
||||
#define INFINEON_XSR_165 20 /* 120/6 = 20 */
|
||||
|
||||
#define INFINEON_V_ACTIMB_165 \
|
||||
ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
|
||||
INFINEON_TXP_165, INFINEON_XSR_165)
|
||||
|
||||
/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
|
||||
#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
|
||||
/* 15/6 + 18/6 = 5.5 -> 6 */
|
||||
#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
|
||||
#define MICRON_TRRD_165 2 /* 12/6 = 2 */
|
||||
#define MICRON_TRCD_165 3 /* 18/6 = 3 */
|
||||
#define MICRON_TRP_165 3 /* 18/6 = 3 */
|
||||
#define MICRON_TRAS_165 7 /* 42/6 = 7 */
|
||||
#define MICRON_TRC_165 10 /* 60/6 = 10 */
|
||||
#define MICRON_TRFC_165 21 /* 125/6 = 21 */
|
||||
|
||||
#define MICRON_V_ACTIMA_165 \
|
||||
ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
|
||||
MICRON_TRAS_165, MICRON_TRP_165, \
|
||||
MICRON_TRCD_165, MICRON_TRRD_165, \
|
||||
MICRON_TDPL_165, MICRON_TDAL_165)
|
||||
|
||||
#define MICRON_TWTR_165 1
|
||||
#define MICRON_TCKE_165 1
|
||||
#define MICRON_XSR_165 23 /* 138/6 = 23 */
|
||||
#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
|
||||
|
||||
#define MICRON_V_ACTIMB_165 \
|
||||
ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
|
||||
MICRON_TXP_165, MICRON_XSR_165)
|
||||
|
||||
#define MICRON_RASWIDTH_165 13
|
||||
#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
|
||||
|
||||
#define MICRON_BL_165 0x2
|
||||
#define MICRON_SIL_165 0x0
|
||||
#define MICRON_CASL_165 0x3
|
||||
#define MICRON_WBST_165 0x0
|
||||
#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \
|
||||
(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
|
||||
(MICRON_BL_165))
|
||||
|
||||
/* Micron part (200MHz optimized) 5 ns */
|
||||
#define MICRON_TDAL_200 6
|
||||
#define MICRON_TDPL_200 3
|
||||
#define MICRON_TRRD_200 2
|
||||
#define MICRON_TRCD_200 3
|
||||
#define MICRON_TRP_200 3
|
||||
#define MICRON_TRAS_200 8
|
||||
#define MICRON_TRC_200 11
|
||||
#define MICRON_TRFC_200 15
|
||||
#define MICRON_V_ACTIMA_200 \
|
||||
ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
|
||||
MICRON_TRAS_200, MICRON_TRP_200, \
|
||||
MICRON_TRCD_200, MICRON_TRRD_200, \
|
||||
MICRON_TDPL_200, MICRON_TDAL_200)
|
||||
|
||||
#define MICRON_TWTR_200 2
|
||||
#define MICRON_TCKE_200 4
|
||||
#define MICRON_TXP_200 2
|
||||
#define MICRON_XSR_200 23
|
||||
#define MICRON_V_ACTIMB_200 \
|
||||
ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
|
||||
MICRON_TXP_200, MICRON_XSR_200)
|
||||
|
||||
#define MICRON_RASWIDTH_200 14
|
||||
#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
|
||||
|
||||
/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
|
||||
#define SAMSUNG_TDAL_165 5
|
||||
#define SAMSUNG_TDPL_165 2
|
||||
#define SAMSUNG_TRRD_165 2
|
||||
#define SAMSUNG_TRCD_165 3
|
||||
#define SAMSUNG_TRP_165 3
|
||||
#define SAMSUNG_TRAS_165 7
|
||||
#define SAMSUNG_TRC_165 10
|
||||
#define SAMSUNG_TRFC_165 12
|
||||
|
||||
#define SAMSUNG_V_ACTIMA_165 \
|
||||
ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
|
||||
SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
|
||||
SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
|
||||
SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
|
||||
|
||||
#define SAMSUNG_TWTR_165 1
|
||||
#define SAMSUNG_TCKE_165 2
|
||||
#define SAMSUNG_XSR_165 20
|
||||
#define SAMSUNG_TXP_165 5
|
||||
|
||||
#define SAMSUNG_V_ACTIMB_165 \
|
||||
ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
|
||||
SAMSUNG_TXP_165, SAMSUNG_XSR_165)
|
||||
|
||||
#define SAMSUNG_RASWIDTH_165 14
|
||||
#define SAMSUNG_V_MCFG_165(size) \
|
||||
V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
|
||||
V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
|
||||
V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
|
||||
|
||||
/* TODO: find which register these were taken from */
|
||||
|
||||
#define SAMSUNG_BL_165 0x2
|
||||
#define SAMSUNG_SIL_165 0x0
|
||||
#define SAMSUNG_CASL_165 0x3
|
||||
#define SAMSUNG_WBST_165 0x0
|
||||
#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
|
||||
(SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
|
||||
(SAMSUNG_BL_165))
|
||||
|
||||
#define SAMSUNG_SHARING 0x00003700
|
||||
|
||||
/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
|
||||
#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
|
||||
/* 15/6 + 18/6 = 5.5 -> 6 */
|
||||
#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
|
||||
#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
|
||||
#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
|
||||
#define NUMONYX_TRP_165 3 /* 18/6 = 3 */
|
||||
#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
|
||||
#define NUMONYX_TRC_165 10 /* 60/6 = 10 */
|
||||
#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
|
||||
|
||||
#define NUMONYX_V_ACTIMA_165 \
|
||||
ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
|
||||
NUMONYX_TRAS_165, NUMONYX_TRP_165, \
|
||||
NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
|
||||
NUMONYX_TDPL_165, NUMONYX_TDAL_165)
|
||||
|
||||
#define NUMONYX_TWTR_165 2
|
||||
#define NUMONYX_TCKE_165 2
|
||||
#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
|
||||
#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
|
||||
|
||||
#define NUMONYX_V_ACTIMB_165 \
|
||||
ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
|
||||
NUMONYX_TXP_165, NUMONYX_XSR_165)
|
||||
|
||||
#define NUMONYX_RASWIDTH_165 15
|
||||
#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
|
||||
|
||||
/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
|
||||
#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
|
||||
/* 15/5 + 15/5 = 3 + 3 -> 6 */
|
||||
#define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
|
||||
#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */
|
||||
#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */
|
||||
#define NUMONYX_TRP_200 3 /* 15/5 = 3 */
|
||||
#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */
|
||||
#define NUMONYX_TRC_200 11 /* 55/5 = 11 */
|
||||
#define NUMONYX_TRFC_200 28 /* 140/5 = 28 */
|
||||
|
||||
#define NUMONYX_V_ACTIMA_200 \
|
||||
ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
|
||||
NUMONYX_TRAS_200, NUMONYX_TRP_200, \
|
||||
NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
|
||||
NUMONYX_TDPL_200, NUMONYX_TDAL_200)
|
||||
|
||||
#define NUMONYX_TWTR_200 2
|
||||
#define NUMONYX_TCKE_200 2
|
||||
#define NUMONYX_TXP_200 3
|
||||
#define NUMONYX_XSR_200 40
|
||||
|
||||
#define NUMONYX_V_ACTIMB_200 \
|
||||
ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
|
||||
NUMONYX_TXP_200, NUMONYX_XSR_200)
|
||||
|
||||
#define NUMONYX_RASWIDTH_200 15
|
||||
#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
|
||||
|
||||
/*
|
||||
* GPMC settings -
|
||||
* Definitions is as per the following format
|
||||
* #define <PART>_GPMC_CONFIG<x> <value>
|
||||
* Where:
|
||||
* PART is the part name e.g. STNOR - Intel Strata Flash
|
||||
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
|
||||
* Value is corresponding value
|
||||
*
|
||||
* For every valid PRCM configuration there should be only one definition of
|
||||
* the same. if values are independent of the board, this definition will be
|
||||
* present in this file if values are dependent on the board, then this should
|
||||
* go into corresponding mem-boardName.h file
|
||||
*
|
||||
* Currently valid part Names are (PART):
|
||||
* STNOR - Intel Strata Flash
|
||||
* SMNAND - Samsung NAND
|
||||
* MPDB - H4 MPDB board
|
||||
* SBNOR - Sibley NOR
|
||||
* MNAND - Micron Large page x16 NAND
|
||||
* ONNAND - Samsung One NAND
|
||||
*
|
||||
* include/configs/file.h contains the defn - for all CS we are interested
|
||||
* #define OMAP34XX_GPMC_CSx PART
|
||||
* #define OMAP34XX_GPMC_CSx_SIZE Size
|
||||
* #define OMAP34XX_GPMC_CSx_MAP Map
|
||||
* Where:
|
||||
* x - CS number
|
||||
* PART - Part Name as defined above
|
||||
* SIZE - how big is the mapping to be
|
||||
* GPMC_SIZE_128M - 0x8
|
||||
* GPMC_SIZE_64M - 0xC
|
||||
* GPMC_SIZE_32M - 0xE
|
||||
* GPMC_SIZE_16M - 0xF
|
||||
* MAP - Map this CS to which address(GPMC address space)- Absolute address
|
||||
* >>24 before being used.
|
||||
*/
|
||||
#define GPMC_SIZE_256M 0x0
|
||||
#define GPMC_SIZE_128M 0x8
|
||||
#define GPMC_SIZE_64M 0xC
|
||||
#define GPMC_SIZE_32M 0xE
|
||||
#define GPMC_SIZE_16M 0xF
|
||||
|
||||
#define GPMC_BASEADDR_MASK 0x3F
|
||||
|
||||
#define GPMC_CS_ENABLE 0x1
|
||||
|
||||
#define M_NAND_GPMC_CONFIG1 0x00001800
|
||||
#define M_NAND_GPMC_CONFIG2 0x00141400
|
||||
#define M_NAND_GPMC_CONFIG3 0x00141400
|
||||
#define M_NAND_GPMC_CONFIG4 0x0F010F01
|
||||
#define M_NAND_GPMC_CONFIG5 0x010C1414
|
||||
#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
|
||||
#define M_NAND_GPMC_CONFIG7 0x00000C44
|
||||
|
||||
#define STNOR_GPMC_CONFIG1 0x3
|
||||
#define STNOR_GPMC_CONFIG2 0x00151501
|
||||
#define STNOR_GPMC_CONFIG3 0x00060602
|
||||
#define STNOR_GPMC_CONFIG4 0x11091109
|
||||
#define STNOR_GPMC_CONFIG5 0x01141F1F
|
||||
#define STNOR_GPMC_CONFIG6 0x000004c4
|
||||
|
||||
#define SIBNOR_GPMC_CONFIG1 0x1200
|
||||
#define SIBNOR_GPMC_CONFIG2 0x001f1f00
|
||||
#define SIBNOR_GPMC_CONFIG3 0x00080802
|
||||
#define SIBNOR_GPMC_CONFIG4 0x1C091C09
|
||||
#define SIBNOR_GPMC_CONFIG5 0x01131F1F
|
||||
#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
|
||||
|
||||
#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
|
||||
#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
|
||||
#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
|
||||
#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
|
||||
#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
|
||||
#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
|
||||
|
||||
#define MPDB_GPMC_CONFIG1 0x00011000
|
||||
#define MPDB_GPMC_CONFIG2 0x001f1f01
|
||||
#define MPDB_GPMC_CONFIG3 0x00080803
|
||||
#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
|
||||
#define MPDB_GPMC_CONFIG5 0x041f1F1F
|
||||
#define MPDB_GPMC_CONFIG6 0x1F0F04C4
|
||||
|
||||
#define P2_GPMC_CONFIG1 0x0
|
||||
#define P2_GPMC_CONFIG2 0x0
|
||||
#define P2_GPMC_CONFIG3 0x0
|
||||
#define P2_GPMC_CONFIG4 0x0
|
||||
#define P2_GPMC_CONFIG5 0x0
|
||||
#define P2_GPMC_CONFIG6 0x0
|
||||
|
||||
#define ONENAND_GPMC_CONFIG1 0x00001200
|
||||
#define ONENAND_GPMC_CONFIG2 0x000F0F01
|
||||
#define ONENAND_GPMC_CONFIG3 0x00030301
|
||||
#define ONENAND_GPMC_CONFIG4 0x0F040F04
|
||||
#define ONENAND_GPMC_CONFIG5 0x010F1010
|
||||
#define ONENAND_GPMC_CONFIG6 0x1F060000
|
||||
|
||||
#define NET_GPMC_CONFIG1 0x00001000
|
||||
#define NET_GPMC_CONFIG2 0x001e1e01
|
||||
#define NET_GPMC_CONFIG3 0x00080300
|
||||
#define NET_GPMC_CONFIG4 0x1c091c09
|
||||
#define NET_GPMC_CONFIG5 0x04181f1f
|
||||
#define NET_GPMC_CONFIG6 0x00000FCF
|
||||
#define NET_GPMC_CONFIG7 0x00000f6c
|
||||
|
||||
/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
|
||||
#define NET_LAN9221_GPMC_CONFIG1 0x00001000
|
||||
#define NET_LAN9221_GPMC_CONFIG2 0x00060700
|
||||
#define NET_LAN9221_GPMC_CONFIG3 0x00020201
|
||||
#define NET_LAN9221_GPMC_CONFIG4 0x06000700
|
||||
#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
|
||||
#define NET_LAN9221_GPMC_CONFIG6 0x87030000
|
||||
#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
|
||||
|
||||
|
||||
/* max number of GPMC Chip Selects */
|
||||
#define GPMC_MAX_CS 8
|
||||
/* max number of GPMC regs */
|
||||
#define GPMC_MAX_REG 7
|
||||
|
||||
#define DBG_MPDB 6
|
||||
#define DBG_MPDB_BASE DEBUG_BASE
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* Function prototypes */
|
||||
void mem_init(void);
|
||||
|
||||
u32 is_mem_sdr(void);
|
||||
u32 mem_ok(u32 cs);
|
||||
|
||||
u32 get_sdr_cs_size(u32);
|
||||
u32 get_sdr_cs_offset(u32);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* endif _MEM_H_ */
|
||||
66
u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h
Normal file
66
u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h
Normal file
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation's version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef MMC_HOST_DEF_H
|
||||
#define MMC_HOST_DEF_H
|
||||
|
||||
#include <asm/omap_mmc.h>
|
||||
|
||||
/* T2 Register definitions */
|
||||
#define T2_BASE 0x48002000
|
||||
|
||||
typedef struct t2 {
|
||||
unsigned char res1[0x274]; /* 0x000 */
|
||||
unsigned int devconf0; /* 0x274 */
|
||||
unsigned char res2[0x060]; /* 0x278 */
|
||||
unsigned int devconf1; /* 0x2D8 */
|
||||
unsigned char res3[0x16C]; /* 0x2DC */
|
||||
unsigned int ctl_prog_io1; /* 0x448 */
|
||||
unsigned char res4[0x0D4]; /* 0x44C */
|
||||
unsigned int pbias_lite; /* 0x520 */
|
||||
} t2_t;
|
||||
|
||||
#define MMCSDIO1ADPCLKISEL (1 << 24)
|
||||
#define MMCSDIO2ADPCLKISEL (1 << 6)
|
||||
|
||||
#define EN_MMC1 (1 << 24)
|
||||
#define EN_MMC2 (1 << 25)
|
||||
#define EN_MMC3 (1 << 30)
|
||||
|
||||
#define PBIASLITEPWRDNZ0 (1 << 1)
|
||||
#define PBIASSPEEDCTRL0 (1 << 2)
|
||||
#define PBIASLITEPWRDNZ1 (1 << 9)
|
||||
#define PBIASLITEVMODE0 (1 << 0)
|
||||
|
||||
#define CTLPROGIO1SPEEDCTRL (1 << 20)
|
||||
|
||||
/*
|
||||
* OMAP HSMMC register definitions
|
||||
*/
|
||||
#define OMAP_HSMMC1_BASE 0x4809C000
|
||||
#define OMAP_HSMMC2_BASE 0x480B4000
|
||||
#define OMAP_HSMMC3_BASE 0x480AD000
|
||||
|
||||
|
||||
#endif /* MMC_HOST_DEF_H */
|
||||
13
u-boot/arch/arm/include/asm/arch-omap3/musb.h
Normal file
13
u-boot/arch/arm/include/asm/arch-omap3/musb.h
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* Ilya Yanok, <ilya.yanok@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_OMAP3_MUSB_H
|
||||
#define __ASM_ARCH_OMAP3_MUSB_H
|
||||
extern void am35x_musb_reset(void);
|
||||
extern void am35x_musb_phy_power(u8 on);
|
||||
extern void am35x_musb_clear_irq(void);
|
||||
#endif
|
||||
498
u-boot/arch/arm/include/asm/arch-omap3/mux.h
Normal file
498
u-boot/arch/arm/include/asm/arch-omap3/mux.h
Normal file
@@ -0,0 +1,498 @@
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Syed Mohammed Khasim <x0khasim@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _MUX_H_
|
||||
#define _MUX_H_
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* SB_LOW - Standby mode configuration: Output low-level
|
||||
* SB_HI - Standby mode configuration: Output high-level
|
||||
* SB_HIZ - Standby mode configuration: Output hi-impedence
|
||||
* SB_PD - Standby mode pull-down enabled
|
||||
* SB_PU - Standby mode pull-up enabled
|
||||
* WKEN - Wakeup input enabled
|
||||
* M0 - Mode 0
|
||||
*/
|
||||
|
||||
#define IEN (1 << 8)
|
||||
|
||||
#define IDIS (0 << 8)
|
||||
#define PTU (1 << 4)
|
||||
#define PTD (0 << 4)
|
||||
#define EN (1 << 3)
|
||||
#define DIS (0 << 3)
|
||||
|
||||
#define SB_LOW (1 << 9)
|
||||
#define SB_HI (5 << 9)
|
||||
#define SB_HIZ (2 << 9)
|
||||
#define SB_PD (1 << 12)
|
||||
#define SB_PU (3 << 12)
|
||||
#define WKEN (1 << 14)
|
||||
|
||||
#define M0 0
|
||||
#define M1 1
|
||||
#define M2 2
|
||||
#define M3 3
|
||||
#define M4 4
|
||||
#define M5 5
|
||||
#define M6 6
|
||||
#define M7 7
|
||||
|
||||
/*
|
||||
* To get the actual address the offset has to be added
|
||||
* to OMAP34XX_CTRL_BASE
|
||||
*/
|
||||
|
||||
/*SDRC*/
|
||||
#define CONTROL_PADCONF_SDRC_D0 0x0030
|
||||
#define CONTROL_PADCONF_SDRC_D1 0x0032
|
||||
#define CONTROL_PADCONF_SDRC_D2 0x0034
|
||||
#define CONTROL_PADCONF_SDRC_D3 0x0036
|
||||
#define CONTROL_PADCONF_SDRC_D4 0x0038
|
||||
#define CONTROL_PADCONF_SDRC_D5 0x003A
|
||||
#define CONTROL_PADCONF_SDRC_D6 0x003C
|
||||
#define CONTROL_PADCONF_SDRC_D7 0x003E
|
||||
#define CONTROL_PADCONF_SDRC_D8 0x0040
|
||||
#define CONTROL_PADCONF_SDRC_D9 0x0042
|
||||
#define CONTROL_PADCONF_SDRC_D10 0x0044
|
||||
#define CONTROL_PADCONF_SDRC_D11 0x0046
|
||||
#define CONTROL_PADCONF_SDRC_D12 0x0048
|
||||
#define CONTROL_PADCONF_SDRC_D13 0x004A
|
||||
#define CONTROL_PADCONF_SDRC_D14 0x004C
|
||||
#define CONTROL_PADCONF_SDRC_D15 0x004E
|
||||
#define CONTROL_PADCONF_SDRC_D16 0x0050
|
||||
#define CONTROL_PADCONF_SDRC_D17 0x0052
|
||||
#define CONTROL_PADCONF_SDRC_D18 0x0054
|
||||
#define CONTROL_PADCONF_SDRC_D19 0x0056
|
||||
#define CONTROL_PADCONF_SDRC_D20 0x0058
|
||||
#define CONTROL_PADCONF_SDRC_D21 0x005A
|
||||
#define CONTROL_PADCONF_SDRC_D22 0x005C
|
||||
#define CONTROL_PADCONF_SDRC_D23 0x005E
|
||||
#define CONTROL_PADCONF_SDRC_D24 0x0060
|
||||
#define CONTROL_PADCONF_SDRC_D25 0x0062
|
||||
#define CONTROL_PADCONF_SDRC_D26 0x0064
|
||||
#define CONTROL_PADCONF_SDRC_D27 0x0066
|
||||
#define CONTROL_PADCONF_SDRC_D28 0x0068
|
||||
#define CONTROL_PADCONF_SDRC_D29 0x006A
|
||||
#define CONTROL_PADCONF_SDRC_D30 0x006C
|
||||
#define CONTROL_PADCONF_SDRC_D31 0x006E
|
||||
#define CONTROL_PADCONF_SDRC_CLK 0x0070
|
||||
#define CONTROL_PADCONF_SDRC_DQS0 0x0072
|
||||
#define CONTROL_PADCONF_SDRC_DQS1 0x0074
|
||||
#define CONTROL_PADCONF_SDRC_DQS2 0x0076
|
||||
#define CONTROL_PADCONF_SDRC_DQS3 0x0078
|
||||
#define CONTROL_PADCONF_SDRC_BA0 0x05A0
|
||||
#define CONTROL_PADCONF_SDRC_BA1 0x05A2
|
||||
#define CONTROL_PADCONF_SDRC_A0 0x05A4
|
||||
#define CONTROL_PADCONF_SDRC_A1 0x05A6
|
||||
#define CONTROL_PADCONF_SDRC_A2 0x05A8
|
||||
#define CONTROL_PADCONF_SDRC_A3 0x05AA
|
||||
#define CONTROL_PADCONF_SDRC_A4 0x05AC
|
||||
#define CONTROL_PADCONF_SDRC_A5 0x05AE
|
||||
#define CONTROL_PADCONF_SDRC_A6 0x05B0
|
||||
#define CONTROL_PADCONF_SDRC_A7 0x05B2
|
||||
#define CONTROL_PADCONF_SDRC_A8 0x05B4
|
||||
#define CONTROL_PADCONF_SDRC_A9 0x05B6
|
||||
#define CONTROL_PADCONF_SDRC_A10 0x05B8
|
||||
#define CONTROL_PADCONF_SDRC_A11 0x05BA
|
||||
#define CONTROL_PADCONF_SDRC_A12 0x05BC
|
||||
#define CONTROL_PADCONF_SDRC_A13 0x05BE
|
||||
#define CONTROL_PADCONF_SDRC_A14 0x05C0
|
||||
#define CONTROL_PADCONF_SDRC_NCS0 0x05C2
|
||||
#define CONTROL_PADCONF_SDRC_NCS1 0x05C4
|
||||
#define CONTROL_PADCONF_SDRC_NCLK 0x05C6
|
||||
#define CONTROL_PADCONF_SDRC_NRAS 0x05C8
|
||||
#define CONTROL_PADCONF_SDRC_NCAS 0x05CA
|
||||
#define CONTROL_PADCONF_SDRC_NWE 0x05CC
|
||||
#define CONTROL_PADCONF_SDRC_DM0 0x05CE
|
||||
#define CONTROL_PADCONF_SDRC_DM1 0x05D0
|
||||
#define CONTROL_PADCONF_SDRC_DM2 0x05D2
|
||||
#define CONTROL_PADCONF_SDRC_DM3 0x05D4
|
||||
/*GPMC*/
|
||||
#define CONTROL_PADCONF_GPMC_A1 0x007A
|
||||
#define CONTROL_PADCONF_GPMC_A2 0x007C
|
||||
#define CONTROL_PADCONF_GPMC_A3 0x007E
|
||||
#define CONTROL_PADCONF_GPMC_A4 0x0080
|
||||
#define CONTROL_PADCONF_GPMC_A5 0x0082
|
||||
#define CONTROL_PADCONF_GPMC_A6 0x0084
|
||||
#define CONTROL_PADCONF_GPMC_A7 0x0086
|
||||
#define CONTROL_PADCONF_GPMC_A8 0x0088
|
||||
#define CONTROL_PADCONF_GPMC_A9 0x008A
|
||||
#define CONTROL_PADCONF_GPMC_A10 0x008C
|
||||
#define CONTROL_PADCONF_GPMC_A11 0x0264
|
||||
#define CONTROL_PADCONF_GPMC_D0 0x008E
|
||||
#define CONTROL_PADCONF_GPMC_D1 0x0090
|
||||
#define CONTROL_PADCONF_GPMC_D2 0x0092
|
||||
#define CONTROL_PADCONF_GPMC_D3 0x0094
|
||||
#define CONTROL_PADCONF_GPMC_D4 0x0096
|
||||
#define CONTROL_PADCONF_GPMC_D5 0x0098
|
||||
#define CONTROL_PADCONF_GPMC_D6 0x009A
|
||||
#define CONTROL_PADCONF_GPMC_D7 0x009C
|
||||
#define CONTROL_PADCONF_GPMC_D8 0x009E
|
||||
#define CONTROL_PADCONF_GPMC_D9 0x00A0
|
||||
#define CONTROL_PADCONF_GPMC_D10 0x00A2
|
||||
#define CONTROL_PADCONF_GPMC_D11 0x00A4
|
||||
#define CONTROL_PADCONF_GPMC_D12 0x00A6
|
||||
#define CONTROL_PADCONF_GPMC_D13 0x00A8
|
||||
#define CONTROL_PADCONF_GPMC_D14 0x00AA
|
||||
#define CONTROL_PADCONF_GPMC_D15 0x00AC
|
||||
#define CONTROL_PADCONF_GPMC_NCS0 0x00AE
|
||||
#define CONTROL_PADCONF_GPMC_NCS1 0x00B0
|
||||
#define CONTROL_PADCONF_GPMC_NCS2 0x00B2
|
||||
#define CONTROL_PADCONF_GPMC_NCS3 0x00B4
|
||||
#define CONTROL_PADCONF_GPMC_NCS4 0x00B6
|
||||
#define CONTROL_PADCONF_GPMC_NCS5 0x00B8
|
||||
#define CONTROL_PADCONF_GPMC_NCS6 0x00BA
|
||||
#define CONTROL_PADCONF_GPMC_NCS7 0x00BC
|
||||
#define CONTROL_PADCONF_GPMC_CLK 0x00BE
|
||||
#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0
|
||||
#define CONTROL_PADCONF_GPMC_NOE 0x00C2
|
||||
#define CONTROL_PADCONF_GPMC_NWE 0x00C4
|
||||
#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6
|
||||
#define CONTROL_PADCONF_GPMC_NBE1 0x00C8
|
||||
#define CONTROL_PADCONF_GPMC_NWP 0x00CA
|
||||
#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC
|
||||
#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE
|
||||
#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0
|
||||
#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2
|
||||
/*DSS*/
|
||||
#define CONTROL_PADCONF_DSS_PCLK 0x00D4
|
||||
#define CONTROL_PADCONF_DSS_HSYNC 0x00D6
|
||||
#define CONTROL_PADCONF_DSS_VSYNC 0x00D8
|
||||
#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA
|
||||
#define CONTROL_PADCONF_DSS_DATA0 0x00DC
|
||||
#define CONTROL_PADCONF_DSS_DATA1 0x00DE
|
||||
#define CONTROL_PADCONF_DSS_DATA2 0x00E0
|
||||
#define CONTROL_PADCONF_DSS_DATA3 0x00E2
|
||||
#define CONTROL_PADCONF_DSS_DATA4 0x00E4
|
||||
#define CONTROL_PADCONF_DSS_DATA5 0x00E6
|
||||
#define CONTROL_PADCONF_DSS_DATA6 0x00E8
|
||||
#define CONTROL_PADCONF_DSS_DATA7 0x00EA
|
||||
#define CONTROL_PADCONF_DSS_DATA8 0x00EC
|
||||
#define CONTROL_PADCONF_DSS_DATA9 0x00EE
|
||||
#define CONTROL_PADCONF_DSS_DATA10 0x00F0
|
||||
#define CONTROL_PADCONF_DSS_DATA11 0x00F2
|
||||
#define CONTROL_PADCONF_DSS_DATA12 0x00F4
|
||||
#define CONTROL_PADCONF_DSS_DATA13 0x00F6
|
||||
#define CONTROL_PADCONF_DSS_DATA14 0x00F8
|
||||
#define CONTROL_PADCONF_DSS_DATA15 0x00FA
|
||||
#define CONTROL_PADCONF_DSS_DATA16 0x00FC
|
||||
#define CONTROL_PADCONF_DSS_DATA17 0x00FE
|
||||
#define CONTROL_PADCONF_DSS_DATA18 0x0100
|
||||
#define CONTROL_PADCONF_DSS_DATA19 0x0102
|
||||
#define CONTROL_PADCONF_DSS_DATA20 0x0104
|
||||
#define CONTROL_PADCONF_DSS_DATA21 0x0106
|
||||
#define CONTROL_PADCONF_DSS_DATA22 0x0108
|
||||
#define CONTROL_PADCONF_DSS_DATA23 0x010A
|
||||
/*CAMERA*/
|
||||
#define CONTROL_PADCONF_CAM_HS 0x010C
|
||||
#define CONTROL_PADCONF_CAM_VS 0x010E
|
||||
#define CONTROL_PADCONF_CAM_XCLKA 0x0110
|
||||
#define CONTROL_PADCONF_CAM_PCLK 0x0112
|
||||
#define CONTROL_PADCONF_CAM_FLD 0x0114
|
||||
#define CONTROL_PADCONF_CAM_D0 0x0116
|
||||
#define CONTROL_PADCONF_CAM_D1 0x0118
|
||||
#define CONTROL_PADCONF_CAM_D2 0x011A
|
||||
#define CONTROL_PADCONF_CAM_D3 0x011C
|
||||
#define CONTROL_PADCONF_CAM_D4 0x011E
|
||||
#define CONTROL_PADCONF_CAM_D5 0x0120
|
||||
#define CONTROL_PADCONF_CAM_D6 0x0122
|
||||
#define CONTROL_PADCONF_CAM_D7 0x0124
|
||||
#define CONTROL_PADCONF_CAM_D8 0x0126
|
||||
#define CONTROL_PADCONF_CAM_D9 0x0128
|
||||
#define CONTROL_PADCONF_CAM_D10 0x012A
|
||||
#define CONTROL_PADCONF_CAM_D11 0x012C
|
||||
#define CONTROL_PADCONF_CAM_XCLKB 0x012E
|
||||
#define CONTROL_PADCONF_CAM_WEN 0x0130
|
||||
#define CONTROL_PADCONF_CAM_STROBE 0x0132
|
||||
#define CONTROL_PADCONF_CSI2_DX0 0x0134
|
||||
#define CONTROL_PADCONF_CSI2_DY0 0x0136
|
||||
#define CONTROL_PADCONF_CSI2_DX1 0x0138
|
||||
#define CONTROL_PADCONF_CSI2_DY1 0x013A
|
||||
/*Audio Interface */
|
||||
#define CONTROL_PADCONF_MCBSP2_FSX 0x013C
|
||||
#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E
|
||||
#define CONTROL_PADCONF_MCBSP2_DR 0x0140
|
||||
#define CONTROL_PADCONF_MCBSP2_DX 0x0142
|
||||
#define CONTROL_PADCONF_MMC1_CLK 0x0144
|
||||
#define CONTROL_PADCONF_MMC1_CMD 0x0146
|
||||
#define CONTROL_PADCONF_MMC1_DAT0 0x0148
|
||||
#define CONTROL_PADCONF_MMC1_DAT1 0x014A
|
||||
#define CONTROL_PADCONF_MMC1_DAT2 0x014C
|
||||
#define CONTROL_PADCONF_MMC1_DAT3 0x014E
|
||||
#define CONTROL_PADCONF_MMC1_DAT4 0x0150
|
||||
#define CONTROL_PADCONF_MMC1_DAT5 0x0152
|
||||
#define CONTROL_PADCONF_MMC1_DAT6 0x0154
|
||||
#define CONTROL_PADCONF_MMC1_DAT7 0x0156
|
||||
/*Wireless LAN */
|
||||
#define CONTROL_PADCONF_MMC2_CLK 0x0158
|
||||
#define CONTROL_PADCONF_MMC2_CMD 0x015A
|
||||
#define CONTROL_PADCONF_MMC2_DAT0 0x015C
|
||||
#define CONTROL_PADCONF_MMC2_DAT1 0x015E
|
||||
#define CONTROL_PADCONF_MMC2_DAT2 0x0160
|
||||
#define CONTROL_PADCONF_MMC2_DAT3 0x0162
|
||||
#define CONTROL_PADCONF_MMC2_DAT4 0x0164
|
||||
#define CONTROL_PADCONF_MMC2_DAT5 0x0166
|
||||
#define CONTROL_PADCONF_MMC2_DAT6 0x0168
|
||||
#define CONTROL_PADCONF_MMC2_DAT7 0x016A
|
||||
/*Bluetooth*/
|
||||
#define CONTROL_PADCONF_MCBSP3_DX 0x016C
|
||||
#define CONTROL_PADCONF_MCBSP3_DR 0x016E
|
||||
#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170
|
||||
#define CONTROL_PADCONF_MCBSP3_FSX 0x0172
|
||||
#define CONTROL_PADCONF_UART2_CTS 0x0174
|
||||
#define CONTROL_PADCONF_UART2_RTS 0x0176
|
||||
#define CONTROL_PADCONF_UART2_TX 0x0178
|
||||
#define CONTROL_PADCONF_UART2_RX 0x017A
|
||||
/*Modem Interface */
|
||||
#define CONTROL_PADCONF_UART1_TX 0x017C
|
||||
#define CONTROL_PADCONF_UART1_RTS 0x017E
|
||||
#define CONTROL_PADCONF_UART1_CTS 0x0180
|
||||
#define CONTROL_PADCONF_UART1_RX 0x0182
|
||||
#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184
|
||||
#define CONTROL_PADCONF_MCBSP4_DR 0x0186
|
||||
#define CONTROL_PADCONF_MCBSP4_DX 0x0188
|
||||
#define CONTROL_PADCONF_MCBSP4_FSX 0x018A
|
||||
#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C
|
||||
#define CONTROL_PADCONF_MCBSP1_FSR 0x018E
|
||||
#define CONTROL_PADCONF_MCBSP1_DX 0x0190
|
||||
#define CONTROL_PADCONF_MCBSP1_DR 0x0192
|
||||
#define CONTROL_PADCONF_MCBSP_CLKS 0x0194
|
||||
#define CONTROL_PADCONF_MCBSP1_FSX 0x0196
|
||||
#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198
|
||||
/*Serial Interface*/
|
||||
#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A
|
||||
#define CONTROL_PADCONF_UART3_RTS_SD 0x019C
|
||||
#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E
|
||||
#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0
|
||||
#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2
|
||||
#define CONTROL_PADCONF_HSUSB0_STP 0x01A4
|
||||
#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6
|
||||
#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8
|
||||
#define CONTROL_PADCONF_I2C1_SCL 0x01BA
|
||||
#define CONTROL_PADCONF_I2C1_SDA 0x01BC
|
||||
#define CONTROL_PADCONF_I2C2_SCL 0x01BE
|
||||
#define CONTROL_PADCONF_I2C2_SDA 0x01C0
|
||||
#define CONTROL_PADCONF_I2C3_SCL 0x01C2
|
||||
#define CONTROL_PADCONF_I2C3_SDA 0x01C4
|
||||
#define CONTROL_PADCONF_I2C4_SCL 0x0A00
|
||||
#define CONTROL_PADCONF_I2C4_SDA 0x0A02
|
||||
#define CONTROL_PADCONF_HDQ_SIO 0x01C6
|
||||
#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8
|
||||
#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA
|
||||
#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC
|
||||
#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE
|
||||
#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0
|
||||
#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2
|
||||
#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4
|
||||
#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6
|
||||
#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8
|
||||
#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA
|
||||
#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC
|
||||
#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE
|
||||
/*Control and debug */
|
||||
#define CONTROL_PADCONF_SYS_32K 0x0A04
|
||||
#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06
|
||||
#define CONTROL_PADCONF_SYS_NIRQ 0x01E0
|
||||
#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A
|
||||
#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C
|
||||
#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E
|
||||
#define CONTROL_PADCONF_SYS_BOOT3 0x0A10
|
||||
#define CONTROL_PADCONF_SYS_BOOT4 0x0A12
|
||||
#define CONTROL_PADCONF_SYS_BOOT5 0x0A14
|
||||
#define CONTROL_PADCONF_SYS_BOOT6 0x0A16
|
||||
#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
|
||||
#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
|
||||
#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
|
||||
#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C
|
||||
#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
|
||||
#define CONTROL_PADCONF_JTAG_TMS 0x0A20
|
||||
#define CONTROL_PADCONF_JTAG_TDI 0x0A22
|
||||
#define CONTROL_PADCONF_JTAG_EMU0 0x0A24
|
||||
#define CONTROL_PADCONF_JTAG_EMU1 0x0A26
|
||||
#define CONTROL_PADCONF_ETK_CLK 0x0A28
|
||||
#define CONTROL_PADCONF_ETK_CTL 0x0A2A
|
||||
#define CONTROL_PADCONF_ETK_D0 0x0A2C
|
||||
#define CONTROL_PADCONF_ETK_D1 0x0A2E
|
||||
#define CONTROL_PADCONF_ETK_D2 0x0A30
|
||||
#define CONTROL_PADCONF_ETK_D3 0x0A32
|
||||
#define CONTROL_PADCONF_ETK_D4 0x0A34
|
||||
#define CONTROL_PADCONF_ETK_D5 0x0A36
|
||||
#define CONTROL_PADCONF_ETK_D6 0x0A38
|
||||
#define CONTROL_PADCONF_ETK_D7 0x0A3A
|
||||
#define CONTROL_PADCONF_ETK_D8 0x0A3C
|
||||
#define CONTROL_PADCONF_ETK_D9 0x0A3E
|
||||
#define CONTROL_PADCONF_ETK_D10 0x0A40
|
||||
#define CONTROL_PADCONF_ETK_D11 0x0A42
|
||||
#define CONTROL_PADCONF_ETK_D12 0x0A44
|
||||
#define CONTROL_PADCONF_ETK_D13 0x0A46
|
||||
#define CONTROL_PADCONF_ETK_D14 0x0A48
|
||||
#define CONTROL_PADCONF_ETK_D15 0x0A4A
|
||||
#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8
|
||||
#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA
|
||||
#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC
|
||||
#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE
|
||||
#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0
|
||||
#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2
|
||||
#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4
|
||||
#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6
|
||||
#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8
|
||||
#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA
|
||||
#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC
|
||||
#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE
|
||||
#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0
|
||||
#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2
|
||||
#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4
|
||||
#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
|
||||
#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
|
||||
#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
|
||||
#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
|
||||
#define CONTROL_PADCONF_JTAG_TDO 0x0A50
|
||||
/*Die to Die */
|
||||
#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
|
||||
#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
|
||||
#define CONTROL_PADCONF_D2D_MCAD2 0x01E8
|
||||
#define CONTROL_PADCONF_D2D_MCAD3 0x01EA
|
||||
#define CONTROL_PADCONF_D2D_MCAD4 0x01EC
|
||||
#define CONTROL_PADCONF_D2D_MCAD5 0x01EE
|
||||
#define CONTROL_PADCONF_D2D_MCAD6 0x01F0
|
||||
#define CONTROL_PADCONF_D2D_MCAD7 0x01F2
|
||||
#define CONTROL_PADCONF_D2D_MCAD8 0x01F4
|
||||
#define CONTROL_PADCONF_D2D_MCAD9 0x01F6
|
||||
#define CONTROL_PADCONF_D2D_MCAD10 0x01F8
|
||||
#define CONTROL_PADCONF_D2D_MCAD11 0x01FA
|
||||
#define CONTROL_PADCONF_D2D_MCAD12 0x01FC
|
||||
#define CONTROL_PADCONF_D2D_MCAD13 0x01FE
|
||||
#define CONTROL_PADCONF_D2D_MCAD14 0x0200
|
||||
#define CONTROL_PADCONF_D2D_MCAD15 0x0202
|
||||
#define CONTROL_PADCONF_D2D_MCAD16 0x0204
|
||||
#define CONTROL_PADCONF_D2D_MCAD17 0x0206
|
||||
#define CONTROL_PADCONF_D2D_MCAD18 0x0208
|
||||
#define CONTROL_PADCONF_D2D_MCAD19 0x020A
|
||||
#define CONTROL_PADCONF_D2D_MCAD20 0x020C
|
||||
#define CONTROL_PADCONF_D2D_MCAD21 0x020E
|
||||
#define CONTROL_PADCONF_D2D_MCAD22 0x0210
|
||||
#define CONTROL_PADCONF_D2D_MCAD23 0x0212
|
||||
#define CONTROL_PADCONF_D2D_MCAD24 0x0214
|
||||
#define CONTROL_PADCONF_D2D_MCAD25 0x0216
|
||||
#define CONTROL_PADCONF_D2D_MCAD26 0x0218
|
||||
#define CONTROL_PADCONF_D2D_MCAD27 0x021A
|
||||
#define CONTROL_PADCONF_D2D_MCAD28 0x021C
|
||||
#define CONTROL_PADCONF_D2D_MCAD29 0x021E
|
||||
#define CONTROL_PADCONF_D2D_MCAD30 0x0220
|
||||
#define CONTROL_PADCONF_D2D_MCAD31 0x0222
|
||||
#define CONTROL_PADCONF_D2D_MCAD32 0x0224
|
||||
#define CONTROL_PADCONF_D2D_MCAD33 0x0226
|
||||
#define CONTROL_PADCONF_D2D_MCAD34 0x0228
|
||||
#define CONTROL_PADCONF_D2D_MCAD35 0x022A
|
||||
#define CONTROL_PADCONF_D2D_MCAD36 0x022C
|
||||
#define CONTROL_PADCONF_D2D_CLK26MI 0x022E
|
||||
#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230
|
||||
#define CONTROL_PADCONF_D2D_NRESWARM 0x0232
|
||||
#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234
|
||||
#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236
|
||||
#define CONTROL_PADCONF_D2D_SPINT 0x0238
|
||||
#define CONTROL_PADCONF_D2D_FRINT 0x023A
|
||||
#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C
|
||||
#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E
|
||||
#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240
|
||||
#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242
|
||||
#define CONTROL_PADCONF_D2D_N3GTRST 0x0244
|
||||
#define CONTROL_PADCONF_D2D_N3GTDI 0x0246
|
||||
#define CONTROL_PADCONF_D2D_N3GTDO 0x0248
|
||||
#define CONTROL_PADCONF_D2D_N3GTMS 0x024A
|
||||
#define CONTROL_PADCONF_D2D_N3GTCK 0x024C
|
||||
#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E
|
||||
#define CONTROL_PADCONF_D2D_MSTDBY 0x0250
|
||||
#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C
|
||||
#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252
|
||||
#define CONTROL_PADCONF_D2D_IDLEACK 0x0254
|
||||
#define CONTROL_PADCONF_D2D_MWRITE 0x0256
|
||||
#define CONTROL_PADCONF_D2D_SWRITE 0x0258
|
||||
#define CONTROL_PADCONF_D2D_MREAD 0x025A
|
||||
#define CONTROL_PADCONF_D2D_SREAD 0x025C
|
||||
#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E
|
||||
#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260
|
||||
#define CONTROL_PADCONF_SDRC_CKE0 0x0262
|
||||
#define CONTROL_PADCONF_SDRC_CKE1 0x0264
|
||||
|
||||
/* AM3517 specific mux configuration */
|
||||
#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
|
||||
/* CCDC */
|
||||
#define CONTROL_PADCONF_CCDC_PCLK 0x01E4
|
||||
#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
|
||||
#define CONTROL_PADCONF_CCDC_HD 0x01E8
|
||||
#define CONTROL_PADCONF_CCDC_VD 0x01EA
|
||||
#define CONTROL_PADCONF_CCDC_WEN 0x01EC
|
||||
#define CONTROL_PADCONF_CCDC_DATA0 0x01EE
|
||||
#define CONTROL_PADCONF_CCDC_DATA1 0x01F0
|
||||
#define CONTROL_PADCONF_CCDC_DATA2 0x01F2
|
||||
#define CONTROL_PADCONF_CCDC_DATA3 0x01F4
|
||||
#define CONTROL_PADCONF_CCDC_DATA4 0x01F6
|
||||
#define CONTROL_PADCONF_CCDC_DATA5 0x01F8
|
||||
#define CONTROL_PADCONF_CCDC_DATA6 0x01FA
|
||||
#define CONTROL_PADCONF_CCDC_DATA7 0x01FC
|
||||
/* RMII */
|
||||
#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
|
||||
#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
|
||||
#define CONTROL_PADCONF_RMII_RXD0 0x0202
|
||||
#define CONTROL_PADCONF_RMII_RXD1 0x0204
|
||||
#define CONTROL_PADCONF_RMII_CRS_DV 0x0206
|
||||
#define CONTROL_PADCONF_RMII_RXER 0x0208
|
||||
#define CONTROL_PADCONF_RMII_TXD0 0x020A
|
||||
#define CONTROL_PADCONF_RMII_TXD1 0x020C
|
||||
#define CONTROL_PADCONF_RMII_TXEN 0x020E
|
||||
#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
|
||||
#define CONTROL_PADCONF_USB0_DRVBUS 0x0212
|
||||
/* CAN */
|
||||
#define CONTROL_PADCONF_HECC1_TXD 0x0214
|
||||
#define CONTROL_PADCONF_HECC1_RXD 0x0216
|
||||
|
||||
#define CONTROL_PADCONF_SYS_BOOT7 0x0218
|
||||
#define CONTROL_PADCONF_SDRC_DQS0N 0x021A
|
||||
#define CONTROL_PADCONF_SDRC_DQS1N 0x021C
|
||||
#define CONTROL_PADCONF_SDRC_DQS2N 0x021E
|
||||
#define CONTROL_PADCONF_SDRC_DQS3N 0x0220
|
||||
#define CONTROL_PADCONF_STRBEN_DLY0 0x0222
|
||||
#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
|
||||
#define CONTROL_PADCONF_SYS_BOOT8 0x0226
|
||||
|
||||
/* AM/DM37xx specific */
|
||||
#define CONTROL_PADCONF_GPIO112 0x0134
|
||||
#define CONTROL_PADCONF_GPIO113 0x0136
|
||||
#define CONTROL_PADCONF_GPIO114 0x0138
|
||||
#define CONTROL_PADCONF_GPIO115 0x013A
|
||||
#define CONTROL_PADCONF_GPIO127 0x0A54
|
||||
#define CONTROL_PADCONF_GPIO126 0x0A56
|
||||
#define CONTROL_PADCONF_GPIO128 0x0A58
|
||||
#define CONTROL_PADCONF_GPIO129 0x0A5A
|
||||
|
||||
/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
|
||||
* of the extended drain cells */
|
||||
#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C)
|
||||
#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
|
||||
|
||||
#define MUX_VAL(OFFSET, VALUE)\
|
||||
writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
|
||||
|
||||
#define CP(x) (CONTROL_PADCONF_##x)
|
||||
|
||||
#endif
|
||||
270
u-boot/arch/arm/include/asm/arch-omap3/omap.h
Normal file
270
u-boot/arch/arm/include/asm/arch-omap3/omap.h
Normal file
@@ -0,0 +1,270 @@
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <x0khasim@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _OMAP3_H_
|
||||
#define _OMAP3_H_
|
||||
|
||||
/* Stuff on L3 Interconnect */
|
||||
#define SMX_APE_BASE 0x68000000
|
||||
|
||||
/* GPMC */
|
||||
#define OMAP34XX_GPMC_BASE 0x6E000000
|
||||
|
||||
/* SMS */
|
||||
#define OMAP34XX_SMS_BASE 0x6C000000
|
||||
|
||||
/* SDRC */
|
||||
#define OMAP34XX_SDRC_BASE 0x6D000000
|
||||
|
||||
/*
|
||||
* L4 Peripherals - L4 Wakeup and L4 Core now
|
||||
*/
|
||||
#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
|
||||
#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
|
||||
#define OMAP34XX_ID_L4_IO_BASE 0x4830A200
|
||||
#define OMAP34XX_L4_PER 0x49000000
|
||||
#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
|
||||
|
||||
/* DMA4/SDMA */
|
||||
#define OMAP34XX_DMA4_BASE 0x48056000
|
||||
|
||||
/* CONTROL */
|
||||
#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* Signal Integrity Parameter Control Registers */
|
||||
struct control_prog_io {
|
||||
unsigned char res[0x408];
|
||||
unsigned int io2; /* 0x408 */
|
||||
unsigned char res2[0x38];
|
||||
unsigned int io0; /* 0x444 */
|
||||
unsigned int io1; /* 0x448 */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* Bit definition for CONTROL_PROG_IO1 */
|
||||
#define PRG_I2C2_PULLUPRESX 0x00000001
|
||||
|
||||
/* Scratchpad memory */
|
||||
#define OMAP34XX_SCRATCHPAD (OMAP34XX_CTRL_BASE + 0x910)
|
||||
|
||||
/* UART */
|
||||
#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
|
||||
#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
|
||||
#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
|
||||
#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
|
||||
|
||||
/* General Purpose Timers */
|
||||
#define OMAP34XX_GPT1 0x48318000
|
||||
#define OMAP34XX_GPT2 0x49032000
|
||||
#define OMAP34XX_GPT3 0x49034000
|
||||
#define OMAP34XX_GPT4 0x49036000
|
||||
#define OMAP34XX_GPT5 0x49038000
|
||||
#define OMAP34XX_GPT6 0x4903A000
|
||||
#define OMAP34XX_GPT7 0x4903C000
|
||||
#define OMAP34XX_GPT8 0x4903E000
|
||||
#define OMAP34XX_GPT9 0x49040000
|
||||
#define OMAP34XX_GPT10 0x48086000
|
||||
#define OMAP34XX_GPT11 0x48088000
|
||||
#define OMAP34XX_GPT12 0x48304000
|
||||
|
||||
/* WatchDog Timers (1 secure, 3 GP) */
|
||||
#define WD1_BASE 0x4830C000
|
||||
#define WD2_BASE 0x48314000
|
||||
#define WD3_BASE 0x49030000
|
||||
|
||||
/* 32KTIMER */
|
||||
#define SYNC_32KTIMER_BASE 0x48320000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct s32ktimer {
|
||||
unsigned char res[0x10];
|
||||
unsigned int s32k_cr; /* 0x10 */
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gpio {
|
||||
unsigned char res1[0x34];
|
||||
unsigned int oe; /* 0x34 */
|
||||
unsigned int datain; /* 0x38 */
|
||||
unsigned char res2[0x54];
|
||||
unsigned int cleardataout; /* 0x90 */
|
||||
unsigned int setdataout; /* 0x94 */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define GPIO0 (0x1 << 0)
|
||||
#define GPIO1 (0x1 << 1)
|
||||
#define GPIO2 (0x1 << 2)
|
||||
#define GPIO3 (0x1 << 3)
|
||||
#define GPIO4 (0x1 << 4)
|
||||
#define GPIO5 (0x1 << 5)
|
||||
#define GPIO6 (0x1 << 6)
|
||||
#define GPIO7 (0x1 << 7)
|
||||
#define GPIO8 (0x1 << 8)
|
||||
#define GPIO9 (0x1 << 9)
|
||||
#define GPIO10 (0x1 << 10)
|
||||
#define GPIO11 (0x1 << 11)
|
||||
#define GPIO12 (0x1 << 12)
|
||||
#define GPIO13 (0x1 << 13)
|
||||
#define GPIO14 (0x1 << 14)
|
||||
#define GPIO15 (0x1 << 15)
|
||||
#define GPIO16 (0x1 << 16)
|
||||
#define GPIO17 (0x1 << 17)
|
||||
#define GPIO18 (0x1 << 18)
|
||||
#define GPIO19 (0x1 << 19)
|
||||
#define GPIO20 (0x1 << 20)
|
||||
#define GPIO21 (0x1 << 21)
|
||||
#define GPIO22 (0x1 << 22)
|
||||
#define GPIO23 (0x1 << 23)
|
||||
#define GPIO24 (0x1 << 24)
|
||||
#define GPIO25 (0x1 << 25)
|
||||
#define GPIO26 (0x1 << 26)
|
||||
#define GPIO27 (0x1 << 27)
|
||||
#define GPIO28 (0x1 << 28)
|
||||
#define GPIO29 (0x1 << 29)
|
||||
#define GPIO30 (0x1 << 30)
|
||||
#define GPIO31 (0x1 << 31)
|
||||
|
||||
/* base address for indirect vectors (internal boot mode) */
|
||||
#define SRAM_OFFSET0 0x40000000
|
||||
#define SRAM_OFFSET1 0x00200000
|
||||
#define SRAM_OFFSET2 0x0000F800
|
||||
#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
|
||||
SRAM_OFFSET2)
|
||||
#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64)
|
||||
|
||||
#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
|
||||
#define NON_SECURE_SRAM_END 0x40210000
|
||||
#define SRAM_SCRATCH_SPACE_ADDR 0x4020E000
|
||||
|
||||
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
|
||||
|
||||
/* scratch area - accessible on both EMU and GP */
|
||||
#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
|
||||
|
||||
#define DEBUG_LED1 149 /* gpio */
|
||||
#define DEBUG_LED2 150 /* gpio */
|
||||
|
||||
#define XDR_POP 5 /* package on package part */
|
||||
#define SDR_DISCRETE 4 /* 128M memory SDR module */
|
||||
#define DDR_STACKED 3 /* stacked part on 2422 */
|
||||
#define DDR_COMBO 2 /* combo part on cpu daughter card */
|
||||
#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
|
||||
|
||||
#define DDR_100 100 /* type found on most mem d-boards */
|
||||
#define DDR_111 111 /* some combo parts */
|
||||
#define DDR_133 133 /* most combo, some mem d-boards */
|
||||
#define DDR_165 165 /* future parts */
|
||||
|
||||
#define CPU_3430 0x3430
|
||||
|
||||
/*
|
||||
* 343x real hardware:
|
||||
* ES1 = rev 0
|
||||
*
|
||||
* ES2 onwards, the value maps to contents of IDCODE register [31:28].
|
||||
*
|
||||
* Note : CPU_3XX_ES20 is used in cache.S. Please review before changing.
|
||||
*/
|
||||
#define CPU_3XX_ES10 0
|
||||
#define CPU_3XX_ES20 1
|
||||
#define CPU_3XX_ES21 2
|
||||
#define CPU_3XX_ES30 3
|
||||
#define CPU_3XX_ES31 4
|
||||
#define CPU_3XX_ES312 7
|
||||
#define CPU_3XX_MAX_REV 8
|
||||
|
||||
/*
|
||||
* 37xx real hardware:
|
||||
* ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
|
||||
*/
|
||||
|
||||
#define CPU_37XX_ES10 0
|
||||
#define CPU_37XX_ES11 1
|
||||
#define CPU_37XX_ES12 2
|
||||
#define CPU_37XX_MAX_REV 3
|
||||
|
||||
#define CPU_3XX_ID_SHIFT 28
|
||||
|
||||
#define WIDTH_8BIT 0x0000
|
||||
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
|
||||
|
||||
/*
|
||||
* Hawkeye values
|
||||
*/
|
||||
#define HAWKEYE_OMAP34XX 0xb7ae
|
||||
#define HAWKEYE_AM35XX 0xb868
|
||||
#define HAWKEYE_OMAP36XX 0xb891
|
||||
|
||||
#define HAWKEYE_SHIFT 12
|
||||
|
||||
/*
|
||||
* Define CPU families
|
||||
*/
|
||||
#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
|
||||
#define CPU_AM35XX 0x3500 /* AM35xx devices */
|
||||
#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
|
||||
|
||||
/*
|
||||
* Control status register values corresponding to cpu variants
|
||||
*/
|
||||
#define OMAP3503 0x5c00
|
||||
#define OMAP3515 0x1c00
|
||||
#define OMAP3525 0x4c00
|
||||
#define OMAP3530 0x0c00
|
||||
|
||||
#define AM3505 0x5c00
|
||||
#define AM3517 0x1c00
|
||||
|
||||
#define OMAP3730 0x0c00
|
||||
|
||||
/*
|
||||
* ROM code API related flags
|
||||
*/
|
||||
#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
|
||||
#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
|
||||
|
||||
/*
|
||||
* EMU device PPA HAL related flags
|
||||
*/
|
||||
#define OMAP3_EMU_HAL_API_L2_INVAL 40
|
||||
#define OMAP3_EMU_HAL_API_WRITE_ACR 42
|
||||
|
||||
#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4
|
||||
|
||||
/* ABB settings */
|
||||
#define OMAP_ABB_SETTLING_TIME 30
|
||||
#define OMAP_ABB_CLOCK_CYCLES 8
|
||||
|
||||
/* ABB tranxdone mask */
|
||||
#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26)
|
||||
|
||||
#define OMAP_REBOOT_REASON_OFFSET 0x04
|
||||
|
||||
/* Boot parameters */
|
||||
#ifndef __ASSEMBLY__
|
||||
struct omap_boot_parameters {
|
||||
unsigned int boot_message;
|
||||
unsigned char boot_device;
|
||||
unsigned char reserved;
|
||||
unsigned char reset_reason;
|
||||
unsigned char ch_flags;
|
||||
unsigned int boot_device_descriptor;
|
||||
};
|
||||
|
||||
int omap_reboot_mode(char *mode, unsigned int length);
|
||||
int omap_reboot_mode_clear(void);
|
||||
int omap_reboot_mode_store(char *mode);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
79
u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h
Normal file
79
u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h
Normal file
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _OMAP3_REGS_H
|
||||
#define _OMAP3_REGS_H
|
||||
|
||||
/*
|
||||
* Register definitions for OMAP3 processors.
|
||||
*/
|
||||
|
||||
/*
|
||||
* GPMC_CONFIG1 - GPMC_CONFIG7
|
||||
*/
|
||||
|
||||
/* Values for GPMC_CONFIG1 - signal control parameters */
|
||||
#define WRAPBURST (1 << 31)
|
||||
#define READMULTIPLE (1 << 30)
|
||||
#define READTYPE (1 << 29)
|
||||
#define WRITEMULTIPLE (1 << 28)
|
||||
#define WRITETYPE (1 << 27)
|
||||
#define CLKACTIVATIONTIME(x) (((x) & 3) << 25)
|
||||
#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23)
|
||||
#define WAITREADMONITORING (1 << 22)
|
||||
#define WAITWRITEMONITORING (1 << 21)
|
||||
#define WAITMONITORINGTIME(x) (((x) & 3) << 18)
|
||||
#define WAITPINSELECT(x) (((x) & 3) << 16)
|
||||
#define DEVICESIZE(x) (((x) & 3) << 12)
|
||||
#define DEVICESIZE_8BIT DEVICESIZE(0)
|
||||
#define DEVICESIZE_16BIT DEVICESIZE(1)
|
||||
#define DEVICETYPE(x) (((x) & 3) << 10)
|
||||
#define DEVICETYPE_NOR DEVICETYPE(0)
|
||||
#define DEVICETYPE_NAND DEVICETYPE(2)
|
||||
#define MUXADDDATA (1 << 9)
|
||||
#define TIMEPARAGRANULARITY (1 << 4)
|
||||
#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG2 - CS timing */
|
||||
#define CSWROFFTIME(x) (((x) & 0x1f) << 16)
|
||||
#define CSRDOFFTIME(x) (((x) & 0x1f) << 8)
|
||||
#define CSEXTRADELAY (1 << 7)
|
||||
#define CSONTIME(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG3 - nADV timing */
|
||||
#define ADVWROFFTIME(x) (((x) & 0x1f) << 16)
|
||||
#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8)
|
||||
#define ADVEXTRADELAY (1 << 7)
|
||||
#define ADVONTIME(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG4 - nWE and nOE timing */
|
||||
#define WEOFFTIME(x) (((x) & 0x1f) << 24)
|
||||
#define WEEXTRADELAY (1 << 23)
|
||||
#define WEONTIME(x) (((x) & 0xf) << 16)
|
||||
#define OEOFFTIME(x) (((x) & 0x1f) << 8)
|
||||
#define OEEXTRADELAY (1 << 7)
|
||||
#define OEONTIME(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
|
||||
#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24)
|
||||
#define RDACCESSTIME(x) (((x) & 0x1f) << 16)
|
||||
#define WRCYCLETIME(x) (((x) & 0x1f) << 8)
|
||||
#define RDCYCLETIME(x) (((x) & 0x1f) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG6 - misc timings */
|
||||
#define WRACCESSTIME(x) (((x) & 0x1f) << 24)
|
||||
#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16)
|
||||
#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8)
|
||||
#define CYCLE2CYCLESAMECSEN (1 << 7)
|
||||
#define CYCLE2CYCLEDIFFCSEN (1 << 6)
|
||||
#define BUSTURNAROUND(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG7 - CS address mapping configuration */
|
||||
#define MASKADDRESS(x) (((x) & 0xf) << 8)
|
||||
#define CSVALID (1 << 6)
|
||||
#define BASEADDRESS(x) (((x) & 0x3f) << 0)
|
||||
|
||||
#endif /* _OMAP3_REGS_H */
|
||||
23
u-boot/arch/arm/include/asm/arch-omap3/spl.h
Normal file
23
u-boot/arch/arm/include/asm/arch-omap3/spl.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_NONE 0x00
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_NAND 0x02
|
||||
#define BOOT_DEVICE_ONENAND 0x03
|
||||
#define BOOT_DEVICE_MMC2 0x05
|
||||
#define BOOT_DEVICE_MMC1 0x06
|
||||
#define BOOT_DEVICE_XIPWAIT 0x07
|
||||
#define BOOT_DEVICE_MMC2_2 0x08
|
||||
#define BOOT_DEVICE_UART 0x10
|
||||
#define BOOT_DEVICE_USB 0x11
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
|
||||
#endif
|
||||
77
u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h
Normal file
77
u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h
Normal file
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
#include <linux/mtd/omap_gpmc.h>
|
||||
#include <asm/omap_common.h>
|
||||
|
||||
typedef struct {
|
||||
u32 mtype;
|
||||
char *board_string;
|
||||
char *nand_string;
|
||||
} omap3_sysinfo;
|
||||
|
||||
struct emu_hal_params {
|
||||
u32 num_params;
|
||||
u32 param1;
|
||||
};
|
||||
|
||||
/* Board SDRC timing values */
|
||||
struct board_sdrc_timings {
|
||||
u32 sharing;
|
||||
u32 mcfg;
|
||||
u32 ctrla;
|
||||
u32 ctrlb;
|
||||
u32 rfr_ctrl;
|
||||
u32 mr;
|
||||
};
|
||||
|
||||
void prcm_init(void);
|
||||
void per_clocks_enable(void);
|
||||
void ehci_clocks_enable(void);
|
||||
|
||||
void memif_init(void);
|
||||
void sdrc_init(void);
|
||||
void do_sdrc_init(u32, u32);
|
||||
|
||||
void get_board_mem_timings(struct board_sdrc_timings *timings);
|
||||
void identify_nand_chip(int *mfr, int *id);
|
||||
void emif4_init(void);
|
||||
void gpmc_init(void);
|
||||
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
|
||||
u32 size);
|
||||
|
||||
void watchdog_init(void);
|
||||
void set_muxconf_regs(void);
|
||||
|
||||
u32 get_cpu_family(void);
|
||||
u32 get_cpu_rev(void);
|
||||
u32 get_sku_id(void);
|
||||
u32 is_gpmc_muxed(void);
|
||||
u32 get_gpmc0_type(void);
|
||||
u32 get_gpmc0_width(void);
|
||||
u32 is_running_in_sdram(void);
|
||||
u32 is_running_in_sram(void);
|
||||
u32 is_running_in_flash(void);
|
||||
u32 get_device_type(void);
|
||||
void secureworld_exit(void);
|
||||
void try_unlock_memory(void);
|
||||
u32 get_boot_type(void);
|
||||
void invalidate_dcache(u32);
|
||||
u32 wait_on_value(u32, u32, void *, u32);
|
||||
void cancel_out(u32 *num, u32 *den, u32 den_limit);
|
||||
void sdelay(unsigned long);
|
||||
void make_cs1_contiguous(void);
|
||||
void omap_nand_switch_ecc(uint32_t, uint32_t);
|
||||
void power_init_r(void);
|
||||
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
|
||||
void omap3_set_aux_cr_secure(u32 acr);
|
||||
u32 warm_reset(void);
|
||||
|
||||
void save_omap_boot_params(void);
|
||||
#endif
|
||||
Reference in New Issue
Block a user