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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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82
u-boot/arch/arm/include/asm/arch-mx6/clock.h Normal file
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/*
* (C) Copyright 2009
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#include <common.h>
#ifdef CONFIG_SYS_MX6_HCLK
#define MXC_HCLK CONFIG_SYS_MX6_HCLK
#else
#define MXC_HCLK 24000000
#endif
#ifdef CONFIG_SYS_MX6_CLK32
#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
#else
#define MXC_CLK32 32768
#endif
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_PER_CLK,
MXC_AHB_CLK,
MXC_IPG_CLK,
MXC_IPG_PERCLK,
MXC_UART_CLK,
MXC_CSPI_CLK,
MXC_AXI_CLK,
MXC_EMI_SLOW_CLK,
MXC_DDR_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
MXC_ESDHC3_CLK,
MXC_ESDHC4_CLK,
MXC_SATA_CLK,
MXC_NFC_CLK,
MXC_I2C_CLK,
};
enum ldb_di_clock {
MXC_PLL5_CLK = 0,
MXC_PLL2_PFD0_CLK,
MXC_PLL2_PFD2_CLK,
MXC_MMDC_CH1_CLK,
MXC_PLL3_SW_CLK,
};
enum enet_freq {
ENET_25MHZ,
ENET_50MHZ,
ENET_100MHZ,
ENET_125MHZ,
};
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
void setup_gpmi_io_clk(u32 cfg);
void hab_caam_clock_enable(unsigned char enable);
void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
void enable_uart_clk(unsigned char enable);
int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
int enable_sata_clock(void);
void disable_sata_clock(void);
int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
int enable_lcdif_clock(u32 base_addr);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);
void mxs_set_lcdclk(u32 base_addr, u32 freq);
void select_ldb_di_clock_source(enum ldb_di_clock clk);
#endif /* __ASM_ARCH_CLOCK_H */

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u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h Normal file
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u-boot/arch/arm/include/asm/arch-mx6/gpio.h Normal file
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/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6_GPIO_H
#define __ASM_ARCH_MX6_GPIO_H
#include <asm/imx-common/gpio.h>
#endif /* __ASM_ARCH_MX6_GPIO_H */

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u-boot/arch/arm/include/asm/arch-mx6/imx-rdc.h Normal file
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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_RDC_H__
#define __IMX_RDC_H__
#if defined(CONFIG_MX6SX)
#include "mx6sx_rdc.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6SX */
#endif /* __IMX_RDC_H__*/

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u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h Normal file
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/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
#define __ASM_ARCH_MX6_IMX_REGS_H__
#define ARCH_MXC
#ifdef CONFIG_MX6UL
#define CONFIG_SYS_CACHELINE_SIZE 64
#else
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
#ifdef CONFIG_MX6SL
#define GPU_2D_ARB_BASE_ADDR 0x02200000
#define GPU_2D_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00107FFF
#define GPU_ARB_BASE_ADDR 0x01800000
#define GPU_ARB_END_ADDR 0x01803FFF
#define APBH_DMA_ARB_BASE_ADDR 0x01804000
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
#else
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
#define APBH_DMA_ARB_END_ADDR 0x00117FFF
#define HDMI_ARB_BASE_ADDR 0x00120000
#define HDMI_ARB_END_ADDR 0x00128FFF
#define GPU_3D_ARB_BASE_ADDR 0x00130000
#define GPU_3D_ARB_END_ADDR 0x00133FFF
#define GPU_2D_ARB_BASE_ADDR 0x00134000
#define GPU_2D_ARB_END_ADDR 0x00137FFF
#define DTCP_ARB_BASE_ADDR 0x00138000
#define DTCP_ARB_END_ADDR 0x0013BFFF
#endif /* CONFIG_MX6SL */
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV2_BASE_ADDR 0x00D00000
#else
#define GPV2_BASE_ADDR 0x00200000
#endif
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000
#define GPV6_BASE_ADDR 0x01100000
#define PCIE_ARB_BASE_ADDR 0x08000000
#define PCIE_ARB_END_ADDR 0x08FFFFFF
#else
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
#define PCIE_ARB_BASE_ADDR 0x01000000
#define PCIE_ARB_END_ADDR 0x01FFFFFF
#endif
#define IRAM_BASE_ADDR 0x00900000
#define SCU_BASE_ADDR 0x00A00000
#define IC_INTERFACES_BASE_ADDR 0x00A00100
#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
#define L2_PL310_BASE 0x00A02000
#define GPV0_BASE_ADDR 0x00B00000
#define GPV1_BASE_ADDR 0x00C00000
#define AIPS1_ARB_BASE_ADDR 0x02000000
#define AIPS1_ARB_END_ADDR 0x020FFFFF
#define AIPS2_ARB_BASE_ADDR 0x02100000
#define AIPS2_ARB_END_ADDR 0x021FFFFF
/* AIPS3 only on i.MX6SX */
#define AIPS3_ARB_BASE_ADDR 0x02200000
#define AIPS3_ARB_END_ADDR 0x022FFFFF
#ifdef CONFIG_MX6SX
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#define QSPI1_AMBA_BASE 0x70000000
#define QSPI1_AMBA_END 0x7FFFFFFF
#elif defined(CONFIG_MX6UL)
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#else
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
#define HSI_ARB_BASE_ADDR 0x02208000
#define HSI_ARB_END_ADDR 0x0220BFFF
#define IPU1_ARB_BASE_ADDR 0x02400000
#define IPU1_ARB_END_ADDR 0x027FFFFF
#define IPU2_ARB_BASE_ADDR 0x02800000
#define IPU2_ARB_END_ADDR 0x02BFFFFF
#define WEIM_ARB_BASE_ADDR 0x08000000
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
#else
#define MMDC0_ARB_BASE_ADDR 0x10000000
#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
#define MMDC1_ARB_BASE_ADDR 0x80000000
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
#endif
#ifndef CONFIG_MX6SX
#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
#define IPU_SOC_OFFSET 0x00200000
#endif
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
#ifdef CONFIG_MX6SL
#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
#else
#ifndef CONFIG_MX6SX
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#endif
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
#endif
#ifndef CONFIG_MX6SX
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
#endif
#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
#ifdef CONFIG_MX6SL
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#elif CONFIG_MX6SX
#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
#else
#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#endif
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
#ifdef CONFIG_MX6SL
#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
#else
#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
#endif
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
/* i.MX6SL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#ifdef CONFIG_MX6UL
#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#else
/* i.MX6SX */
#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#endif
/* i.MX6DQ/SDL */
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#ifdef CONFIG_MX6SX
#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#else
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#endif
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
#ifdef CONFIG_MX6UL
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#elif defined(CONFIG_MX6SX)
#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#else
#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#endif
#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#ifdef CONFIG_MX6SX
#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
#endif
/* Only for i.MX6SX */
#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define IRAM_SIZE 0x00040000
#else
#define IRAM_SIZE 0x00020000
#endif
#define FEC_QUIRK_ENET_MAC
#include <asm/imx-common/regs-lcdif.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
/* only for i.MX6SX/UL */
#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \
MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_1_RESET_OFFSET 14
#define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
#define SRC_SCR_CORE_2_RESET_OFFSET 15
#define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
#define SRC_SCR_CORE_3_RESET_OFFSET 16
#define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
#define SRC_SCR_CORE_1_ENABLE_OFFSET 22
#define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
#define SRC_SCR_CORE_2_ENABLE_OFFSET 23
#define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
struct rdc_regs {
u32 vir; /* Version information */
u32 reserved1[8];
u32 stat; /* Status */
u32 intctrl; /* Interrupt and Control */
u32 intstat; /* Interrupt Status */
u32 reserved2[116];
u32 mda[32]; /* Master Domain Assignment */
u32 reserved3[96];
u32 pdap[104]; /* Peripheral Domain Access Permissions */
u32 reserved4[88];
struct {
u32 mrsa; /* Memory Region Start Address */
u32 mrea; /* Memory Region End Address */
u32 mrc; /* Memory Region Control */
u32 mrvs; /* Memory Region Violation Status */
} mem_region[55];
};
struct rdc_sema_regs {
u8 gate[64]; /* Gate */
u16 rstgt; /* Reset Gate */
};
/* WEIM registers */
struct weim {
u32 cs0gcr1;
u32 cs0gcr2;
u32 cs0rcr1;
u32 cs0rcr2;
u32 cs0wcr1;
u32 cs0wcr2;
u32 cs1gcr1;
u32 cs1gcr2;
u32 cs1rcr1;
u32 cs1rcr2;
u32 cs1wcr1;
u32 cs1wcr2;
u32 cs2gcr1;
u32 cs2gcr2;
u32 cs2rcr1;
u32 cs2rcr2;
u32 cs2wcr1;
u32 cs2wcr2;
u32 cs3gcr1;
u32 cs3gcr2;
u32 cs3rcr1;
u32 cs3rcr2;
u32 cs3wcr1;
u32 cs3wcr2;
u32 unused[12];
u32 wcr;
u32 wiar;
u32 ear;
};
/* System Reset Controller (SRC) */
struct src {
u32 scr;
u32 sbmr1;
u32 srsr;
u32 reserved1[2];
u32 sisr;
u32 simr;
u32 sbmr2;
u32 gpr1;
u32 gpr2;
u32 gpr3;
u32 gpr4;
u32 gpr5;
u32 gpr6;
u32 gpr7;
u32 gpr8;
u32 gpr9;
u32 gpr10;
};
#define SRC_SCR_M4_ENABLE_OFFSET 22
#define SRC_SCR_M4_ENABLE_MASK (1 << 22)
#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
/* GPR1 bitfields */
#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
#define IOMUXC_GPR1_DPI_OFF BIT(24)
#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
#define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
#define IOMUXC_GPR1_PCIE_INT BIT(14)
#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
#define IOMUXC_GPR1_GINT BIT(12)
#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
#define IOMUXC_GPR1_ACT_CS3 BIT(9)
#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
#define IOMUXC_GPR1_ACT_CS2 BIT(6)
#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
#define IOMUXC_GPR1_ACT_CS1 BIT(3)
#define IOMUXC_GPR1_ADDRS0_OFFSET (1)
#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
#define IOMUXC_GPR1_ACT_CS0 BIT(0)
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
/* gpr12 bitfields */
#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
struct iomuxc {
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
u8 reserved[0x4000];
#endif
u32 gpr[14];
};
struct gpc {
u32 cntr;
u32 pgr;
u32 imr1;
u32 imr2;
u32 imr3;
u32 imr4;
u32 isr1;
u32 isr2;
u32 isr3;
u32 isr4;
};
#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
#define IOMUXC_GPR2_BITMAP_SPWG 0
#define IOMUXC_GPR2_BITMAP_JEIDA 1
#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_18 0
#define IOMUXC_GPR2_DATA_WIDTH_24 1
#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
#define IOMUXC_GPR2_MODE_DISABLED 0
#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
/* ECSPI registers */
struct cspi_regs {
u32 rxdata;
u32 txdata;
u32 ctrl;
u32 cfg;
u32 intr;
u32 dma;
u32 stat;
u32 period;
};
/*
* CSPI register definitions
*/
#define MXC_ECSPI
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
#define MXC_CSPICTRL_MAXBITS 0xfff
#define MXC_CSPICTRL_TC (1 << 7)
#define MXC_CSPICTRL_RXOVF (1 << 6)
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
#define MAX_SPI_BYTES 32
#define SPI_MAX_NUM 4
/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_PHA 0 /* SCLK phase control */
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
ECSPI3_BASE_ADDR, \
ECSPI4_BASE_ADDR
#else
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
ECSPI3_BASE_ADDR, \
ECSPI4_BASE_ADDR, \
ECSPI5_BASE_ADDR
#endif
struct ocotp_regs {
u32 ctrl;
u32 ctrl_set;
u32 ctrl_clr;
u32 ctrl_tog;
u32 timing;
u32 rsvd0[3];
u32 data;
u32 rsvd1[3];
u32 read_ctrl;
u32 rsvd2[3];
u32 read_fuse_data;
u32 rsvd3[3];
u32 sw_sticky;
u32 rsvd4[3];
u32 scs;
u32 scs_set;
u32 scs_clr;
u32 scs_tog;
u32 crc_addr;
u32 rsvd5[3];
u32 crc_value;
u32 rsvd6[3];
u32 version;
u32 rsvd7[0xdb];
/* fuse banks */
struct fuse_bank {
u32 fuse_regs[0x20];
} bank[0];
};
struct fuse_bank0_regs {
u32 lock;
u32 rsvd0[3];
u32 uid_low;
u32 rsvd1[3];
u32 uid_high;
u32 rsvd2[3];
u32 cfg2;
u32 rsvd3[3];
u32 cfg3;
u32 rsvd4[3];
u32 cfg4;
u32 rsvd5[3];
u32 cfg5;
u32 rsvd6[3];
u32 cfg6;
u32 rsvd7[3];
};
struct fuse_bank1_regs {
u32 mem0;
u32 rsvd0[3];
u32 mem1;
u32 rsvd1[3];
u32 mem2;
u32 rsvd2[3];
u32 mem3;
u32 rsvd3[3];
u32 mem4;
u32 rsvd4[3];
u32 ana0;
u32 rsvd5[3];
u32 ana1;
u32 rsvd6[3];
u32 ana2;
u32 rsvd7[3];
};
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
u32 sjc_resp_high;
u32 rsvd1[3];
u32 mac_addr0;
u32 rsvd2[3];
u32 mac_addr1;
u32 rsvd3[3];
u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
u32 rsvd4[7];
u32 gp1;
u32 rsvd5[3];
u32 gp2;
u32 rsvd6[3];
};
struct aipstz_regs {
u32 mprot0;
u32 mprot1;
u32 rsvd[0xe];
u32 opacr0;
u32 opacr1;
u32 opacr2;
u32 opacr3;
u32 opacr4;
};
struct anatop_regs {
u32 pll_sys; /* 0x000 */
u32 pll_sys_set; /* 0x004 */
u32 pll_sys_clr; /* 0x008 */
u32 pll_sys_tog; /* 0x00c */
u32 usb1_pll_480_ctrl; /* 0x010 */
u32 usb1_pll_480_ctrl_set; /* 0x014 */
u32 usb1_pll_480_ctrl_clr; /* 0x018 */
u32 usb1_pll_480_ctrl_tog; /* 0x01c */
u32 usb2_pll_480_ctrl; /* 0x020 */
u32 usb2_pll_480_ctrl_set; /* 0x024 */
u32 usb2_pll_480_ctrl_clr; /* 0x028 */
u32 usb2_pll_480_ctrl_tog; /* 0x02c */
u32 pll_528; /* 0x030 */
u32 pll_528_set; /* 0x034 */
u32 pll_528_clr; /* 0x038 */
u32 pll_528_tog; /* 0x03c */
u32 pll_528_ss; /* 0x040 */
u32 rsvd0[3];
u32 pll_528_num; /* 0x050 */
u32 rsvd1[3];
u32 pll_528_denom; /* 0x060 */
u32 rsvd2[3];
u32 pll_audio; /* 0x070 */
u32 pll_audio_set; /* 0x074 */
u32 pll_audio_clr; /* 0x078 */
u32 pll_audio_tog; /* 0x07c */
u32 pll_audio_num; /* 0x080 */
u32 rsvd3[3];
u32 pll_audio_denom; /* 0x090 */
u32 rsvd4[3];
u32 pll_video; /* 0x0a0 */
u32 pll_video_set; /* 0x0a4 */
u32 pll_video_clr; /* 0x0a8 */
u32 pll_video_tog; /* 0x0ac */
u32 pll_video_num; /* 0x0b0 */
u32 rsvd5[3];
u32 pll_video_denom; /* 0x0c0 */
u32 rsvd6[3];
u32 pll_mlb; /* 0x0d0 */
u32 pll_mlb_set; /* 0x0d4 */
u32 pll_mlb_clr; /* 0x0d8 */
u32 pll_mlb_tog; /* 0x0dc */
u32 pll_enet; /* 0x0e0 */
u32 pll_enet_set; /* 0x0e4 */
u32 pll_enet_clr; /* 0x0e8 */
u32 pll_enet_tog; /* 0x0ec */
u32 pfd_480; /* 0x0f0 */
u32 pfd_480_set; /* 0x0f4 */
u32 pfd_480_clr; /* 0x0f8 */
u32 pfd_480_tog; /* 0x0fc */
u32 pfd_528; /* 0x100 */
u32 pfd_528_set; /* 0x104 */
u32 pfd_528_clr; /* 0x108 */
u32 pfd_528_tog; /* 0x10c */
u32 reg_1p1; /* 0x110 */
u32 reg_1p1_set; /* 0x114 */
u32 reg_1p1_clr; /* 0x118 */
u32 reg_1p1_tog; /* 0x11c */
u32 reg_3p0; /* 0x120 */
u32 reg_3p0_set; /* 0x124 */
u32 reg_3p0_clr; /* 0x128 */
u32 reg_3p0_tog; /* 0x12c */
u32 reg_2p5; /* 0x130 */
u32 reg_2p5_set; /* 0x134 */
u32 reg_2p5_clr; /* 0x138 */
u32 reg_2p5_tog; /* 0x13c */
u32 reg_core; /* 0x140 */
u32 reg_core_set; /* 0x144 */
u32 reg_core_clr; /* 0x148 */
u32 reg_core_tog; /* 0x14c */
u32 ana_misc0; /* 0x150 */
u32 ana_misc0_set; /* 0x154 */
u32 ana_misc0_clr; /* 0x158 */
u32 ana_misc0_tog; /* 0x15c */
u32 ana_misc1; /* 0x160 */
u32 ana_misc1_set; /* 0x164 */
u32 ana_misc1_clr; /* 0x168 */
u32 ana_misc1_tog; /* 0x16c */
u32 ana_misc2; /* 0x170 */
u32 ana_misc2_set; /* 0x174 */
u32 ana_misc2_clr; /* 0x178 */
u32 ana_misc2_tog; /* 0x17c */
u32 tempsense0; /* 0x180 */
u32 tempsense0_set; /* 0x184 */
u32 tempsense0_clr; /* 0x188 */
u32 tempsense0_tog; /* 0x18c */
u32 tempsense1; /* 0x190 */
u32 tempsense1_set; /* 0x194 */
u32 tempsense1_clr; /* 0x198 */
u32 tempsense1_tog; /* 0x19c */
u32 usb1_vbus_detect; /* 0x1a0 */
u32 usb1_vbus_detect_set; /* 0x1a4 */
u32 usb1_vbus_detect_clr; /* 0x1a8 */
u32 usb1_vbus_detect_tog; /* 0x1ac */
u32 usb1_chrg_detect; /* 0x1b0 */
u32 usb1_chrg_detect_set; /* 0x1b4 */
u32 usb1_chrg_detect_clr; /* 0x1b8 */
u32 usb1_chrg_detect_tog; /* 0x1bc */
u32 usb1_vbus_det_stat; /* 0x1c0 */
u32 usb1_vbus_det_stat_set; /* 0x1c4 */
u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
u32 usb1_vbus_det_stat_tog; /* 0x1cc */
u32 usb1_chrg_det_stat; /* 0x1d0 */
u32 usb1_chrg_det_stat_set; /* 0x1d4 */
u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
u32 usb1_chrg_det_stat_tog; /* 0x1dc */
u32 usb1_loopback; /* 0x1e0 */
u32 usb1_loopback_set; /* 0x1e4 */
u32 usb1_loopback_clr; /* 0x1e8 */
u32 usb1_loopback_tog; /* 0x1ec */
u32 usb1_misc; /* 0x1f0 */
u32 usb1_misc_set; /* 0x1f4 */
u32 usb1_misc_clr; /* 0x1f8 */
u32 usb1_misc_tog; /* 0x1fc */
u32 usb2_vbus_detect; /* 0x200 */
u32 usb2_vbus_detect_set; /* 0x204 */
u32 usb2_vbus_detect_clr; /* 0x208 */
u32 usb2_vbus_detect_tog; /* 0x20c */
u32 usb2_chrg_detect; /* 0x210 */
u32 usb2_chrg_detect_set; /* 0x214 */
u32 usb2_chrg_detect_clr; /* 0x218 */
u32 usb2_chrg_detect_tog; /* 0x21c */
u32 usb2_vbus_det_stat; /* 0x220 */
u32 usb2_vbus_det_stat_set; /* 0x224 */
u32 usb2_vbus_det_stat_clr; /* 0x228 */
u32 usb2_vbus_det_stat_tog; /* 0x22c */
u32 usb2_chrg_det_stat; /* 0x230 */
u32 usb2_chrg_det_stat_set; /* 0x234 */
u32 usb2_chrg_det_stat_clr; /* 0x238 */
u32 usb2_chrg_det_stat_tog; /* 0x23c */
u32 usb2_loopback; /* 0x240 */
u32 usb2_loopback_set; /* 0x244 */
u32 usb2_loopback_clr; /* 0x248 */
u32 usb2_loopback_tog; /* 0x24c */
u32 usb2_misc; /* 0x250 */
u32 usb2_misc_set; /* 0x254 */
u32 usb2_misc_clr; /* 0x258 */
u32 usb2_misc_tog; /* 0x25c */
u32 digprog; /* 0x260 */
u32 reserved1[7];
u32 digprog_sololite; /* 0x280 */
};
#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
struct wdog_regs {
u16 wcr; /* Control */
u16 wsr; /* Service */
u16 wrsr; /* Reset Status */
u16 wicr; /* Interrupt Control */
u16 wmcr; /* Miscellaneous Control */
};
#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
#define PWMCR_DOZEEN (1 << 24)
#define PWMCR_WAITEN (1 << 23)
#define PWMCR_DBGEN (1 << 22)
#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
#define PWMCR_CLKSRC_IPG (1 << 16)
#define PWMCR_EN (1 << 0)
struct pwm_regs {
u32 cr;
u32 sr;
u32 ir;
u32 sar;
u32 pr;
u32 cnr;
};
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */

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/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_IOMUX_H__
#define __ASM_ARCH_IOMUX_H__
#define MX6_IOMUXC_GPR4 0x020e0010
#define MX6_IOMUXC_GPR6 0x020e0018
#define MX6_IOMUXC_GPR7 0x020e001c
/*
* IOMUXC_GPR1 bit fields
*/
#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13)
#define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13)
#define IOMUXC_GPR1_OTG_ID_MASK (1<<13)
#define IOMUXC_GPR1_REF_SSP_EN (1 << 16)
#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29)
/*
* IOMUXC_GPR5 bit fields
*/
#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19)
#define IOMUXC_GPR5_PCIE_PERST (1 << 18)
/*
* IOMUXC_GPR8 bit fields
*/
#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0)
#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0
#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6)
#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6
#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12)
#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12
#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18)
#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18
#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25)
#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25
/*
* IOMUXC_GPR12 bit fields
*/
#define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0)
#define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0)
#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4)
#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4)
#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10)
#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12)
#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12)
#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12)
#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30)
/*
* IOMUXC_GPR13 bit fields
*/
#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30)
#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29)
#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28)
#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27)
#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24)
#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19)
#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16
#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15)
#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14)
#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11)
#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7)
#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
| IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17)
#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13)
#define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \
| IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK)
#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18)
#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14)
#define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \
| IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19)
#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15)
#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15)
#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14)
#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14)
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11)
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11)
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11)
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11)
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11)
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2)
#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2
#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
|IOMUXC_GPR13_SATA_PHY_7_MASK \
|IOMUXC_GPR13_SATA_PHY_6_MASK \
|IOMUXC_GPR13_SATA_SPEED_MASK \
|IOMUXC_GPR13_SATA_PHY_5_MASK \
|IOMUXC_GPR13_SATA_PHY_4_MASK \
|IOMUXC_GPR13_SATA_PHY_3_MASK \
|IOMUXC_GPR13_SATA_PHY_2_MASK \
|IOMUXC_GPR13_SATA_PHY_1_MASK)
#endif /* __ASM_ARCH_IOMUX_H__ */

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/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_MX6Q
#include "mx6q-ddr.h"
#else
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#include "mx6dl-ddr.h"
#else
#ifdef CONFIG_MX6SX
#include "mx6sx-ddr.h"
#else
#ifdef CONFIG_MX6UL
#include "mx6ul-ddr.h"
#else
#ifdef CONFIG_MX6SL
#include "mx6sl-ddr.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6SL */
#endif /* CONFIG_MX6UL */
#endif /* CONFIG_MX6SX */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#else
enum {
DDR_TYPE_DDR3,
DDR_TYPE_LPDDR2,
};
/* MMDC P0/P1 Registers */
struct mmdc_p_regs {
u32 mdctl;
u32 mdpdc;
u32 mdotc;
u32 mdcfg0;
u32 mdcfg1;
u32 mdcfg2;
u32 mdmisc;
u32 mdscr;
u32 mdref;
u32 res1[2];
u32 mdrwd;
u32 mdor;
u32 mdmrr;
u32 mdcfg3lp;
u32 mdmr4;
u32 mdasp;
u32 res2[239];
u32 maarcr;
u32 mapsr;
u32 maexidr0;
u32 maexidr1;
u32 madpcr0;
u32 madpcr1;
u32 madpsr0;
u32 madpsr1;
u32 madpsr2;
u32 madpsr3;
u32 madpsr4;
u32 madpsr5;
u32 masbs0;
u32 masbs1;
u32 res3[2];
u32 magenp;
u32 res4[239];
u32 mpzqhwctrl;
u32 mpzqswctrl;
u32 mpwlgcr;
u32 mpwldectrl0;
u32 mpwldectrl1;
u32 mpwldlst;
u32 mpodtctrl;
u32 mprddqby0dl;
u32 mprddqby1dl;
u32 mprddqby2dl;
u32 mprddqby3dl;
u32 mpwrdqby0dl;
u32 mpwrdqby1dl;
u32 mpwrdqby2dl;
u32 mpwrdqby3dl;
u32 mpdgctrl0;
u32 mpdgctrl1;
u32 mpdgdlst0;
u32 mprddlctl;
u32 mprddlst;
u32 mpwrdlctl;
u32 mpwrdlst;
u32 mpsdctrl;
u32 mpzqlp2ctl;
u32 mprddlhwctl;
u32 mpwrdlhwctl;
u32 mprddlhwst0;
u32 mprddlhwst1;
u32 mpwrdlhwst0;
u32 mpwrdlhwst1;
u32 mpwlhwerr;
u32 mpdghwst0;
u32 mpdghwst1;
u32 mpdghwst2;
u32 mpdghwst3;
u32 mppdcmpr1;
u32 mppdcmpr2;
u32 mpswdar0;
u32 mpswdrdr0;
u32 mpswdrdr1;
u32 mpswdrdr2;
u32 mpswdrdr3;
u32 mpswdrdr4;
u32 mpswdrdr5;
u32 mpswdrdr6;
u32 mpswdrdr7;
u32 mpmur0;
u32 mpwrcadl;
u32 mpdccr;
};
#define MX6SL_IOM_DDR_BASE 0x020e0300
struct mx6sl_iomux_ddr_regs {
u32 dram_cas;
u32 dram_cs0_b;
u32 dram_cs1_b;
u32 dram_dqm0;
u32 dram_dqm1;
u32 dram_dqm2;
u32 dram_dqm3;
u32 dram_ras;
u32 dram_reset;
u32 dram_sdba0;
u32 dram_sdba1;
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdcke1;
u32 dram_sdclk_0;
u32 dram_odt0;
u32 dram_odt1;
u32 dram_sdqs0;
u32 dram_sdqs1;
u32 dram_sdqs2;
u32 dram_sdqs3;
u32 dram_sdwe_b;
};
#define MX6SL_IOM_GRP_BASE 0x020e0500
struct mx6sl_iomux_grp_regs {
u32 res1[43];
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 grp_ddrpke;
u32 grp_ddrpk;
u32 grp_ddrhys;
u32 grp_ddrmode;
u32 grp_b0ds;
u32 grp_ctlds;
u32 grp_b1ds;
u32 grp_ddr_type;
u32 grp_b2ds;
u32 grp_b3ds;
};
#define MX6UL_IOM_DDR_BASE 0x020e0200
struct mx6ul_iomux_ddr_regs {
u32 res1[17];
u32 dram_dqm0;
u32 dram_dqm1;
u32 dram_ras;
u32 dram_cas;
u32 dram_cs0;
u32 dram_cs1;
u32 dram_sdwe_b;
u32 dram_odt0;
u32 dram_odt1;
u32 dram_sdba0;
u32 dram_sdba1;
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdcke1;
u32 dram_sdclk_0;
u32 dram_sdqs0;
u32 dram_sdqs1;
u32 dram_reset;
};
#define MX6UL_IOM_GRP_BASE 0x020e0400
struct mx6ul_iomux_grp_regs {
u32 res1[36];
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 grp_b0ds;
u32 grp_ddrpk;
u32 grp_ctlds;
u32 grp_b1ds;
u32 grp_ddrhys;
u32 grp_ddrpke;
u32 grp_ddrmode;
u32 grp_ddr_type;
};
#define MX6SX_IOM_DDR_BASE 0x020e0200
struct mx6sx_iomux_ddr_regs {
u32 res1[59];
u32 dram_dqm0;
u32 dram_dqm1;
u32 dram_dqm2;
u32 dram_dqm3;
u32 dram_ras;
u32 dram_cas;
u32 res2[2];
u32 dram_sdwe_b;
u32 dram_odt0;
u32 dram_odt1;
u32 dram_sdba0;
u32 dram_sdba1;
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdcke1;
u32 dram_sdclk_0;
u32 dram_sdqs0;
u32 dram_sdqs1;
u32 dram_sdqs2;
u32 dram_sdqs3;
u32 dram_reset;
};
#define MX6SX_IOM_GRP_BASE 0x020e0500
struct mx6sx_iomux_grp_regs {
u32 res1[61];
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 grp_ddrpke;
u32 grp_ddrpk;
u32 grp_ddrhys;
u32 grp_ddrmode;
u32 grp_b0ds;
u32 grp_b1ds;
u32 grp_ctlds;
u32 grp_ddr_type;
u32 grp_b2ds;
u32 grp_b3ds;
};
/*
* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
*/
#define MX6DQ_IOM_DDR_BASE 0x020e0500
struct mx6dq_iomux_ddr_regs {
u32 res1[3];
u32 dram_sdqs5;
u32 dram_dqm5;
u32 dram_dqm4;
u32 dram_sdqs4;
u32 dram_sdqs3;
u32 dram_dqm3;
u32 dram_sdqs2;
u32 dram_dqm2;
u32 res2[16];
u32 dram_cas;
u32 res3[2];
u32 dram_ras;
u32 dram_reset;
u32 res4[2];
u32 dram_sdclk_0;
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdclk_1;
u32 dram_sdcke1;
u32 dram_sdodt0;
u32 dram_sdodt1;
u32 res5;
u32 dram_sdqs0;
u32 dram_dqm0;
u32 dram_sdqs1;
u32 dram_dqm1;
u32 dram_sdqs6;
u32 dram_dqm6;
u32 dram_sdqs7;
u32 dram_dqm7;
};
#define MX6DQ_IOM_GRP_BASE 0x020e0700
struct mx6dq_iomux_grp_regs {
u32 res1[18];
u32 grp_b7ds;
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 res2;
u32 grp_ddrpke;
u32 res3[6];
u32 grp_ddrmode;
u32 res4[3];
u32 grp_b0ds;
u32 grp_b1ds;
u32 grp_ctlds;
u32 res5;
u32 grp_b2ds;
u32 grp_ddr_type;
u32 grp_b3ds;
u32 grp_b4ds;
u32 grp_b5ds;
u32 grp_b6ds;
};
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];
u32 dram_cas;
u32 res2[2];
u32 dram_dqm0;
u32 dram_dqm1;
u32 dram_dqm2;
u32 dram_dqm3;
u32 dram_dqm4;
u32 dram_dqm5;
u32 dram_dqm6;
u32 dram_dqm7;
u32 dram_ras;
u32 dram_reset;
u32 res3[2];
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdcke1;
u32 dram_sdclk_0;
u32 dram_sdclk_1;
u32 dram_sdodt0;
u32 dram_sdodt1;
u32 dram_sdqs0;
u32 dram_sdqs1;
u32 dram_sdqs2;
u32 dram_sdqs3;
u32 dram_sdqs4;
u32 dram_sdqs5;
u32 dram_sdqs6;
u32 dram_sdqs7;
};
#define MX6SDL_IOM_GRP_BASE 0x020e0700
struct mx6sdl_iomux_grp_regs {
u32 res1[18];
u32 grp_b7ds;
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 grp_ddrpke;
u32 res2[2];
u32 grp_ddrmode;
u32 grp_b0ds;
u32 res3;
u32 grp_ctlds;
u32 grp_b1ds;
u32 grp_ddr_type;
u32 grp_b2ds;
u32 grp_b3ds;
u32 grp_b4ds;
u32 grp_b5ds;
u32 res4;
u32 grp_b6ds;
};
/* Device Information: Varies per DDR3 part number and speed grade */
struct mx6_ddr3_cfg {
u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
u8 density; /* chip density (Gb) (1,2,4,8) */
u8 width; /* bus width (bits) (4,8,16) */
u8 banks; /* number of banks */
u8 rowaddr; /* row address bits (11-16)*/
u8 coladdr; /* col address bits (9-12) */
u8 pagesz; /* page size (K) (1-2) */
u16 trcd; /* tRCD=tRP=CL (ns*100) */
u16 trcmin; /* tRC min (ns*100) */
u16 trasmin; /* tRAS min (ns*100) */
u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
};
/* Device Information: Varies per LPDDR2 part number and speed grade */
struct mx6_lpddr2_cfg {
u16 mem_speed; /* ie 800 for LPDDR2-800 */
u8 density; /* chip density (Gb) (1,2,4,8) */
u8 width; /* bus width (bits) (4,8,16) */
u8 banks; /* number of banks */
u8 rowaddr; /* row address bits (11-16)*/
u8 coladdr; /* col address bits (9-12) */
u16 trcd_lp;
u16 trppb_lp;
u16 trpab_lp;
u16 trcmin; /* tRC min (ns*100) */
u16 trasmin; /* tRAS min (ns*100) */
};
/* System Information: Varies per board design, layout, and term choices */
struct mx6_ddr_sysinfo {
u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
u8 cs_density; /* density per chip select (Gb) */
u8 ncs; /* number chip selects used (1|2) */
char cs1_mirror;/* enable address mirror (0|1) */
char bi_on; /* Bank interleaving enable */
u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
u8 ralat; /* Read Additional Latency (0-7) */
u8 walat; /* Write Additional Latency (0-3) */
u8 mif3_mode; /* Command prediction working mode */
u8 rst_to_cke; /* Time from SDE enable to CKE rise */
u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
};
/*
* Board specific calibration:
* This includes write leveling calibration values as well as DQS gating
* and read/write delays. These values are board/layout/device specific.
* Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
* (DOC-96412) to determine these values over a range of boards and
* temperatures.
*/
struct mx6_mmdc_calibration {
/* write leveling calibration */
u32 p0_mpwldectrl0;
u32 p0_mpwldectrl1;
u32 p1_mpwldectrl0;
u32 p1_mpwldectrl1;
/* read DQS gating */
u32 p0_mpdgctrl0;
u32 p0_mpdgctrl1;
u32 p1_mpdgctrl0;
u32 p1_mpdgctrl1;
/* read delay */
u32 p0_mprddlctl;
u32 p1_mprddlctl;
/* write delay */
u32 p0_mpwrdlctl;
u32 p1_mpwrdlctl;
/* lpddr2 zq hw calibration */
u32 mpzqlp2ctl;
};
/* configure iomux (pinctl/padctl) */
void mx6dq_dram_iocfg(unsigned width,
const struct mx6dq_iomux_ddr_regs *,
const struct mx6dq_iomux_grp_regs *);
void mx6sdl_dram_iocfg(unsigned width,
const struct mx6sdl_iomux_ddr_regs *,
const struct mx6sdl_iomux_grp_regs *);
void mx6sx_dram_iocfg(unsigned width,
const struct mx6sx_iomux_ddr_regs *,
const struct mx6sx_iomux_grp_regs *);
void mx6ul_dram_iocfg(unsigned width,
const struct mx6ul_iomux_ddr_regs *,
const struct mx6ul_iomux_grp_regs *);
void mx6sl_dram_iocfg(unsigned width,
const struct mx6sl_iomux_ddr_regs *,
const struct mx6sl_iomux_grp_regs *);
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
int mmdc_do_write_level_calibration(void);
int mmdc_do_dqs_calibration(void);
#endif
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
const struct mx6_mmdc_calibration *,
const void *);
#endif /* CONFIG_SPL_BUILD */
#define MX6_MMDC_P0_MDCTL 0x021b0000
#define MX6_MMDC_P0_MDPDC 0x021b0004
#define MX6_MMDC_P0_MDOTC 0x021b0008
#define MX6_MMDC_P0_MDCFG0 0x021b000c
#define MX6_MMDC_P0_MDCFG1 0x021b0010
#define MX6_MMDC_P0_MDCFG2 0x021b0014
#define MX6_MMDC_P0_MDMISC 0x021b0018
#define MX6_MMDC_P0_MDSCR 0x021b001c
#define MX6_MMDC_P0_MDREF 0x021b0020
#define MX6_MMDC_P0_MDRWD 0x021b002c
#define MX6_MMDC_P0_MDOR 0x021b0030
#define MX6_MMDC_P0_MDASP 0x021b0040
#define MX6_MMDC_P0_MAPSR 0x021b0404
#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
#define MX6_MMDC_P0_MPMUR0 0x021b08b8
#define MX6_MMDC_P1_MDCTL 0x021b4000
#define MX6_MMDC_P1_MDPDC 0x021b4004
#define MX6_MMDC_P1_MDOTC 0x021b4008
#define MX6_MMDC_P1_MDCFG0 0x021b400c
#define MX6_MMDC_P1_MDCFG1 0x021b4010
#define MX6_MMDC_P1_MDCFG2 0x021b4014
#define MX6_MMDC_P1_MDMISC 0x021b4018
#define MX6_MMDC_P1_MDSCR 0x021b401c
#define MX6_MMDC_P1_MDREF 0x021b4020
#define MX6_MMDC_P1_MDRWD 0x021b402c
#define MX6_MMDC_P1_MDOR 0x021b4030
#define MX6_MMDC_P1_MDASP 0x021b4040
#define MX6_MMDC_P1_MAPSR 0x021b4404
#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
#define MX6_MMDC_P1_MPMUR0 0x021b48b8
#endif /*__ASM_ARCH_MX6_DDR_H__ */

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/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6_PINS_H__
#define __ASM_ARCH_MX6_PINS_H__
#include <asm/imx-common/iomux-v3.h>
#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
#ifdef CONFIG_MX6QDL
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6q_pins.h"
#undef MX6_PAD_DECL
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6dl_pins.h"
};
#elif defined(CONFIG_MX6Q)
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6q_pins.h"
};
#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6dl_pins.h"
};
#elif defined(CONFIG_MX6SL)
#include "mx6sl_pins.h"
#elif defined(CONFIG_MX6SX)
#include "mx6sx_pins.h"
#elif defined(CONFIG_MX6UL)
#include "mx6ul_pins.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6Q */
#endif /*__ASM_ARCH_MX6_PINS_H__ */

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/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6DLS_DDR_H__
#define __ASM_ARCH_MX6DLS_DDR_H__
#ifndef CONFIG_MX6DL
#ifndef CONFIG_MX6S
#error "wrong CPU"
#endif
#endif
#define MX6_IOM_DRAM_DQM0 0x020e0470
#define MX6_IOM_DRAM_DQM1 0x020e0474
#define MX6_IOM_DRAM_DQM2 0x020e0478
#define MX6_IOM_DRAM_DQM3 0x020e047c
#define MX6_IOM_DRAM_DQM4 0x020e0480
#define MX6_IOM_DRAM_DQM5 0x020e0484
#define MX6_IOM_DRAM_DQM6 0x020e0488
#define MX6_IOM_DRAM_DQM7 0x020e048c
#define MX6_IOM_DRAM_CAS 0x020e0464
#define MX6_IOM_DRAM_RAS 0x020e0490
#define MX6_IOM_DRAM_RESET 0x020e0494
#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
#define MX6_IOM_DRAM_SDBA2 0x020e04a0
#define MX6_IOM_DRAM_SDCKE0 0x020e04a4
#define MX6_IOM_DRAM_SDCKE1 0x020e04a8
#define MX6_IOM_DRAM_SDODT0 0x020e04b4
#define MX6_IOM_DRAM_SDODT1 0x020e04b8
#define MX6_IOM_DRAM_SDQS0 0x020e04bc
#define MX6_IOM_DRAM_SDQS1 0x020e04c0
#define MX6_IOM_DRAM_SDQS2 0x020e04c4
#define MX6_IOM_DRAM_SDQS3 0x020e04c8
#define MX6_IOM_DRAM_SDQS4 0x020e04cc
#define MX6_IOM_DRAM_SDQS5 0x020e04d0
#define MX6_IOM_DRAM_SDQS6 0x020e04d4
#define MX6_IOM_DRAM_SDQS7 0x020e04d8
#define MX6_IOM_GRP_B0DS 0x020e0764
#define MX6_IOM_GRP_B1DS 0x020e0770
#define MX6_IOM_GRP_B2DS 0x020e0778
#define MX6_IOM_GRP_B3DS 0x020e077c
#define MX6_IOM_GRP_B4DS 0x020e0780
#define MX6_IOM_GRP_B5DS 0x020e0784
#define MX6_IOM_GRP_B6DS 0x020e078c
#define MX6_IOM_GRP_B7DS 0x020e0748
#define MX6_IOM_GRP_ADDDS 0x020e074c
#define MX6_IOM_DDRMODE_CTL 0x020e0750
#define MX6_IOM_GRP_DDRPKE 0x020e0754
#define MX6_IOM_GRP_DDRMODE 0x020e0760
#define MX6_IOM_GRP_CTLDS 0x020e076c
#define MX6_IOM_GRP_DDR_TYPE 0x020e0774
#endif /*__ASM_ARCH_MX6S_DDR_H__ */

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/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6Q_DDR_H__
#define __ASM_ARCH_MX6Q_DDR_H__
#ifndef CONFIG_MX6Q
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_DQM0 0x020e05ac
#define MX6_IOM_DRAM_DQM1 0x020e05b4
#define MX6_IOM_DRAM_DQM2 0x020e0528
#define MX6_IOM_DRAM_DQM3 0x020e0520
#define MX6_IOM_DRAM_DQM4 0x020e0514
#define MX6_IOM_DRAM_DQM5 0x020e0510
#define MX6_IOM_DRAM_DQM6 0x020e05bc
#define MX6_IOM_DRAM_DQM7 0x020e05c4
#define MX6_IOM_DRAM_CAS 0x020e056c
#define MX6_IOM_DRAM_RAS 0x020e0578
#define MX6_IOM_DRAM_RESET 0x020e057c
#define MX6_IOM_DRAM_SDCLK_0 0x020e0588
#define MX6_IOM_DRAM_SDCLK_1 0x020e0594
#define MX6_IOM_DRAM_SDBA2 0x020e058c
#define MX6_IOM_DRAM_SDCKE0 0x020e0590
#define MX6_IOM_DRAM_SDCKE1 0x020e0598
#define MX6_IOM_DRAM_SDODT0 0x020e059c
#define MX6_IOM_DRAM_SDODT1 0x020e05a0
#define MX6_IOM_DRAM_SDQS0 0x020e05a8
#define MX6_IOM_DRAM_SDQS1 0x020e05b0
#define MX6_IOM_DRAM_SDQS2 0x020e0524
#define MX6_IOM_DRAM_SDQS3 0x020e051c
#define MX6_IOM_DRAM_SDQS4 0x020e0518
#define MX6_IOM_DRAM_SDQS5 0x020e050c
#define MX6_IOM_DRAM_SDQS6 0x020e05b8
#define MX6_IOM_DRAM_SDQS7 0x020e05c0
#define MX6_IOM_GRP_B0DS 0x020e0784
#define MX6_IOM_GRP_B1DS 0x020e0788
#define MX6_IOM_GRP_B2DS 0x020e0794
#define MX6_IOM_GRP_B3DS 0x020e079c
#define MX6_IOM_GRP_B4DS 0x020e07a0
#define MX6_IOM_GRP_B5DS 0x020e07a4
#define MX6_IOM_GRP_B6DS 0x020e07a8
#define MX6_IOM_GRP_B7DS 0x020e0748
#define MX6_IOM_GRP_ADDDS 0x020e074c
#define MX6_IOM_DDRMODE_CTL 0x020e0750
#define MX6_IOM_GRP_DDRPKE 0x020e0758
#define MX6_IOM_GRP_DDRMODE 0x020e0774
#define MX6_IOM_GRP_CTLDS 0x020e078c
#define MX6_IOM_GRP_DDR_TYPE 0x020e0798
#endif /*__ASM_ARCH_MX6Q_DDR_H__ */

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/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6SL_DDR_H__
#define __ASM_ARCH_MX6SL_DDR_H__
#ifndef CONFIG_MX6SL
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_CAS_B 0x020e0300
#define MX6_IOM_DRAM_CS0_B 0x020e0304
#define MX6_IOM_DRAM_CS1_B 0x020e0308
#define MX6_IOM_DRAM_DQM0 0x020e030c
#define MX6_IOM_DRAM_DQM1 0x020e0310
#define MX6_IOM_DRAM_DQM2 0x020e0314
#define MX6_IOM_DRAM_DQM3 0x020e0318
#define MX6_IOM_DRAM_RAS_B 0x020e031c
#define MX6_IOM_DRAM_RESET 0x020e0320
#define MX6_IOM_DRAM_SDBA0 0x020e0324
#define MX6_IOM_DRAM_SDBA1 0x020e0328
#define MX6_IOM_DRAM_SDBA2 0x020e032c
#define MX6_IOM_DRAM_SDCKE0 0x020e0330
#define MX6_IOM_DRAM_SDCKE1 0x020e0334
#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338
#define MX6_IOM_DRAM_ODT0 0x020e033c
#define MX6_IOM_DRAM_ODT1 0x020e0340
#define MX6_IOM_DRAM_SDQS0_P 0x020e0344
#define MX6_IOM_DRAM_SDQS1_P 0x020e0348
#define MX6_IOM_DRAM_SDQS2_P 0x020e034c
#define MX6_IOM_DRAM_SDQS3_P 0x020e0350
#define MX6_IOM_DRAM_SDWE_B 0x020e0354
#endif /*__ASM_ARCH_MX6SL_DDR_H__ */

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/*
* Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
#define __ASM_ARCH_MX6_MX6SL_PINS_H__
#include <asm/imx-common/iomux-v3.h>
enum {
MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0),
MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT5__GPIO_5_9 = IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0),
MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0),
MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0),
MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0),
MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0),
MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0),
MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0),
MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0),
MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0),
MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0),
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */

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/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6SX_DDR_H__
#define __ASM_ARCH_MX6SX_DDR_H__
#ifndef CONFIG_MX6SX
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_DQM0 0x020e02ec
#define MX6_IOM_DRAM_DQM1 0x020e02f0
#define MX6_IOM_DRAM_DQM2 0x020e02f4
#define MX6_IOM_DRAM_DQM3 0x020e02f8
#define MX6_IOM_DRAM_RAS 0x020e02fc
#define MX6_IOM_DRAM_CAS 0x020e0300
#define MX6_IOM_DRAM_SDODT0 0x020e0310
#define MX6_IOM_DRAM_SDODT1 0x020e0314
#define MX6_IOM_DRAM_SDBA2 0x020e0320
#define MX6_IOM_DRAM_SDCKE0 0x020e0324
#define MX6_IOM_DRAM_SDCKE1 0x020e0328
#define MX6_IOM_DRAM_SDCLK_0 0x020e032c
#define MX6_IOM_DRAM_RESET 0x020e0340
#define MX6_IOM_DRAM_SDQS0 0x020e0330
#define MX6_IOM_DRAM_SDQS1 0x020e0334
#define MX6_IOM_DRAM_SDQS2 0x020e0338
#define MX6_IOM_DRAM_SDQS3 0x020e033c
#define MX6_IOM_GRP_ADDDS 0x020e05f4
#define MX6_IOM_DDRMODE_CTL 0x020e05f8
#define MX6_IOM_GRP_DDRPKE 0x020e05fc
#define MX6_IOM_GRP_DDRMODE 0x020e0608
#define MX6_IOM_GRP_B0DS 0x020e060c
#define MX6_IOM_GRP_B1DS 0x020e0610
#define MX6_IOM_GRP_CTLDS 0x020e0614
#define MX6_IOM_GRP_DDR_TYPE 0x020e0618
#define MX6_IOM_GRP_B2DS 0x020e061c
#define MX6_IOM_GRP_B3DS 0x020e0620
#endif /*__ASM_ARCH_MX6SX_DDR_H__ */

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/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX6SX_RDC_H__
#define __MX6SX_RDC_H__
#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */
enum {
RDC_PER_PWM1 = 0,
RDC_PER_PWM2,
RDC_PER_PWM3,
RDC_PER_PWM4,
RDC_PER_CAN1,
RDC_PER_CAN2,
RDC_PER_GPT,
RDC_PER_GPIO1,
RDC_PER_GPIO2,
RDC_PER_GPIO3,
RDC_PER_GPIO4,
RDC_PER_GPIO5,
RDC_PER_GPIO6,
RDC_PER_GPIO7,
RDC_PER_KPP,
RDC_PER_WDOG1,
RDC_PER_WODG2,
RDC_PER_CCM,
RDC_PER_ANATOPDIG,
RDC_PER_SNVSHP,
RDC_PER_EPIT1,
RDC_PER_EPIT2,
RDC_PER_SRC,
RDC_PER_GPC,
RDC_PER_IOMUXC,
RDC_PER_IOMUXCGPR,
RDC_PER_CANFD1,
RDC_PER_SDMA,
RDC_PER_CANFD2,
RDC_PER_SEMA1,
RDC_PER_SEMA2,
RDC_PER_RDC,
RDC_PER_AIPSTZ1_GE1,
RDC_PER_AIPSTZ2_GE2,
RDC_PER_USBO2H_PL301,
RDC_PER_USBO2H_USB,
RDC_PER_ENET1,
RDC_PER_MLB25,
RDC_PER_USDHC1,
RDC_PER_USDHC2,
RDC_PER_USDHC3,
RDC_PER_USDHC4,
RDC_PER_I2C1,
RDC_PER_I2C2,
RDC_PER_I2C3,
RDC_PER_ROMCP,
RDC_PER_MMDC,
RDC_PER_ENET2,
RDC_PER_EIM,
RDC_PER_OCOTP,
RDC_PER_CSU,
RDC_PER_PERFMON1,
RDC_PER_PERFMON2,
RDC_PER_AXIMON,
RDC_PER_TZASC1,
RDC_PER_SAI1,
RDC_PER_AUDMUX,
RDC_PER_SAI2,
RDC_PER_QSPI1,
RDC_PER_QSPI2,
RDC_PER_UART2,
RDC_PER_UART3,
RDC_PER_UART4,
RDC_PER_UART5,
RDC_PER_I2C4,
RDC_PER_QOSC,
RDC_PER_CAAM,
RDC_PER_DAP,
RDC_PER_ADC1,
RDC_PER_ADC2,
RDC_PER_WDOG3,
RDC_PER_ECSPI5,
RDC_PER_SEMA4,
RDC_PER_MUPORT1,
RDC_PER_CANFD_CPU,
RDC_PER_MUPORT2,
RDC_PER_UART6,
RDC_PER_PWM5,
RDC_PER_PWM6,
RDC_PER_PWM7,
RDC_PER_PWM8,
RDC_PER_AIPSTZ3_GE0,
RDC_PER_AIPSTZ3_GE1,
RDC_PER_RESERVED1,
RDC_PER_SPDIF,
RDC_PER_ECSPI1,
RDC_PER_ECSPI2,
RDC_PER_ECSPI3,
RDC_PER_ECSPI4,
RDC_PER_RESERVED2,
RDC_PER_RESERVED3,
RDC_PER_UART1,
RDC_PER_ESAI,
RDC_PER_SSI1,
RDC_PER_SSI2,
RDC_PER_SSI3,
RDC_PER_ASRC,
RDC_PER_RESERVED4,
RDC_PER_SPBA_MA,
RDC_PER_GIS,
RDC_PER_DCIC1,
RDC_PER_DCIC2,
RDC_PER_CSI1,
RDC_PER_PXP,
RDC_PER_CSI2,
RDC_PER_LCDIF1,
RDC_PER_LCDIF2,
RDC_PER_VADC,
RDC_PER_VDEC,
RDC_PER_SPBA_DISPLAYMIX,
};
enum {
RDC_MA_A9_L2CACHE = 0,
RDC_MA_M4,
RDC_MA_GPU,
RDC_MA_CSI1,
RDC_MA_CSI2,
RDC_MA_LCDIF1,
RDC_MA_LCDIF2,
RDC_MA_PXP,
RDC_MA_PCIE_CTRL,
RDC_MA_DAP,
RDC_MA_CAAM,
RDC_MA_SDMA_PERI,
RDC_MA_SDMA_BURST,
RDC_MA_APBHDMA,
RDC_MA_RAWNAND,
RDC_MA_USDHC1,
RDC_MA_USDHC2,
RDC_MA_USDHC3,
RDC_MA_USDHC4,
RDC_MA_USB,
RDC_MA_MLB,
RDC_MA_TEST,
RDC_MA_ENET1_TX,
RDC_MA_ENET1_RX,
RDC_MA_ENET2_TX,
RDC_MA_ENET2_RX,
RDC_MA_SDMA,
};
#endif /* __MX6SX_RDC_H__*/

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/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6UL_DDR_H__
#define __ASM_ARCH_MX6UL_DDR_H__
#ifndef CONFIG_MX6UL
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_DQM0 0x020e0244
#define MX6_IOM_DRAM_DQM1 0x020e0248
#define MX6_IOM_DRAM_RAS 0x020e024c
#define MX6_IOM_DRAM_CAS 0x020e0250
#define MX6_IOM_DRAM_CS0 0x020e0254
#define MX6_IOM_DRAM_CS1 0x020e0258
#define MX6_IOM_DRAM_SDWE_B 0x020e025c
#define MX6_IOM_DRAM_SDODT0 0x020e0260
#define MX6_IOM_DRAM_SDODT1 0x020e0264
#define MX6_IOM_DRAM_SDBA0 0x020e0268
#define MX6_IOM_DRAM_SDBA1 0x020e026c
#define MX6_IOM_DRAM_SDBA2 0x020e0270
#define MX6_IOM_DRAM_SDCKE0 0x020e0274
#define MX6_IOM_DRAM_SDCKE1 0x020e0278
#define MX6_IOM_DRAM_SDCLK_0 0x020e027c
#define MX6_IOM_DRAM_SDQS0 0x020e0280
#define MX6_IOM_DRAM_SDQS1 0x020e0284
#define MX6_IOM_DRAM_RESET 0x020e0288
#define MX6_IOM_GRP_ADDDS 0x020e0490
#define MX6_IOM_DDRMODE_CTL 0x020e0494
#define MX6_IOM_GRP_B0DS 0x020e0498
#define MX6_IOM_GRP_DDRPK 0x020e049c
#define MX6_IOM_GRP_CTLDS 0x020e04a0
#define MX6_IOM_GRP_B1DS 0x020e04a4
#define MX6_IOM_GRP_DDRHYS 0x020e04a8
#define MX6_IOM_GRP_DDRPKE 0x020e04ac
#define MX6_IOM_GRP_DDRMODE 0x020e04b0
#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4
#endif /*__ASM_ARCH_MX6SX_DDR_H__ */

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/*
* (C) Copyright 2009
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/imx-common/sys_proto.h>