avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
43
u-boot/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
Normal file
43
u-boot/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
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@@ -0,0 +1,43 @@
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/*
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* clk-synthesizer.h
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*
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* Clock synthesizer header
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*
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* Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CLK_SYNTHESIZER_H
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#define __CLK_SYNTHESIZER_H
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#include <common.h>
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#define CLK_SYNTHESIZER_ID_REG 0x0
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#define CLK_SYNTHESIZER_XCSEL 0x05
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#define CLK_SYNTHESIZER_MUX_REG 0x14
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#define CLK_SYNTHESIZER_PDIV2_REG 0x16
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#define CLK_SYNTHESIZER_PDIV3_REG 0x17
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#define CLK_SYNTHESIZER_BYTE_MODE 0x80
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/**
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* struct clk_synth: This structure holds data neeed for configuring
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* for clock synthesizer.
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* @id: The id of synthesizer
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* @capacitor: value of the capacitor attached
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* @mux: mux settings.
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* @pdiv2: Div to be applied to second output
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* @pdiv3: Div to be applied to third output
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*/
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struct clk_synth {
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u32 id;
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u32 capacitor;
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u32 mux;
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u32 pdiv2;
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u32 pdiv3;
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};
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int setup_clock_synthesizer(struct clk_synth *data);
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#endif
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121
u-boot/arch/arm/include/asm/arch-am33xx/clock.h
Normal file
121
u-boot/arch/arm/include/asm/arch-am33xx/clock.h
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@@ -0,0 +1,121 @@
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/*
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* clock.h
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*
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* clock header
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*
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* Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCKS_H_
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#define _CLOCKS_H_
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#include <asm/arch/clocks_am33xx.h>
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#ifdef CONFIG_TI81XX
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#include <asm/arch/clock_ti81xx.h>
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#endif
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#define LDELAY 1000000
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/*CM_<clock_domain>__CLKCTRL */
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#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
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#define CD_CLKCTRL_CLKTRCTRL_MASK 3
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#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
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#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
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#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
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/* CM_<clock_domain>_<module>_CLKCTRL */
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#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
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#define MODULE_CLKCTRL_MODULEMODE_MASK 3
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#define MODULE_CLKCTRL_IDLEST_SHIFT 16
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#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
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#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
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#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
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#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
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#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
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#define MODULE_CLKCTRL_IDLEST_IDLE 2
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#define MODULE_CLKCTRL_IDLEST_DISABLED 3
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
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#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
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#define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13)
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#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
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#define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15)
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#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
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#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
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#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
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#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
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#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
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#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_LOCK 7
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/* CM_IDLEST_DPLL fields */
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#define ST_DPLL_CLK_MASK 1
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/* CM_CLKSEL_DPLL */
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#define CM_CLKSEL_DPLL_M_SHIFT 8
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#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
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#define CM_CLKSEL_DPLL_N_SHIFT 0
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#define CM_CLKSEL_DPLL_N_MASK 0x7F
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struct dpll_params {
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u32 m;
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u32 n;
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s8 m2;
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s8 m3;
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s8 m4;
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s8 m5;
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s8 m6;
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};
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struct dpll_regs {
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u32 cm_clkmode_dpll;
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u32 cm_idlest_dpll;
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u32 cm_autoidle_dpll;
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u32 cm_clksel_dpll;
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u32 cm_div_m2_dpll;
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u32 cm_div_m3_dpll;
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u32 cm_div_m4_dpll;
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u32 cm_div_m5_dpll;
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u32 cm_div_m6_dpll;
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};
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extern const struct dpll_regs dpll_mpu_regs;
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extern const struct dpll_regs dpll_core_regs;
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extern const struct dpll_regs dpll_per_regs;
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extern const struct dpll_regs dpll_ddr_regs;
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extern struct cm_wkuppll *const cmwkup;
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const struct dpll_params *get_dpll_mpu_params(void);
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const struct dpll_params *get_dpll_core_params(void);
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const struct dpll_params *get_dpll_per_params(void);
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const struct dpll_params *get_dpll_ddr_params(void);
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void scale_vcores(void);
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void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
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void prcm_init(void);
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void enable_basic_clocks(void);
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void do_enable_clocks(u32 *const *, u32 *const *, u8);
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void do_disable_clocks(u32 *const *, u32 *const *, u8);
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void set_mpu_spreadspectrum(int permille);
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#endif
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142
u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
Normal file
142
u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
Normal file
@@ -0,0 +1,142 @@
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||||
/*
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* ti81xx.h
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||||
*
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Antoine Tenart, <atenart@adeneo-embedded.com>
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*
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||||
* This file is released under the terms of GPL v2 and any later version.
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* See the file COPYING in the root directory of the source tree for details.
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*/
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#ifndef _CLOCK_TI81XX_H_
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#define _CLOCK_TI81XX_H_
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#define PRCM_MOD_EN 0x2
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#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
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#define CM_ALWON_BASE (PRCM_BASE + 0x1400)
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struct cm_def {
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unsigned int resv0[2];
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unsigned int l3fastclkstctrl;
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unsigned int resv1[1];
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unsigned int pciclkstctrl;
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unsigned int resv2[1];
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unsigned int ducaticlkstctrl;
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unsigned int resv3[1];
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unsigned int emif0clkctrl;
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unsigned int emif1clkctrl;
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unsigned int dmmclkctrl;
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unsigned int fwclkctrl;
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unsigned int resv4[10];
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unsigned int usbclkctrl;
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unsigned int resv5[1];
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unsigned int sataclkctrl;
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unsigned int resv6[4];
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unsigned int ducaticlkctrl;
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unsigned int pciclkctrl;
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};
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struct cm_alwon {
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unsigned int l3slowclkstctrl;
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unsigned int ethclkstctrl;
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unsigned int l3medclkstctrl;
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unsigned int mmu_clkstctrl;
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unsigned int mmucfg_clkstctrl;
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unsigned int ocmc0clkstctrl;
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#if defined(CONFIG_TI814X)
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unsigned int vcpclkstctrl;
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#elif defined(CONFIG_TI816X)
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unsigned int ocmc1clkstctrl;
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#endif
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unsigned int mpuclkstctrl;
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unsigned int sysclk4clkstctrl;
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unsigned int sysclk5clkstctrl;
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unsigned int sysclk6clkstctrl;
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unsigned int rtcclkstctrl;
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unsigned int l3fastclkstctrl;
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unsigned int resv0[67];
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unsigned int mcasp0clkctrl;
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unsigned int mcasp1clkctrl;
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unsigned int mcasp2clkctrl;
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unsigned int mcbspclkctrl;
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unsigned int uart0clkctrl;
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unsigned int uart1clkctrl;
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unsigned int uart2clkctrl;
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unsigned int gpio0clkctrl;
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unsigned int gpio1clkctrl;
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unsigned int i2c0clkctrl;
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unsigned int i2c1clkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int mcasp345clkctrl;
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unsigned int atlclkctrl;
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unsigned int mlbclkctrl;
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unsigned int pataclkctrl;
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unsigned int resv1[1];
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unsigned int uart3clkctrl;
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unsigned int uart4clkctrl;
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unsigned int uart5clkctrl;
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#elif defined(CONFIG_TI816X)
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||||
unsigned int resv1[1];
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unsigned int timer1clkctrl;
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unsigned int timer2clkctrl;
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unsigned int timer3clkctrl;
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unsigned int timer4clkctrl;
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unsigned int timer5clkctrl;
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unsigned int timer6clkctrl;
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unsigned int timer7clkctrl;
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#endif
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unsigned int wdtimerclkctrl;
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unsigned int spiclkctrl;
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||||
unsigned int mailboxclkctrl;
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unsigned int spinboxclkctrl;
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unsigned int mmudataclkctrl;
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unsigned int resv2[2];
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unsigned int mmucfgclkctrl;
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||||
#if defined(CONFIG_TI814X)
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||||
unsigned int resv3[2];
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||||
#elif defined(CONFIG_TI816X)
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||||
unsigned int resv3[1];
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unsigned int sdioclkctrl;
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||||
#endif
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||||
unsigned int ocmc0clkctrl;
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||||
#if defined(CONFIG_TI814X)
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||||
unsigned int vcpclkctrl;
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||||
#elif defined(CONFIG_TI816X)
|
||||
unsigned int ocmc1clkctrl;
|
||||
#endif
|
||||
unsigned int resv4[2];
|
||||
unsigned int controlclkctrl;
|
||||
unsigned int resv5[2];
|
||||
unsigned int gpmcclkctrl;
|
||||
unsigned int ethernet0clkctrl;
|
||||
unsigned int ethernet1clkctrl;
|
||||
unsigned int mpuclkctrl;
|
||||
#if defined(CONFIG_TI814X)
|
||||
unsigned int debugssclkctrl;
|
||||
#elif defined(CONFIG_TI816X)
|
||||
unsigned int resv6[1];
|
||||
#endif
|
||||
unsigned int l3clkctrl;
|
||||
unsigned int l4hsclkctrl;
|
||||
unsigned int l4lsclkctrl;
|
||||
unsigned int rtcclkctrl;
|
||||
unsigned int tpccclkctrl;
|
||||
unsigned int tptc0clkctrl;
|
||||
unsigned int tptc1clkctrl;
|
||||
unsigned int tptc2clkctrl;
|
||||
unsigned int tptc3clkctrl;
|
||||
#if defined(CONFIG_TI814X)
|
||||
unsigned int resv6[4];
|
||||
unsigned int dcan01clkctrl;
|
||||
unsigned int mmchs0clkctrl;
|
||||
unsigned int mmchs1clkctrl;
|
||||
unsigned int mmchs2clkctrl;
|
||||
unsigned int custefuseclkctrl;
|
||||
#elif defined(CONFIG_TI816X)
|
||||
unsigned int sr0clkctrl;
|
||||
unsigned int sr1clkctrl;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* _CLOCK_TI81XX_H_ */
|
||||
38
u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
Normal file
38
u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* clocks_am33xx.h
|
||||
*
|
||||
* AM33xx clock define
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _CLOCKS_AM33XX_H_
|
||||
#define _CLOCKS_AM33XX_H_
|
||||
|
||||
/* MAIN PLL Fdll supported frequencies */
|
||||
#define MPUPLL_M_1000 1000
|
||||
#define MPUPLL_M_800 800
|
||||
#define MPUPLL_M_720 720
|
||||
#define MPUPLL_M_600 600
|
||||
#define MPUPLL_M_550 550
|
||||
#define MPUPLL_M_300 300
|
||||
|
||||
/* MAIN PLL Fdll = 550 MHz, by default */
|
||||
#ifndef CONFIG_SYS_MPUCLK
|
||||
#define CONFIG_SYS_MPUCLK MPUPLL_M_550
|
||||
#endif
|
||||
|
||||
#define UART_RESET (0x1 << 1)
|
||||
#define UART_CLK_RUNNING_MASK 0x1
|
||||
#define UART_SMART_IDLE_EN (0x1 << 0x3)
|
||||
|
||||
#define CM_DLL_CTRL_NO_OVERRIDE 0x0
|
||||
#define CM_DLL_READYST 0x4
|
||||
|
||||
extern void enable_dmm_clocks(void);
|
||||
extern const struct dpll_params dpll_core_opp100;
|
||||
extern struct dpll_params dpll_mpu_opp100;
|
||||
|
||||
#endif /* endif _CLOCKS_AM33XX_H_ */
|
||||
605
u-boot/arch/arm/include/asm/arch-am33xx/cpu.h
Normal file
605
u-boot/arch/arm/include/asm/arch-am33xx/cpu.h
Normal file
@@ -0,0 +1,605 @@
|
||||
/*
|
||||
* cpu.h
|
||||
*
|
||||
* AM33xx specific header file
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _AM33XX_CPU_H
|
||||
#define _AM33XX_CPU_H
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define CL_BIT(x) (0 << x)
|
||||
|
||||
/* Timer register bits */
|
||||
#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
|
||||
#define TCLR_AR BIT(1) /* Auto reload */
|
||||
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
|
||||
#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
|
||||
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
|
||||
#define TCLR_CE BIT(6) /* compare mode enable */
|
||||
#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
|
||||
#define TCLR_TCM BIT(8) /* edge detection of input pin*/
|
||||
#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
|
||||
#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
|
||||
#define TCLR_CAPTMODE BIT(13) /* capture mode */
|
||||
#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
|
||||
|
||||
#define TCFG_RESET BIT(0) /* software reset */
|
||||
#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
|
||||
#define TCFG_IDLEMOD_SHIFT (2) /* power management */
|
||||
/* device type */
|
||||
#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
|
||||
#define TST_DEVICE 0x0
|
||||
#define EMU_DEVICE 0x1
|
||||
#define HS_DEVICE 0x2
|
||||
#define GP_DEVICE 0x3
|
||||
|
||||
/* cpu-id for AM33XX and TI81XX family */
|
||||
#define AM335X 0xB944
|
||||
#define TI81XX 0xB81E
|
||||
#define DEVICE_ID (CTRL_BASE + 0x0600)
|
||||
#define DEVICE_ID_MASK 0x1FFF
|
||||
|
||||
/* MPU max frequencies */
|
||||
#define AM335X_ZCZ_300 0x1FEF
|
||||
#define AM335X_ZCZ_600 0x1FAF
|
||||
#define AM335X_ZCZ_720 0x1F2F
|
||||
#define AM335X_ZCZ_800 0x1E2F
|
||||
#define AM335X_ZCZ_1000 0x1C2F
|
||||
#define AM335X_ZCE_300 0x1FDF
|
||||
#define AM335X_ZCE_600 0x1F9F
|
||||
|
||||
/* This gives the status of the boot mode pins on the evm */
|
||||
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
|
||||
| BIT(3) | BIT(4))
|
||||
|
||||
#define PRM_RSTCTRL_RESET 0x01
|
||||
#define PRM_RSTST_WARM_RESET_MASK 0x232
|
||||
|
||||
/*
|
||||
* Watchdog:
|
||||
* Using the prescaler, the OMAP watchdog could go for many
|
||||
* months before firing. These limits work without scaling,
|
||||
* with the 60 second default assumed by most tools and docs.
|
||||
*/
|
||||
#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
|
||||
#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
|
||||
#define TIMER_MARGIN_MIN 1
|
||||
|
||||
#define PTV 0 /* prescale */
|
||||
#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
|
||||
#define WDT_WWPS_PEND_WCLR BIT(0)
|
||||
#define WDT_WWPS_PEND_WLDR BIT(2)
|
||||
#define WDT_WWPS_PEND_WTGR BIT(3)
|
||||
#define WDT_WWPS_PEND_WSPR BIT(4)
|
||||
|
||||
#define WDT_WCLR_PRE BIT(5)
|
||||
#define WDT_WCLR_PTV_OFF 2
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
#ifndef CONFIG_AM43XX
|
||||
/* Encapsulating core pll registers */
|
||||
struct cm_wkuppll {
|
||||
unsigned int wkclkstctrl; /* offset 0x00 */
|
||||
unsigned int wkctrlclkctrl; /* offset 0x04 */
|
||||
unsigned int wkgpio0clkctrl; /* offset 0x08 */
|
||||
unsigned int wkl4wkclkctrl; /* offset 0x0c */
|
||||
unsigned int timer0clkctrl; /* offset 0x10 */
|
||||
unsigned int resv2[3];
|
||||
unsigned int idlestdpllmpu; /* offset 0x20 */
|
||||
unsigned int sscdeltamstepdllmpu; /* off 0x24 */
|
||||
unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
|
||||
unsigned int clkseldpllmpu; /* offset 0x2c */
|
||||
unsigned int resv4[1];
|
||||
unsigned int idlestdpllddr; /* offset 0x34 */
|
||||
unsigned int resv5[2];
|
||||
unsigned int clkseldpllddr; /* offset 0x40 */
|
||||
unsigned int resv6[4];
|
||||
unsigned int clkseldplldisp; /* offset 0x54 */
|
||||
unsigned int resv7[1];
|
||||
unsigned int idlestdpllcore; /* offset 0x5c */
|
||||
unsigned int resv8[2];
|
||||
unsigned int clkseldpllcore; /* offset 0x68 */
|
||||
unsigned int resv9[1];
|
||||
unsigned int idlestdpllper; /* offset 0x70 */
|
||||
unsigned int resv10[2];
|
||||
unsigned int clkdcoldodpllper; /* offset 0x7c */
|
||||
unsigned int divm4dpllcore; /* offset 0x80 */
|
||||
unsigned int divm5dpllcore; /* offset 0x84 */
|
||||
unsigned int clkmoddpllmpu; /* offset 0x88 */
|
||||
unsigned int clkmoddpllper; /* offset 0x8c */
|
||||
unsigned int clkmoddpllcore; /* offset 0x90 */
|
||||
unsigned int clkmoddpllddr; /* offset 0x94 */
|
||||
unsigned int clkmoddplldisp; /* offset 0x98 */
|
||||
unsigned int clkseldpllper; /* offset 0x9c */
|
||||
unsigned int divm2dpllddr; /* offset 0xA0 */
|
||||
unsigned int divm2dplldisp; /* offset 0xA4 */
|
||||
unsigned int divm2dpllmpu; /* offset 0xA8 */
|
||||
unsigned int divm2dpllper; /* offset 0xAC */
|
||||
unsigned int resv11[1];
|
||||
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
|
||||
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
|
||||
unsigned int wkup_adctscctrl; /* offset 0xBC */
|
||||
unsigned int resv12;
|
||||
unsigned int timer1clkctrl; /* offset 0xC4 */
|
||||
unsigned int resv13[4];
|
||||
unsigned int divm6dpllcore; /* offset 0xD8 */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulating peripheral functional clocks
|
||||
* pll registers
|
||||
*/
|
||||
struct cm_perpll {
|
||||
unsigned int l4lsclkstctrl; /* offset 0x00 */
|
||||
unsigned int l3sclkstctrl; /* offset 0x04 */
|
||||
unsigned int l4fwclkstctrl; /* offset 0x08 */
|
||||
unsigned int l3clkstctrl; /* offset 0x0c */
|
||||
unsigned int resv1;
|
||||
unsigned int cpgmac0clkctrl; /* offset 0x14 */
|
||||
unsigned int lcdclkctrl; /* offset 0x18 */
|
||||
unsigned int usb0clkctrl; /* offset 0x1C */
|
||||
unsigned int resv2;
|
||||
unsigned int tptc0clkctrl; /* offset 0x24 */
|
||||
unsigned int emifclkctrl; /* offset 0x28 */
|
||||
unsigned int ocmcramclkctrl; /* offset 0x2c */
|
||||
unsigned int gpmcclkctrl; /* offset 0x30 */
|
||||
unsigned int mcasp0clkctrl; /* offset 0x34 */
|
||||
unsigned int uart5clkctrl; /* offset 0x38 */
|
||||
unsigned int mmc0clkctrl; /* offset 0x3C */
|
||||
unsigned int elmclkctrl; /* offset 0x40 */
|
||||
unsigned int i2c2clkctrl; /* offset 0x44 */
|
||||
unsigned int i2c1clkctrl; /* offset 0x48 */
|
||||
unsigned int spi0clkctrl; /* offset 0x4C */
|
||||
unsigned int spi1clkctrl; /* offset 0x50 */
|
||||
unsigned int resv3[3];
|
||||
unsigned int l4lsclkctrl; /* offset 0x60 */
|
||||
unsigned int l4fwclkctrl; /* offset 0x64 */
|
||||
unsigned int mcasp1clkctrl; /* offset 0x68 */
|
||||
unsigned int uart1clkctrl; /* offset 0x6C */
|
||||
unsigned int uart2clkctrl; /* offset 0x70 */
|
||||
unsigned int uart3clkctrl; /* offset 0x74 */
|
||||
unsigned int uart4clkctrl; /* offset 0x78 */
|
||||
unsigned int timer7clkctrl; /* offset 0x7C */
|
||||
unsigned int timer2clkctrl; /* offset 0x80 */
|
||||
unsigned int timer3clkctrl; /* offset 0x84 */
|
||||
unsigned int timer4clkctrl; /* offset 0x88 */
|
||||
unsigned int resv4[8];
|
||||
unsigned int gpio1clkctrl; /* offset 0xAC */
|
||||
unsigned int gpio2clkctrl; /* offset 0xB0 */
|
||||
unsigned int gpio3clkctrl; /* offset 0xB4 */
|
||||
unsigned int resv5;
|
||||
unsigned int tpccclkctrl; /* offset 0xBC */
|
||||
unsigned int dcan0clkctrl; /* offset 0xC0 */
|
||||
unsigned int dcan1clkctrl; /* offset 0xC4 */
|
||||
unsigned int resv6;
|
||||
unsigned int epwmss1clkctrl; /* offset 0xCC */
|
||||
unsigned int emiffwclkctrl; /* offset 0xD0 */
|
||||
unsigned int epwmss0clkctrl; /* offset 0xD4 */
|
||||
unsigned int epwmss2clkctrl; /* offset 0xD8 */
|
||||
unsigned int l3instrclkctrl; /* offset 0xDC */
|
||||
unsigned int l3clkctrl; /* Offset 0xE0 */
|
||||
unsigned int resv8[2];
|
||||
unsigned int timer5clkctrl; /* offset 0xEC */
|
||||
unsigned int timer6clkctrl; /* offset 0xF0 */
|
||||
unsigned int mmc1clkctrl; /* offset 0xF4 */
|
||||
unsigned int mmc2clkctrl; /* offset 0xF8 */
|
||||
unsigned int resv9[8];
|
||||
unsigned int l4hsclkstctrl; /* offset 0x11C */
|
||||
unsigned int l4hsclkctrl; /* offset 0x120 */
|
||||
unsigned int resv10[8];
|
||||
unsigned int cpswclkstctrl; /* offset 0x144 */
|
||||
unsigned int lcdcclkstctrl; /* offset 0x148 */
|
||||
};
|
||||
|
||||
/* Encapsulating Display pll registers */
|
||||
struct cm_dpll {
|
||||
unsigned int resv1;
|
||||
unsigned int clktimer7clk; /* offset 0x04 */
|
||||
unsigned int clktimer2clk; /* offset 0x08 */
|
||||
unsigned int clktimer3clk; /* offset 0x0C */
|
||||
unsigned int clktimer4clk; /* offset 0x10 */
|
||||
unsigned int resv2;
|
||||
unsigned int clktimer5clk; /* offset 0x18 */
|
||||
unsigned int clktimer6clk; /* offset 0x1C */
|
||||
unsigned int resv3[2];
|
||||
unsigned int clktimer1clk; /* offset 0x28 */
|
||||
unsigned int resv4[2];
|
||||
unsigned int clklcdcpixelclk; /* offset 0x34 */
|
||||
};
|
||||
|
||||
struct prm_device_inst {
|
||||
unsigned int prm_rstctrl;
|
||||
unsigned int prm_rsttime;
|
||||
unsigned int prm_rstst;
|
||||
};
|
||||
#else
|
||||
/* Encapsulating core pll registers */
|
||||
struct cm_wkuppll {
|
||||
unsigned int resv0[136];
|
||||
unsigned int wkl4wkclkctrl; /* offset 0x220 */
|
||||
unsigned int resv1[7];
|
||||
unsigned int usbphy0clkctrl; /* offset 0x240 */
|
||||
unsigned int resv112;
|
||||
unsigned int usbphy1clkctrl; /* offset 0x248 */
|
||||
unsigned int resv113[45];
|
||||
unsigned int wkclkstctrl; /* offset 0x300 */
|
||||
unsigned int resv2[15];
|
||||
unsigned int wkup_i2c0ctrl; /* offset 0x340 */
|
||||
unsigned int resv3;
|
||||
unsigned int wkup_uart0ctrl; /* offset 0x348 */
|
||||
unsigned int resv4[5];
|
||||
unsigned int wkctrlclkctrl; /* offset 0x360 */
|
||||
unsigned int resv5;
|
||||
unsigned int wkgpio0clkctrl; /* offset 0x368 */
|
||||
|
||||
unsigned int resv6[109];
|
||||
unsigned int clkmoddpllcore; /* offset 0x520 */
|
||||
unsigned int idlestdpllcore; /* offset 0x524 */
|
||||
unsigned int resv61;
|
||||
unsigned int clkseldpllcore; /* offset 0x52C */
|
||||
unsigned int resv7[2];
|
||||
unsigned int divm4dpllcore; /* offset 0x538 */
|
||||
unsigned int divm5dpllcore; /* offset 0x53C */
|
||||
unsigned int divm6dpllcore; /* offset 0x540 */
|
||||
|
||||
unsigned int resv8[7];
|
||||
unsigned int clkmoddpllmpu; /* offset 0x560 */
|
||||
unsigned int idlestdpllmpu; /* offset 0x564 */
|
||||
unsigned int resv9;
|
||||
unsigned int clkseldpllmpu; /* offset 0x56c */
|
||||
unsigned int divm2dpllmpu; /* offset 0x570 */
|
||||
|
||||
unsigned int resv10[11];
|
||||
unsigned int clkmoddpllddr; /* offset 0x5A0 */
|
||||
unsigned int idlestdpllddr; /* offset 0x5A4 */
|
||||
unsigned int resv11;
|
||||
unsigned int clkseldpllddr; /* offset 0x5AC */
|
||||
unsigned int divm2dpllddr; /* offset 0x5B0 */
|
||||
|
||||
unsigned int resv12[11];
|
||||
unsigned int clkmoddpllper; /* offset 0x5E0 */
|
||||
unsigned int idlestdpllper; /* offset 0x5E4 */
|
||||
unsigned int resv13;
|
||||
unsigned int clkseldpllper; /* offset 0x5EC */
|
||||
unsigned int divm2dpllper; /* offset 0x5F0 */
|
||||
unsigned int resv14[8];
|
||||
unsigned int clkdcoldodpllper; /* offset 0x614 */
|
||||
|
||||
unsigned int resv15[2];
|
||||
unsigned int clkmoddplldisp; /* offset 0x620 */
|
||||
unsigned int resv16[2];
|
||||
unsigned int clkseldplldisp; /* offset 0x62C */
|
||||
unsigned int divm2dplldisp; /* offset 0x630 */
|
||||
};
|
||||
|
||||
/*
|
||||
* Encapsulating peripheral functional clocks
|
||||
* pll registers
|
||||
*/
|
||||
struct cm_perpll {
|
||||
unsigned int l3clkstctrl; /* offset 0x00 */
|
||||
unsigned int resv0[7];
|
||||
unsigned int l3clkctrl; /* Offset 0x20 */
|
||||
unsigned int resv112[7];
|
||||
unsigned int l3instrclkctrl; /* offset 0x40 */
|
||||
unsigned int resv2[3];
|
||||
unsigned int ocmcramclkctrl; /* offset 0x50 */
|
||||
unsigned int resv3[9];
|
||||
unsigned int tpccclkctrl; /* offset 0x78 */
|
||||
unsigned int resv4;
|
||||
unsigned int tptc0clkctrl; /* offset 0x80 */
|
||||
|
||||
unsigned int resv5[7];
|
||||
unsigned int l4hsclkctrl; /* offset 0x0A0 */
|
||||
unsigned int resv6;
|
||||
unsigned int l4fwclkctrl; /* offset 0x0A8 */
|
||||
unsigned int resv7[85];
|
||||
unsigned int l3sclkstctrl; /* offset 0x200 */
|
||||
unsigned int resv8[7];
|
||||
unsigned int gpmcclkctrl; /* offset 0x220 */
|
||||
unsigned int resv9[5];
|
||||
unsigned int mcasp0clkctrl; /* offset 0x238 */
|
||||
unsigned int resv10;
|
||||
unsigned int mcasp1clkctrl; /* offset 0x240 */
|
||||
unsigned int resv11;
|
||||
unsigned int mmc2clkctrl; /* offset 0x248 */
|
||||
unsigned int resv12[3];
|
||||
unsigned int qspiclkctrl; /* offset 0x258 */
|
||||
unsigned int resv121;
|
||||
unsigned int usb0clkctrl; /* offset 0x260 */
|
||||
unsigned int resv122;
|
||||
unsigned int usb1clkctrl; /* offset 0x268 */
|
||||
unsigned int resv13[101];
|
||||
unsigned int l4lsclkstctrl; /* offset 0x400 */
|
||||
unsigned int resv14[7];
|
||||
unsigned int l4lsclkctrl; /* offset 0x420 */
|
||||
unsigned int resv15;
|
||||
unsigned int dcan0clkctrl; /* offset 0x428 */
|
||||
unsigned int resv16;
|
||||
unsigned int dcan1clkctrl; /* offset 0x430 */
|
||||
unsigned int resv17[13];
|
||||
unsigned int elmclkctrl; /* offset 0x468 */
|
||||
|
||||
unsigned int resv18[3];
|
||||
unsigned int gpio1clkctrl; /* offset 0x478 */
|
||||
unsigned int resv19;
|
||||
unsigned int gpio2clkctrl; /* offset 0x480 */
|
||||
unsigned int resv20;
|
||||
unsigned int gpio3clkctrl; /* offset 0x488 */
|
||||
unsigned int resv41;
|
||||
unsigned int gpio4clkctrl; /* offset 0x490 */
|
||||
unsigned int resv42;
|
||||
unsigned int gpio5clkctrl; /* offset 0x498 */
|
||||
unsigned int resv21[3];
|
||||
|
||||
unsigned int i2c1clkctrl; /* offset 0x4A8 */
|
||||
unsigned int resv22;
|
||||
unsigned int i2c2clkctrl; /* offset 0x4B0 */
|
||||
unsigned int resv23[3];
|
||||
unsigned int mmc0clkctrl; /* offset 0x4C0 */
|
||||
unsigned int resv24;
|
||||
unsigned int mmc1clkctrl; /* offset 0x4C8 */
|
||||
|
||||
unsigned int resv25[13];
|
||||
unsigned int spi0clkctrl; /* offset 0x500 */
|
||||
unsigned int resv26;
|
||||
unsigned int spi1clkctrl; /* offset 0x508 */
|
||||
unsigned int resv27[9];
|
||||
unsigned int timer2clkctrl; /* offset 0x530 */
|
||||
unsigned int resv28;
|
||||
unsigned int timer3clkctrl; /* offset 0x538 */
|
||||
unsigned int resv29;
|
||||
unsigned int timer4clkctrl; /* offset 0x540 */
|
||||
unsigned int resv30[5];
|
||||
unsigned int timer7clkctrl; /* offset 0x558 */
|
||||
|
||||
unsigned int resv31[9];
|
||||
unsigned int uart1clkctrl; /* offset 0x580 */
|
||||
unsigned int resv32;
|
||||
unsigned int uart2clkctrl; /* offset 0x588 */
|
||||
unsigned int resv33;
|
||||
unsigned int uart3clkctrl; /* offset 0x590 */
|
||||
unsigned int resv34;
|
||||
unsigned int uart4clkctrl; /* offset 0x598 */
|
||||
unsigned int resv35;
|
||||
unsigned int uart5clkctrl; /* offset 0x5A0 */
|
||||
unsigned int resv36[5];
|
||||
unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
|
||||
unsigned int resv361;
|
||||
unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
|
||||
unsigned int resv3611[79];
|
||||
|
||||
unsigned int emifclkstctrl; /* offset 0x700 */
|
||||
unsigned int resv362[7];
|
||||
unsigned int emifclkctrl; /* offset 0x720 */
|
||||
unsigned int resv37[3];
|
||||
unsigned int emiffwclkctrl; /* offset 0x730 */
|
||||
unsigned int resv371;
|
||||
unsigned int otfaemifclkctrl; /* offset 0x738 */
|
||||
unsigned int resv38[57];
|
||||
unsigned int lcdclkctrl; /* offset 0x820 */
|
||||
unsigned int resv39[183];
|
||||
unsigned int cpswclkstctrl; /* offset 0xB00 */
|
||||
unsigned int resv40[7];
|
||||
unsigned int cpgmac0clkctrl; /* offset 0xB20 */
|
||||
};
|
||||
|
||||
struct cm_device_inst {
|
||||
unsigned int cm_clkout1_ctrl;
|
||||
unsigned int cm_dll_ctrl;
|
||||
};
|
||||
|
||||
struct prm_device_inst {
|
||||
unsigned int prm_rstctrl;
|
||||
unsigned int prm_rstst;
|
||||
};
|
||||
|
||||
struct cm_dpll {
|
||||
unsigned int resv1;
|
||||
unsigned int clktimer2clk; /* offset 0x04 */
|
||||
unsigned int resv2[11];
|
||||
unsigned int clkselmacclk; /* offset 0x34 */
|
||||
};
|
||||
#endif /* CONFIG_AM43XX */
|
||||
|
||||
/* Control Module RTC registers */
|
||||
struct cm_rtc {
|
||||
unsigned int rtcclkctrl; /* offset 0x0 */
|
||||
unsigned int clkstctrl; /* offset 0x4 */
|
||||
};
|
||||
|
||||
/* Watchdog timer registers */
|
||||
struct wd_timer {
|
||||
unsigned int resv1[4];
|
||||
unsigned int wdtwdsc; /* offset 0x010 */
|
||||
unsigned int wdtwdst; /* offset 0x014 */
|
||||
unsigned int wdtwisr; /* offset 0x018 */
|
||||
unsigned int wdtwier; /* offset 0x01C */
|
||||
unsigned int wdtwwer; /* offset 0x020 */
|
||||
unsigned int wdtwclr; /* offset 0x024 */
|
||||
unsigned int wdtwcrr; /* offset 0x028 */
|
||||
unsigned int wdtwldr; /* offset 0x02C */
|
||||
unsigned int wdtwtgr; /* offset 0x030 */
|
||||
unsigned int wdtwwps; /* offset 0x034 */
|
||||
unsigned int resv2[3];
|
||||
unsigned int wdtwdly; /* offset 0x044 */
|
||||
unsigned int wdtwspr; /* offset 0x048 */
|
||||
unsigned int resv3[1];
|
||||
unsigned int wdtwqeoi; /* offset 0x050 */
|
||||
unsigned int wdtwqstar; /* offset 0x054 */
|
||||
unsigned int wdtwqsta; /* offset 0x058 */
|
||||
unsigned int wdtwqens; /* offset 0x05C */
|
||||
unsigned int wdtwqenc; /* offset 0x060 */
|
||||
unsigned int resv4[39];
|
||||
unsigned int wdt_unfr; /* offset 0x100 */
|
||||
};
|
||||
|
||||
/* Timer 32 bit registers */
|
||||
struct gptimer {
|
||||
unsigned int tidr; /* offset 0x00 */
|
||||
unsigned char res1[12];
|
||||
unsigned int tiocp_cfg; /* offset 0x10 */
|
||||
unsigned char res2[12];
|
||||
unsigned int tier; /* offset 0x20 */
|
||||
unsigned int tistatr; /* offset 0x24 */
|
||||
unsigned int tistat; /* offset 0x28 */
|
||||
unsigned int tisr; /* offset 0x2c */
|
||||
unsigned int tcicr; /* offset 0x30 */
|
||||
unsigned int twer; /* offset 0x34 */
|
||||
unsigned int tclr; /* offset 0x38 */
|
||||
unsigned int tcrr; /* offset 0x3c */
|
||||
unsigned int tldr; /* offset 0x40 */
|
||||
unsigned int ttgr; /* offset 0x44 */
|
||||
unsigned int twpc; /* offset 0x48 */
|
||||
unsigned int tmar; /* offset 0x4c */
|
||||
unsigned int tcar1; /* offset 0x50 */
|
||||
unsigned int tscir; /* offset 0x54 */
|
||||
unsigned int tcar2; /* offset 0x58 */
|
||||
};
|
||||
|
||||
/* UART Registers */
|
||||
struct uart_sys {
|
||||
unsigned int resv1[21];
|
||||
unsigned int uartsyscfg; /* offset 0x54 */
|
||||
unsigned int uartsyssts; /* offset 0x58 */
|
||||
};
|
||||
|
||||
/* VTP Registers */
|
||||
struct vtp_reg {
|
||||
unsigned int vtp0ctrlreg;
|
||||
};
|
||||
|
||||
/* Control Status Register */
|
||||
struct ctrl_stat {
|
||||
unsigned int resv1[16];
|
||||
unsigned int statusreg; /* ofset 0x40 */
|
||||
unsigned int resv2[51];
|
||||
unsigned int secure_emif_sdram_config; /* offset 0x0110 */
|
||||
unsigned int resv3[319];
|
||||
unsigned int dev_attr;
|
||||
};
|
||||
|
||||
/* AM33XX GPIO registers */
|
||||
#define OMAP_GPIO_REVISION 0x0000
|
||||
#define OMAP_GPIO_SYSCONFIG 0x0010
|
||||
#define OMAP_GPIO_SYSSTATUS 0x0114
|
||||
#define OMAP_GPIO_IRQSTATUS1 0x002c
|
||||
#define OMAP_GPIO_IRQSTATUS2 0x0030
|
||||
#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034
|
||||
#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038
|
||||
#define OMAP_GPIO_CTRL 0x0130
|
||||
#define OMAP_GPIO_OE 0x0134
|
||||
#define OMAP_GPIO_DATAIN 0x0138
|
||||
#define OMAP_GPIO_DATAOUT 0x013c
|
||||
#define OMAP_GPIO_LEVELDETECT0 0x0140
|
||||
#define OMAP_GPIO_LEVELDETECT1 0x0144
|
||||
#define OMAP_GPIO_RISINGDETECT 0x0148
|
||||
#define OMAP_GPIO_FALLINGDETECT 0x014c
|
||||
#define OMAP_GPIO_DEBOUNCE_EN 0x0150
|
||||
#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
|
||||
#define OMAP_GPIO_CLEARDATAOUT 0x0190
|
||||
#define OMAP_GPIO_SETDATAOUT 0x0194
|
||||
|
||||
/* Control Device Register */
|
||||
|
||||
/* Control Device Register */
|
||||
#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
|
||||
#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
|
||||
#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
|
||||
|
||||
struct ctrl_dev {
|
||||
unsigned int deviceid; /* offset 0x00 */
|
||||
unsigned int resv1[7];
|
||||
unsigned int usb_ctrl0; /* offset 0x20 */
|
||||
unsigned int resv2;
|
||||
unsigned int usb_ctrl1; /* offset 0x28 */
|
||||
unsigned int resv3;
|
||||
unsigned int macid0l; /* offset 0x30 */
|
||||
unsigned int macid0h; /* offset 0x34 */
|
||||
unsigned int macid1l; /* offset 0x38 */
|
||||
unsigned int macid1h; /* offset 0x3c */
|
||||
unsigned int resv4[4];
|
||||
unsigned int miisel; /* offset 0x50 */
|
||||
unsigned int resv5[7];
|
||||
unsigned int mreqprio_0; /* offset 0x70 */
|
||||
unsigned int mreqprio_1; /* offset 0x74 */
|
||||
unsigned int resv6[97];
|
||||
unsigned int efuse_sma; /* offset 0x1FC */
|
||||
};
|
||||
|
||||
/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
|
||||
#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
|
||||
#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
|
||||
#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
|
||||
|
||||
struct l3f_cfg_bwlimiter {
|
||||
u32 padding0[2];
|
||||
u32 modena_init0_bw_fractional;
|
||||
u32 modena_init0_bw_integer;
|
||||
u32 modena_init0_watermark_0;
|
||||
};
|
||||
|
||||
/* gmii_sel register defines */
|
||||
#define GMII1_SEL_MII 0x0
|
||||
#define GMII1_SEL_RMII 0x1
|
||||
#define GMII1_SEL_RGMII 0x2
|
||||
#define GMII2_SEL_MII 0x0
|
||||
#define GMII2_SEL_RMII 0x4
|
||||
#define GMII2_SEL_RGMII 0x8
|
||||
#define RGMII1_IDMODE BIT(4)
|
||||
#define RGMII2_IDMODE BIT(5)
|
||||
#define RMII1_IO_CLK_EN BIT(6)
|
||||
#define RMII2_IO_CLK_EN BIT(7)
|
||||
|
||||
#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
|
||||
#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
|
||||
#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
|
||||
#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
|
||||
#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
|
||||
|
||||
/* PWMSS */
|
||||
struct pwmss_regs {
|
||||
unsigned int idver;
|
||||
unsigned int sysconfig;
|
||||
unsigned int clkconfig;
|
||||
unsigned int clkstatus;
|
||||
};
|
||||
#define ECAP_CLK_EN BIT(0)
|
||||
#define ECAP_CLK_STOP_REQ BIT(1)
|
||||
|
||||
struct pwmss_ecap_regs {
|
||||
unsigned int tsctr;
|
||||
unsigned int ctrphs;
|
||||
unsigned int cap1;
|
||||
unsigned int cap2;
|
||||
unsigned int cap3;
|
||||
unsigned int cap4;
|
||||
unsigned int resv1[4];
|
||||
unsigned short ecctl1;
|
||||
unsigned short ecctl2;
|
||||
};
|
||||
|
||||
/* Capture Control register 2 */
|
||||
#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
|
||||
#define ECTRL2_MDSL_ECAP BIT(9)
|
||||
#define ECTRL2_CTRSTP_FREERUN BIT(4)
|
||||
#define ECTRL2_PLSL_LOW BIT(10)
|
||||
#define ECTRL2_SYNC_EN BIT(5)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#endif /* _AM33XX_CPU_H */
|
||||
362
u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h
Normal file
362
u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h
Normal file
@@ -0,0 +1,362 @@
|
||||
/*
|
||||
* ddr_defs.h
|
||||
*
|
||||
* ddr specific header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _DDR_DEFS_H
|
||||
#define _DDR_DEFS_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/emif.h>
|
||||
|
||||
/* AM335X EMIF Register values */
|
||||
#define VTP_CTRL_READY (0x1 << 5)
|
||||
#define VTP_CTRL_ENABLE (0x1 << 6)
|
||||
#define VTP_CTRL_START_EN (0x1)
|
||||
#ifdef CONFIG_AM43XX
|
||||
#define DDR_CKE_CTRL_NORMAL 0x3
|
||||
#else
|
||||
#define DDR_CKE_CTRL_NORMAL 0x1
|
||||
#endif
|
||||
#define PHY_EN_DYN_PWRDN (0x1 << 20)
|
||||
|
||||
/* Micron MT47H128M16RT-25E */
|
||||
#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
|
||||
#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
|
||||
#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
|
||||
#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
|
||||
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
|
||||
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
|
||||
#define MT47H128M16RT25E_RATIO 0x80
|
||||
#define MT47H128M16RT25E_RD_DQS 0x12
|
||||
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
|
||||
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
|
||||
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41J128M16JT-125 */
|
||||
#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
|
||||
#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
|
||||
#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
|
||||
#define MT41J128MJT125_EMIF_TIM3 0x501F830F
|
||||
#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
|
||||
#define MT41J128MJT125_EMIF_SDREF 0x0000093B
|
||||
#define MT41J128MJT125_ZQ_CFG 0x50074BE4
|
||||
#define MT41J128MJT125_RATIO 0x40
|
||||
#define MT41J128MJT125_INVERT_CLKOUT 0x1
|
||||
#define MT41J128MJT125_RD_DQS 0x3B
|
||||
#define MT41J128MJT125_WR_DQS 0x85
|
||||
#define MT41J128MJT125_PHY_WR_DATA 0xC1
|
||||
#define MT41J128MJT125_PHY_FIFO_WE 0x100
|
||||
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41J128M16JT-125 at 400MHz*/
|
||||
#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
|
||||
#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
|
||||
#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
|
||||
#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
|
||||
#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
|
||||
#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
|
||||
#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
|
||||
#define MT41J128MJT125_RATIO_400MHz 0x80
|
||||
#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
|
||||
#define MT41J128MJT125_RD_DQS_400MHz 0x3A
|
||||
#define MT41J128MJT125_WR_DQS_400MHz 0x3B
|
||||
#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
|
||||
#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
|
||||
|
||||
/* Micron MT41K128M16JT-187E */
|
||||
#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
|
||||
#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
|
||||
#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
|
||||
#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
|
||||
#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
|
||||
#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
|
||||
#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
|
||||
#define MT41K128MJT187E_RATIO 0x40
|
||||
#define MT41K128MJT187E_INVERT_CLKOUT 0x1
|
||||
#define MT41K128MJT187E_RD_DQS 0x3B
|
||||
#define MT41K128MJT187E_WR_DQS 0x85
|
||||
#define MT41K128MJT187E_PHY_WR_DATA 0xC1
|
||||
#define MT41K128MJT187E_PHY_FIFO_WE 0x100
|
||||
#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41J64M16JT-125 */
|
||||
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
|
||||
|
||||
/* Micron MT41J256M16JT-125 */
|
||||
#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
|
||||
|
||||
/* Micron MT41J256M8HX-15E */
|
||||
#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
|
||||
#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
|
||||
#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
|
||||
#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
|
||||
#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
|
||||
#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
|
||||
#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
|
||||
#define MT41J256M8HX15E_RATIO 0x40
|
||||
#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
|
||||
#define MT41J256M8HX15E_RD_DQS 0x3B
|
||||
#define MT41J256M8HX15E_WR_DQS 0x85
|
||||
#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
|
||||
#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
|
||||
#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41K256M16HA-125E */
|
||||
#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
|
||||
#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
|
||||
#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
|
||||
#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
|
||||
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
|
||||
#define MT41K256M16HA125E_EMIF_SDREF 0xC30
|
||||
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
|
||||
#define MT41K256M16HA125E_RATIO 0x80
|
||||
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
|
||||
#define MT41K256M16HA125E_RD_DQS 0x38
|
||||
#define MT41K256M16HA125E_WR_DQS 0x44
|
||||
#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
|
||||
#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
|
||||
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41J512M8RH-125 on EVM v1.5 */
|
||||
#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
|
||||
#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
|
||||
#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
|
||||
#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
|
||||
#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
|
||||
#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
|
||||
#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
|
||||
#define MT41J512M8RH125_RATIO 0x80
|
||||
#define MT41J512M8RH125_INVERT_CLKOUT 0x0
|
||||
#define MT41J512M8RH125_RD_DQS 0x3B
|
||||
#define MT41J512M8RH125_WR_DQS 0x3C
|
||||
#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
|
||||
#define MT41J512M8RH125_PHY_WR_DATA 0x74
|
||||
#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Samsung K4B2G1646E-BIH9 */
|
||||
#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
|
||||
#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
|
||||
#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
|
||||
#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
|
||||
#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
|
||||
#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
|
||||
#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
|
||||
#define K4B2G1646EBIH9_RATIO 0x80
|
||||
#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
|
||||
#define K4B2G1646EBIH9_RD_DQS 0x35
|
||||
#define K4B2G1646EBIH9_WR_DQS 0x3A
|
||||
#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
|
||||
#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
|
||||
#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
|
||||
|
||||
#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
|
||||
#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
|
||||
#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
|
||||
#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
|
||||
#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
|
||||
#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
|
||||
#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
|
||||
|
||||
#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
|
||||
#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
|
||||
#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
|
||||
#define DDR3_DATA0_IOCTRL_VALUE 0x84
|
||||
#define DDR3_DATA1_IOCTRL_VALUE 0x84
|
||||
#define DDR3_DATA2_IOCTRL_VALUE 0x84
|
||||
#define DDR3_DATA3_IOCTRL_VALUE 0x84
|
||||
|
||||
/**
|
||||
* Configure DMM
|
||||
*/
|
||||
void config_dmm(const struct dmm_lisa_map_regs *regs);
|
||||
|
||||
/**
|
||||
* Configure SDRAM
|
||||
*/
|
||||
void config_sdram(const struct emif_regs *regs, int nr);
|
||||
void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
|
||||
|
||||
/**
|
||||
* Set SDRAM timings
|
||||
*/
|
||||
void set_sdram_timings(const struct emif_regs *regs, int nr);
|
||||
|
||||
/**
|
||||
* Configure DDR PHY
|
||||
*/
|
||||
void config_ddr_phy(const struct emif_regs *regs, int nr);
|
||||
|
||||
struct ddr_cmd_regs {
|
||||
unsigned int resv0[7];
|
||||
unsigned int cm0csratio; /* offset 0x01C */
|
||||
unsigned int resv1[3];
|
||||
unsigned int cm0iclkout; /* offset 0x02C */
|
||||
unsigned int resv2[8];
|
||||
unsigned int cm1csratio; /* offset 0x050 */
|
||||
unsigned int resv3[3];
|
||||
unsigned int cm1iclkout; /* offset 0x060 */
|
||||
unsigned int resv4[8];
|
||||
unsigned int cm2csratio; /* offset 0x084 */
|
||||
unsigned int resv5[3];
|
||||
unsigned int cm2iclkout; /* offset 0x094 */
|
||||
unsigned int resv6[3];
|
||||
};
|
||||
|
||||
struct ddr_data_regs {
|
||||
unsigned int dt0rdsratio0; /* offset 0x0C8 */
|
||||
unsigned int resv1[4];
|
||||
unsigned int dt0wdsratio0; /* offset 0x0DC */
|
||||
unsigned int resv2[4];
|
||||
unsigned int dt0wiratio0; /* offset 0x0F0 */
|
||||
unsigned int resv3;
|
||||
unsigned int dt0wimode0; /* offset 0x0F8 */
|
||||
unsigned int dt0giratio0; /* offset 0x0FC */
|
||||
unsigned int resv4;
|
||||
unsigned int dt0gimode0; /* offset 0x104 */
|
||||
unsigned int dt0fwsratio0; /* offset 0x108 */
|
||||
unsigned int resv5[4];
|
||||
unsigned int dt0dqoffset; /* offset 0x11C */
|
||||
unsigned int dt0wrsratio0; /* offset 0x120 */
|
||||
unsigned int resv6[4];
|
||||
unsigned int dt0rdelays0; /* offset 0x134 */
|
||||
unsigned int dt0dldiff0; /* offset 0x138 */
|
||||
unsigned int resv7[12];
|
||||
};
|
||||
|
||||
/**
|
||||
* This structure represents the DDR registers on AM33XX devices.
|
||||
* We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
|
||||
* correspond to DATA1 registers defined here.
|
||||
*/
|
||||
struct ddr_regs {
|
||||
unsigned int resv0[3];
|
||||
unsigned int cm0config; /* offset 0x00C */
|
||||
unsigned int cm0configclk; /* offset 0x010 */
|
||||
unsigned int resv1[2];
|
||||
unsigned int cm0csratio; /* offset 0x01C */
|
||||
unsigned int resv2[3];
|
||||
unsigned int cm0iclkout; /* offset 0x02C */
|
||||
unsigned int resv3[4];
|
||||
unsigned int cm1config; /* offset 0x040 */
|
||||
unsigned int cm1configclk; /* offset 0x044 */
|
||||
unsigned int resv4[2];
|
||||
unsigned int cm1csratio; /* offset 0x050 */
|
||||
unsigned int resv5[3];
|
||||
unsigned int cm1iclkout; /* offset 0x060 */
|
||||
unsigned int resv6[4];
|
||||
unsigned int cm2config; /* offset 0x074 */
|
||||
unsigned int cm2configclk; /* offset 0x078 */
|
||||
unsigned int resv7[2];
|
||||
unsigned int cm2csratio; /* offset 0x084 */
|
||||
unsigned int resv8[3];
|
||||
unsigned int cm2iclkout; /* offset 0x094 */
|
||||
unsigned int resv9[12];
|
||||
unsigned int dt0rdsratio0; /* offset 0x0C8 */
|
||||
unsigned int resv10[4];
|
||||
unsigned int dt0wdsratio0; /* offset 0x0DC */
|
||||
unsigned int resv11[4];
|
||||
unsigned int dt0wiratio0; /* offset 0x0F0 */
|
||||
unsigned int resv12;
|
||||
unsigned int dt0wimode0; /* offset 0x0F8 */
|
||||
unsigned int dt0giratio0; /* offset 0x0FC */
|
||||
unsigned int resv13;
|
||||
unsigned int dt0gimode0; /* offset 0x104 */
|
||||
unsigned int dt0fwsratio0; /* offset 0x108 */
|
||||
unsigned int resv14[4];
|
||||
unsigned int dt0dqoffset; /* offset 0x11C */
|
||||
unsigned int dt0wrsratio0; /* offset 0x120 */
|
||||
unsigned int resv15[4];
|
||||
unsigned int dt0rdelays0; /* offset 0x134 */
|
||||
unsigned int dt0dldiff0; /* offset 0x138 */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR CMD control registers.
|
||||
*/
|
||||
struct cmd_control {
|
||||
unsigned long cmd0csratio;
|
||||
unsigned long cmd0csforce;
|
||||
unsigned long cmd0csdelay;
|
||||
unsigned long cmd0iclkout;
|
||||
unsigned long cmd1csratio;
|
||||
unsigned long cmd1csforce;
|
||||
unsigned long cmd1csdelay;
|
||||
unsigned long cmd1iclkout;
|
||||
unsigned long cmd2csratio;
|
||||
unsigned long cmd2csforce;
|
||||
unsigned long cmd2csdelay;
|
||||
unsigned long cmd2iclkout;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR DATA registers.
|
||||
*/
|
||||
struct ddr_data {
|
||||
unsigned long datardsratio0;
|
||||
unsigned long datawdsratio0;
|
||||
unsigned long datawiratio0;
|
||||
unsigned long datagiratio0;
|
||||
unsigned long datafwsratio0;
|
||||
unsigned long datawrsratio0;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure DDR CMD control registers
|
||||
*/
|
||||
void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
|
||||
|
||||
/**
|
||||
* Configure DDR DATA registers
|
||||
*/
|
||||
void config_ddr_data(const struct ddr_data *data, int nr);
|
||||
|
||||
/**
|
||||
* This structure represents the DDR io control on AM33XX devices.
|
||||
*/
|
||||
struct ddr_cmdtctrl {
|
||||
unsigned int cm0ioctl;
|
||||
unsigned int cm1ioctl;
|
||||
unsigned int cm2ioctl;
|
||||
unsigned int resv2[12];
|
||||
unsigned int dt0ioctl;
|
||||
unsigned int dt1ioctl;
|
||||
unsigned int dt2ioctrl;
|
||||
unsigned int dt3ioctrl;
|
||||
unsigned int resv3[4];
|
||||
unsigned int emif_sdram_config_ext;
|
||||
};
|
||||
|
||||
struct ctrl_ioregs {
|
||||
unsigned int cm0ioctl;
|
||||
unsigned int cm1ioctl;
|
||||
unsigned int cm2ioctl;
|
||||
unsigned int dt0ioctl;
|
||||
unsigned int dt1ioctl;
|
||||
unsigned int dt2ioctrl;
|
||||
unsigned int dt3ioctrl;
|
||||
unsigned int emif_sdram_config_ext;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure DDR io control registers
|
||||
*/
|
||||
void config_io_ctrl(const struct ctrl_ioregs *ioregs);
|
||||
|
||||
struct ddr_ctrl {
|
||||
unsigned int ddrioctrl;
|
||||
unsigned int resv1[325];
|
||||
unsigned int ddrckectrl;
|
||||
};
|
||||
|
||||
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
|
||||
const struct ddr_data *data, const struct cmd_control *ctrl,
|
||||
const struct emif_regs *regs, int nr);
|
||||
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
|
||||
|
||||
#endif /* _DDR_DEFS_H */
|
||||
32
u-boot/arch/arm/include/asm/arch-am33xx/gpio.h
Normal file
32
u-boot/arch/arm/include/asm/arch-am33xx/gpio.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _GPIO_AM33xx_H
|
||||
#define _GPIO_AM33xx_H
|
||||
|
||||
#include <asm/omap_gpio.h>
|
||||
|
||||
#ifdef CONFIG_AM43XX
|
||||
#define OMAP_MAX_GPIO 192
|
||||
#else
|
||||
#define OMAP_MAX_GPIO 128
|
||||
#endif
|
||||
|
||||
#define AM33XX_GPIO0_BASE 0x44E07000
|
||||
#define AM33XX_GPIO1_BASE 0x4804C000
|
||||
#define AM33XX_GPIO2_BASE 0x481AC000
|
||||
#define AM33XX_GPIO3_BASE 0x481AE000
|
||||
#define AM33XX_GPIO4_BASE 0x48320000
|
||||
#define AM33XX_GPIO5_BASE 0x48322000
|
||||
|
||||
/* GPIO CTRL register */
|
||||
#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
|
||||
#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0)
|
||||
#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
|
||||
|
||||
/* GPIO OUTPUT ENABLE register */
|
||||
#define GPIO_OE_ENABLE(x) (1 << x)
|
||||
|
||||
/* GPIO SETDATAOUT register */
|
||||
#define GPIO_SETDATAOUT(x) (1 << x)
|
||||
#endif /* _GPIO_AM33xx_H */
|
||||
65
u-boot/arch/arm/include/asm/arch-am33xx/hardware.h
Normal file
65
u-boot/arch/arm/include/asm/arch-am33xx/hardware.h
Normal file
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* hardware.h
|
||||
*
|
||||
* hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_H
|
||||
#define __AM33XX_HARDWARE_H
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch/omap.h>
|
||||
#ifdef CONFIG_AM33XX
|
||||
#include <asm/arch/hardware_am33xx.h>
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#include <asm/arch/hardware_ti816x.h>
|
||||
#elif defined(CONFIG_TI814X)
|
||||
#include <asm/arch/hardware_ti814x.h>
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#include <asm/arch/hardware_am43xx.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Common hardware definitions
|
||||
*/
|
||||
|
||||
/* DM Timer base addresses */
|
||||
#define DM_TIMER0_BASE 0x4802C000
|
||||
#define DM_TIMER1_BASE 0x4802E000
|
||||
#define DM_TIMER2_BASE 0x48040000
|
||||
#define DM_TIMER3_BASE 0x48042000
|
||||
#define DM_TIMER4_BASE 0x48044000
|
||||
#define DM_TIMER5_BASE 0x48046000
|
||||
#define DM_TIMER6_BASE 0x48048000
|
||||
#define DM_TIMER7_BASE 0x4804A000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO0_BASE 0x48032000
|
||||
#define GPIO1_BASE 0x4804C000
|
||||
|
||||
/* BCH Error Location Module */
|
||||
#define ELM_BASE 0x48080000
|
||||
|
||||
/* EMIF Base address */
|
||||
#define EMIF4_0_CFG_BASE 0x4C000000
|
||||
#define EMIF4_1_CFG_BASE 0x4D000000
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_CTRL_ADDR 0x44E10E04
|
||||
#define DDR_CONTROL_BASE_ADDR 0x44E11404
|
||||
|
||||
/* UART */
|
||||
#define DEFAULT_UART_BASE UART0_BASE
|
||||
|
||||
/* GPMC Base address */
|
||||
#define GPMC_BASE 0x50000000
|
||||
|
||||
/* CPSW Config space */
|
||||
#define CPSW_BASE 0x4A100000
|
||||
|
||||
int clk_get(int clk);
|
||||
#endif /* __AM33XX_HARDWARE_H */
|
||||
71
u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
Normal file
71
u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
Normal file
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
* hardware_am33xx.h
|
||||
*
|
||||
* AM33xx hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_AM33XX_H
|
||||
#define __AM33XX_HARDWARE_AM33XX_H
|
||||
|
||||
/* Module base addresses */
|
||||
|
||||
/* UART Base Address */
|
||||
#define UART0_BASE 0x44E09000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO2_BASE 0x481AC000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x44E35000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x44E10000
|
||||
#define CTRL_DEVICE_BASE 0x44E10600
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x44E00000
|
||||
#define CM_PER 0x44E00000
|
||||
#define CM_WKUP 0x44E00400
|
||||
#define CM_DPLL 0x44E00500
|
||||
#define CM_RTC 0x44E00800
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 8)
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x44E10E0C
|
||||
#define VTP1_CTRL_ADDR 0x48140E10
|
||||
#define PRM_DEVICE_INST 0x44E00F00
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x44E12000
|
||||
#define DDR_PHY_DATA_ADDR 0x44E120C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x47C0C800
|
||||
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
|
||||
#define DDR_DATA_REGS_NR 2
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
|
||||
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
|
||||
|
||||
/* CPSW Config space */
|
||||
#define CPSW_MDIO_BASE 0x4A101000
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x44E3E000
|
||||
|
||||
/* OTG */
|
||||
#define USB0_OTG_BASE 0x47401000
|
||||
#define USB1_OTG_BASE 0x47401800
|
||||
|
||||
/* LCD Controller */
|
||||
#define LCD_CNTL_BASE 0x4830E000
|
||||
|
||||
/* PWMSS */
|
||||
#define PWMSS0_BASE 0x48300000
|
||||
#define AM33XX_ECAP0_BASE 0x48300100
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_AM33XX_H */
|
||||
104
u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
Normal file
104
u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
Normal file
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* hardware_am43xx.h
|
||||
*
|
||||
* AM43xx hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __AM43XX_HARDWARE_AM43XX_H
|
||||
#define __AM43XX_HARDWARE_AM43XX_H
|
||||
|
||||
/* Module base addresses */
|
||||
|
||||
/* L3 Fast Configuration Bandwidth Limiter Base Address */
|
||||
#define L3F_CFG_BWLIMITER 0x44005200
|
||||
|
||||
/* UART Base Address */
|
||||
#define UART0_BASE 0x44E09000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO2_BASE 0x481AC000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x44E35000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x44E10000
|
||||
#define CTRL_DEVICE_BASE 0x44E10600
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x44DF0000
|
||||
#define CM_WKUP 0x44DF2800
|
||||
#define CM_PER 0x44DF8800
|
||||
#define CM_DPLL 0x44DF4200
|
||||
#define CM_RTC 0x44DF8500
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x4000)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 4)
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x44E10E0C
|
||||
#define VTP1_CTRL_ADDR 0x48140E10
|
||||
|
||||
/* USB CTRL Base Address */
|
||||
#define USB1_CTRL 0x44e10628
|
||||
#define USB1_CTRL_CM_PWRDN BIT(0)
|
||||
#define USB1_CTRL_OTG_PWRDN BIT(1)
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x44E12000
|
||||
#define DDR_PHY_DATA_ADDR 0x44E120C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x47C0C800
|
||||
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
|
||||
#define DDR_DATA_REGS_NR 2
|
||||
|
||||
/* CPSW Config space */
|
||||
#define CPSW_MDIO_BASE 0x4A101000
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x44E3E000
|
||||
|
||||
/* USB OTG */
|
||||
#define USB_OTG_SS1_BASE 0x48390000
|
||||
#define USB_OTG_SS1_GLUE_BASE 0x48380000
|
||||
#define USB2_PHY1_POWER 0x44E10620
|
||||
|
||||
#define USB_OTG_SS2_BASE 0x483D0000
|
||||
#define USB_OTG_SS2_GLUE_BASE 0x483C0000
|
||||
#define USB2_PHY2_POWER 0x44E10628
|
||||
|
||||
/* USB Clock Control */
|
||||
#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
|
||||
#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
|
||||
#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1)
|
||||
#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
|
||||
|
||||
#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
|
||||
#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
|
||||
#define USBPHYOCPSCP_MODULE_EN (1 << 1)
|
||||
#define CM_DEVICE_INST 0x44df4100
|
||||
#define PRM_DEVICE_INST 0x44df4000
|
||||
|
||||
#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
|
||||
#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
|
||||
|
||||
/* Control status register */
|
||||
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
|
||||
#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
|
||||
#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
|
||||
#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
|
||||
#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
|
||||
#define CTRL_SYSBOOT_15_14_SHIFT 22
|
||||
|
||||
#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
|
||||
#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
|
||||
|
||||
#define NUM_CRYSTAL_FREQ 0x4
|
||||
|
||||
/* EDMA3 Base Address */
|
||||
#define EDMA3_BASE 0x49000000
|
||||
|
||||
#endif /* __AM43XX_HARDWARE_AM43XX_H */
|
||||
61
u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
Normal file
61
u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
Normal file
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* hardware_ti814x.h
|
||||
*
|
||||
* TI814x hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_TI814X_H
|
||||
#define __AM33XX_HARDWARE_TI814X_H
|
||||
|
||||
/* Module base addresses */
|
||||
|
||||
/* UART Base Address */
|
||||
#define UART0_BASE 0x48020000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x481C7000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x48140000
|
||||
#define CTRL_DEVICE_BASE 0x48140600
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x48180000
|
||||
#define CM_PER 0x44E00000
|
||||
#define CM_WKUP 0x44E00400
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 8)
|
||||
|
||||
/* PLL Subsystem Base Address */
|
||||
#define PLL_SUBSYS_BASE 0x481C5000
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x48140E0C
|
||||
#define VTP1_CTRL_ADDR 0x48140E10
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x47C0C400
|
||||
#define DDR_PHY_DATA_ADDR 0x47C0C4C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x47C0C800
|
||||
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
|
||||
#define DDR_DATA_REGS_NR 4
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
|
||||
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
|
||||
|
||||
/* CPSW Config space */
|
||||
#define CPSW_MDIO_BASE 0x4A100800
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x480C0000
|
||||
|
||||
/* OTG */
|
||||
#define USB0_OTG_BASE 0x47401000
|
||||
#define USB1_OTG_BASE 0x47401800
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_TI814X_H */
|
||||
61
u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
Normal file
61
u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
Normal file
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* hardware_ti816x.h
|
||||
*
|
||||
* TI816x hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
||||
* Antoine Tenart, <atenart@adeneo-embedded.com>
|
||||
* Based on TI-PSP-04.00.02.14
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_TI816X_H
|
||||
#define __AM33XX_HARDWARE_TI816X_H
|
||||
|
||||
/* UART */
|
||||
#define UART0_BASE 0x48020000
|
||||
#define UART1_BASE 0x48022000
|
||||
#define UART2_BASE 0x48024000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x480C2000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x48140000
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x48180000
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 8)
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x48198358
|
||||
#define VTP1_CTRL_ADDR 0x4819A358
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x48198000
|
||||
#define DDR_PHY_DATA_ADDR 0x481980C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x4819A000
|
||||
#define DDR_PHY_DATA_ADDR2 0x4819A0C8
|
||||
#define DDR_DATA_REGS_NR 4
|
||||
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE 0x48198000
|
||||
#define DDRPHY_1_CONFIG_BASE 0x4819A000
|
||||
#define DDRPHY_CONFIG_BASE ((emif == 0) ? \
|
||||
DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x480C0000
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_TI816X_H */
|
||||
65
u-boot/arch/arm/include/asm/arch-am33xx/i2c.h
Normal file
65
u-boot/arch/arm/include/asm/arch-am33xx/i2c.h
Normal file
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _I2C_AM33XX_H_
|
||||
#define _I2C_AM33XX_H_
|
||||
|
||||
#define I2C_BASE1 0x44E0B000
|
||||
#define I2C_BASE2 0x4802A000
|
||||
#define I2C_BASE3 0x4819C000
|
||||
#define I2C_BUS_MAX 3
|
||||
|
||||
#define I2C_DEFAULT_BASE I2C_BASE1
|
||||
|
||||
struct i2c {
|
||||
unsigned short revnb_lo; /* 0x00 */
|
||||
unsigned short res1;
|
||||
unsigned short revnb_hi; /* 0x04 */
|
||||
unsigned short res2[5];
|
||||
unsigned short sysc; /* 0x10 */
|
||||
unsigned short res3[9];
|
||||
unsigned short irqstatus_raw; /* 0x24 */
|
||||
unsigned short res4;
|
||||
unsigned short stat; /* 0x28 */
|
||||
unsigned short res5;
|
||||
unsigned short ie; /* 0x2C */
|
||||
unsigned short res6;
|
||||
unsigned short irqenable_clr; /* 0x30 */
|
||||
unsigned short res7;
|
||||
unsigned short iv; /* 0x34 */
|
||||
unsigned short res8[45];
|
||||
unsigned short syss; /* 0x90 */
|
||||
unsigned short res9;
|
||||
unsigned short buf; /* 0x94 */
|
||||
unsigned short res10;
|
||||
unsigned short cnt; /* 0x98 */
|
||||
unsigned short res11;
|
||||
unsigned short data; /* 0x9C */
|
||||
unsigned short res13;
|
||||
unsigned short res14; /* 0xA0 */
|
||||
unsigned short res15;
|
||||
unsigned short con; /* 0xA4 */
|
||||
unsigned short res16;
|
||||
unsigned short oa; /* 0xA8 */
|
||||
unsigned short res17;
|
||||
unsigned short sa; /* 0xAC */
|
||||
unsigned short res18;
|
||||
unsigned short psc; /* 0xB0 */
|
||||
unsigned short res19;
|
||||
unsigned short scll; /* 0xB4 */
|
||||
unsigned short res20;
|
||||
unsigned short sclh; /* 0xB8 */
|
||||
unsigned short res21;
|
||||
unsigned short systest; /* 0xBC */
|
||||
unsigned short res22;
|
||||
unsigned short bufstat; /* 0xC0 */
|
||||
unsigned short res23;
|
||||
};
|
||||
|
||||
#define I2C_IP_CLK 48000000
|
||||
#define I2C_INTERNAL_SAMPLING_CLK 12000000
|
||||
|
||||
#endif /* _I2C_AM33XX_H_ */
|
||||
64
u-boot/arch/arm/include/asm/arch-am33xx/mem.h
Normal file
64
u-boot/arch/arm/include/asm/arch-am33xx/mem.h
Normal file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author
|
||||
* Mansoor Ahamed <mansoor.ahamed@ti.com>
|
||||
*
|
||||
* Initial Code from:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _MEM_H_
|
||||
#define _MEM_H_
|
||||
|
||||
/*
|
||||
* GPMC settings -
|
||||
* Definitions is as per the following format
|
||||
* #define <PART>_GPMC_CONFIG<x> <value>
|
||||
* Where:
|
||||
* PART is the part name e.g. STNOR - Intel Strata Flash
|
||||
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
|
||||
* Value is corresponding value
|
||||
*
|
||||
* For every valid PRCM configuration there should be only one definition of
|
||||
* the same. if values are independent of the board, this definition will be
|
||||
* present in this file if values are dependent on the board, then this should
|
||||
* go into corresponding mem-boardName.h file
|
||||
*
|
||||
* Currently valid part Names are (PART):
|
||||
* M_NAND - Micron NAND
|
||||
* STNOR - STMicrolelctronics M29W128GL
|
||||
*/
|
||||
#define GPMC_SIZE_256M 0x0
|
||||
#define GPMC_SIZE_128M 0x8
|
||||
#define GPMC_SIZE_64M 0xC
|
||||
#define GPMC_SIZE_32M 0xE
|
||||
#define GPMC_SIZE_16M 0xF
|
||||
|
||||
#define M_NAND_GPMC_CONFIG1 0x00000800
|
||||
#define M_NAND_GPMC_CONFIG2 0x001e1e00
|
||||
#define M_NAND_GPMC_CONFIG3 0x001e1e00
|
||||
#define M_NAND_GPMC_CONFIG4 0x16051807
|
||||
#define M_NAND_GPMC_CONFIG5 0x00151e1e
|
||||
#define M_NAND_GPMC_CONFIG6 0x16000f80
|
||||
#define M_NAND_GPMC_CONFIG7 0x00000008
|
||||
|
||||
#define STNOR_GPMC_CONFIG1 0x00001200
|
||||
#define STNOR_GPMC_CONFIG2 0x00101000
|
||||
#define STNOR_GPMC_CONFIG3 0x00030301
|
||||
#define STNOR_GPMC_CONFIG4 0x10041004
|
||||
#define STNOR_GPMC_CONFIG5 0x000C1010
|
||||
#define STNOR_GPMC_CONFIG6 0x08070280
|
||||
#define STNOR_GPMC_CONFIG7 0x00000F48
|
||||
|
||||
/* max number of GPMC Chip Selects */
|
||||
#define GPMC_MAX_CS 8
|
||||
/* max number of GPMC regs */
|
||||
#define GPMC_MAX_REG 7
|
||||
|
||||
#define DBG_MPDB 6
|
||||
|
||||
#endif /* endif _MEM_H_ */
|
||||
35
u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
Normal file
35
u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* mmc_host_def.h
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MMC_HOST_DEF_H
|
||||
#define MMC_HOST_DEF_H
|
||||
|
||||
#include <asm/omap_mmc.h>
|
||||
|
||||
/*
|
||||
* OMAP HSMMC register definitions
|
||||
*/
|
||||
#define OMAP_HSMMC1_BASE 0x48060100
|
||||
#define OMAP_HSMMC2_BASE 0x481D8100
|
||||
|
||||
#if defined(CONFIG_TI814X)
|
||||
#undef MMC_CLOCK_REFERENCE
|
||||
#define MMC_CLOCK_REFERENCE 192 /* MHz */
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#undef MMC_CLOCK_REFERENCE
|
||||
#define MMC_CLOCK_REFERENCE 48 /* MHz */
|
||||
#endif
|
||||
|
||||
#endif /* MMC_HOST_DEF_H */
|
||||
47
u-boot/arch/arm/include/asm/arch-am33xx/mux.h
Normal file
47
u-boot/arch/arm/include/asm/arch-am33xx/mux.h
Normal file
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* mux.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_H_
|
||||
#define _MUX_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_AM33XX
|
||||
#include <asm/arch/mux_am33xx.h>
|
||||
#elif defined(CONFIG_TI814X)
|
||||
#include <asm/arch/mux_ti814x.h>
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#include <asm/arch/mux_ti816x.h>
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#include <asm/arch/mux_am43xx.h>
|
||||
#endif
|
||||
|
||||
struct module_pin_mux {
|
||||
short reg_offset;
|
||||
unsigned int val;
|
||||
};
|
||||
|
||||
/* Pad control register offset */
|
||||
#define PAD_CTRL_BASE 0x800
|
||||
#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\
|
||||
(PAD_CTRL_BASE))->x)
|
||||
|
||||
/*
|
||||
* Configure the pin mux for the module
|
||||
*/
|
||||
void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
|
||||
|
||||
#endif /* endif _MUX_H */
|
||||
247
u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
Normal file
247
u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
Normal file
@@ -0,0 +1,247 @@
|
||||
/*
|
||||
* mux_am33xx.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_AM33XX_H_
|
||||
#define _MUX_AM33XX_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
__raw_writel(value, (CTRL_BASE + offset));
|
||||
|
||||
/* PAD Control Fields */
|
||||
#define SLEWCTRL (0x1 << 6)
|
||||
#define RXACTIVE (0x1 << 5)
|
||||
#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
|
||||
#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
|
||||
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
|
||||
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
|
||||
#define MODE(val) val /* used for Readability */
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int gpmc_ad0;
|
||||
int gpmc_ad1;
|
||||
int gpmc_ad2;
|
||||
int gpmc_ad3;
|
||||
int gpmc_ad4;
|
||||
int gpmc_ad5;
|
||||
int gpmc_ad6;
|
||||
int gpmc_ad7;
|
||||
int gpmc_ad8;
|
||||
int gpmc_ad9;
|
||||
int gpmc_ad10;
|
||||
int gpmc_ad11;
|
||||
int gpmc_ad12;
|
||||
int gpmc_ad13;
|
||||
int gpmc_ad14;
|
||||
int gpmc_ad15;
|
||||
int gpmc_a0;
|
||||
int gpmc_a1;
|
||||
int gpmc_a2;
|
||||
int gpmc_a3;
|
||||
int gpmc_a4;
|
||||
int gpmc_a5;
|
||||
int gpmc_a6;
|
||||
int gpmc_a7;
|
||||
int gpmc_a8;
|
||||
int gpmc_a9;
|
||||
int gpmc_a10;
|
||||
int gpmc_a11;
|
||||
int gpmc_wait0;
|
||||
int gpmc_wpn;
|
||||
int gpmc_be1n;
|
||||
int gpmc_csn0;
|
||||
int gpmc_csn1;
|
||||
int gpmc_csn2;
|
||||
int gpmc_csn3;
|
||||
int gpmc_clk;
|
||||
int gpmc_advn_ale;
|
||||
int gpmc_oen_ren;
|
||||
int gpmc_wen;
|
||||
int gpmc_be0n_cle;
|
||||
int lcd_data0;
|
||||
int lcd_data1;
|
||||
int lcd_data2;
|
||||
int lcd_data3;
|
||||
int lcd_data4;
|
||||
int lcd_data5;
|
||||
int lcd_data6;
|
||||
int lcd_data7;
|
||||
int lcd_data8;
|
||||
int lcd_data9;
|
||||
int lcd_data10;
|
||||
int lcd_data11;
|
||||
int lcd_data12;
|
||||
int lcd_data13;
|
||||
int lcd_data14;
|
||||
int lcd_data15;
|
||||
int lcd_vsync;
|
||||
int lcd_hsync;
|
||||
int lcd_pclk;
|
||||
int lcd_ac_bias_en;
|
||||
int mmc0_dat3;
|
||||
int mmc0_dat2;
|
||||
int mmc0_dat1;
|
||||
int mmc0_dat0;
|
||||
int mmc0_clk;
|
||||
int mmc0_cmd;
|
||||
int mii1_col;
|
||||
int mii1_crs;
|
||||
int mii1_rxerr;
|
||||
int mii1_txen;
|
||||
int mii1_rxdv;
|
||||
int mii1_txd3;
|
||||
int mii1_txd2;
|
||||
int mii1_txd1;
|
||||
int mii1_txd0;
|
||||
int mii1_txclk;
|
||||
int mii1_rxclk;
|
||||
int mii1_rxd3;
|
||||
int mii1_rxd2;
|
||||
int mii1_rxd1;
|
||||
int mii1_rxd0;
|
||||
int rmii1_refclk;
|
||||
int mdio_data;
|
||||
int mdio_clk;
|
||||
int spi0_sclk;
|
||||
int spi0_d0;
|
||||
int spi0_d1;
|
||||
int spi0_cs0;
|
||||
int spi0_cs1;
|
||||
int ecap0_in_pwm0_out;
|
||||
int uart0_ctsn;
|
||||
int uart0_rtsn;
|
||||
int uart0_rxd;
|
||||
int uart0_txd;
|
||||
int uart1_ctsn;
|
||||
int uart1_rtsn;
|
||||
int uart1_rxd;
|
||||
int uart1_txd;
|
||||
int i2c0_sda;
|
||||
int i2c0_scl;
|
||||
int mcasp0_aclkx;
|
||||
int mcasp0_fsx;
|
||||
int mcasp0_axr0;
|
||||
int mcasp0_ahclkr;
|
||||
int mcasp0_aclkr;
|
||||
int mcasp0_fsr;
|
||||
int mcasp0_axr1;
|
||||
int mcasp0_ahclkx;
|
||||
int xdma_event_intr0;
|
||||
int xdma_event_intr1;
|
||||
int nresetin_out;
|
||||
int porz;
|
||||
int nnmi;
|
||||
int osc0_in;
|
||||
int osc0_out;
|
||||
int rsvd1;
|
||||
int tms;
|
||||
int tdi;
|
||||
int tdo;
|
||||
int tck;
|
||||
int ntrst;
|
||||
int emu0;
|
||||
int emu1;
|
||||
int osc1_in;
|
||||
int osc1_out;
|
||||
int pmic_power_en;
|
||||
int rtc_porz;
|
||||
int rsvd2;
|
||||
int ext_wakeup;
|
||||
int enz_kaldo_1p8v;
|
||||
int usb0_dm;
|
||||
int usb0_dp;
|
||||
int usb0_ce;
|
||||
int usb0_id;
|
||||
int usb0_vbus;
|
||||
int usb0_drvvbus;
|
||||
int usb1_dm;
|
||||
int usb1_dp;
|
||||
int usb1_ce;
|
||||
int usb1_id;
|
||||
int usb1_vbus;
|
||||
int usb1_drvvbus;
|
||||
int ddr_resetn;
|
||||
int ddr_csn0;
|
||||
int ddr_cke;
|
||||
int ddr_ck;
|
||||
int ddr_nck;
|
||||
int ddr_casn;
|
||||
int ddr_rasn;
|
||||
int ddr_wen;
|
||||
int ddr_ba0;
|
||||
int ddr_ba1;
|
||||
int ddr_ba2;
|
||||
int ddr_a0;
|
||||
int ddr_a1;
|
||||
int ddr_a2;
|
||||
int ddr_a3;
|
||||
int ddr_a4;
|
||||
int ddr_a5;
|
||||
int ddr_a6;
|
||||
int ddr_a7;
|
||||
int ddr_a8;
|
||||
int ddr_a9;
|
||||
int ddr_a10;
|
||||
int ddr_a11;
|
||||
int ddr_a12;
|
||||
int ddr_a13;
|
||||
int ddr_a14;
|
||||
int ddr_a15;
|
||||
int ddr_odt;
|
||||
int ddr_d0;
|
||||
int ddr_d1;
|
||||
int ddr_d2;
|
||||
int ddr_d3;
|
||||
int ddr_d4;
|
||||
int ddr_d5;
|
||||
int ddr_d6;
|
||||
int ddr_d7;
|
||||
int ddr_d8;
|
||||
int ddr_d9;
|
||||
int ddr_d10;
|
||||
int ddr_d11;
|
||||
int ddr_d12;
|
||||
int ddr_d13;
|
||||
int ddr_d14;
|
||||
int ddr_d15;
|
||||
int ddr_dqm0;
|
||||
int ddr_dqm1;
|
||||
int ddr_dqs0;
|
||||
int ddr_dqsn0;
|
||||
int ddr_dqs1;
|
||||
int ddr_dqsn1;
|
||||
int ddr_vref;
|
||||
int ddr_vtp;
|
||||
int ddr_strben0;
|
||||
int ddr_strben1;
|
||||
int ain7;
|
||||
int ain6;
|
||||
int ain5;
|
||||
int ain4;
|
||||
int ain3;
|
||||
int ain2;
|
||||
int ain1;
|
||||
int ain0;
|
||||
int vrefp;
|
||||
int vrefn;
|
||||
};
|
||||
|
||||
#endif /* endif _MUX_AM33XX_H_ */
|
||||
212
u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
Normal file
212
u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
Normal file
@@ -0,0 +1,212 @@
|
||||
/*
|
||||
* mux_am43xx.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _MUX_AM43XX_H_
|
||||
#define _MUX_AM43XX_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
__raw_writel(value, (CTRL_BASE + offset));
|
||||
|
||||
/* PAD Control Fields */
|
||||
#define SLEWCTRL (0x1 << 19)
|
||||
#define RXACTIVE (0x1 << 18)
|
||||
#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */
|
||||
#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */
|
||||
#define PULLUDEN (0x0 << 16) /* Pull up/down enable */
|
||||
#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */
|
||||
#define MODE(val) val /* used for Readability */
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int gpmc_ad0;
|
||||
int gpmc_ad1;
|
||||
int gpmc_ad2;
|
||||
int gpmc_ad3;
|
||||
int gpmc_ad4;
|
||||
int gpmc_ad5;
|
||||
int gpmc_ad6;
|
||||
int gpmc_ad7;
|
||||
int gpmc_ad8;
|
||||
int gpmc_ad9;
|
||||
int gpmc_ad10;
|
||||
int gpmc_ad11;
|
||||
int gpmc_ad12;
|
||||
int gpmc_ad13;
|
||||
int gpmc_ad14;
|
||||
int gpmc_ad15;
|
||||
int gpmc_a0;
|
||||
int gpmc_a1;
|
||||
int gpmc_a2;
|
||||
int gpmc_a3;
|
||||
int gpmc_a4;
|
||||
int gpmc_a5;
|
||||
int gpmc_a6;
|
||||
int gpmc_a7;
|
||||
int gpmc_a8;
|
||||
int gpmc_a9;
|
||||
int gpmc_a10;
|
||||
int gpmc_a11;
|
||||
int gpmc_wait0;
|
||||
int gpmc_wpn;
|
||||
int gpmc_be1n;
|
||||
int gpmc_csn0;
|
||||
int gpmc_csn1;
|
||||
int gpmc_csn2;
|
||||
int gpmc_csn3;
|
||||
int gpmc_clk;
|
||||
int gpmc_advn_ale;
|
||||
int gpmc_oen_ren;
|
||||
int gpmc_wen;
|
||||
int gpmc_be0n_cle;
|
||||
int lcd_data0;
|
||||
int lcd_data1;
|
||||
int lcd_data2;
|
||||
int lcd_data3;
|
||||
int lcd_data4;
|
||||
int lcd_data5;
|
||||
int lcd_data6;
|
||||
int lcd_data7;
|
||||
int lcd_data8;
|
||||
int lcd_data9;
|
||||
int lcd_data10;
|
||||
int lcd_data11;
|
||||
int lcd_data12;
|
||||
int lcd_data13;
|
||||
int lcd_data14;
|
||||
int lcd_data15;
|
||||
int lcd_vsync;
|
||||
int lcd_hsync;
|
||||
int lcd_pclk;
|
||||
int lcd_ac_bias_en;
|
||||
int mmc0_dat3;
|
||||
int mmc0_dat2;
|
||||
int mmc0_dat1;
|
||||
int mmc0_dat0;
|
||||
int mmc0_clk;
|
||||
int mmc0_cmd;
|
||||
int mii1_col;
|
||||
int mii1_crs;
|
||||
int mii1_rxerr;
|
||||
int mii1_txen;
|
||||
int mii1_rxdv;
|
||||
int mii1_txd3;
|
||||
int mii1_txd2;
|
||||
int mii1_txd1;
|
||||
int mii1_txd0;
|
||||
int mii1_txclk;
|
||||
int mii1_rxclk;
|
||||
int mii1_rxd3;
|
||||
int mii1_rxd2;
|
||||
int mii1_rxd1;
|
||||
int mii1_rxd0;
|
||||
int rmii1_refclk;
|
||||
int mdio_data;
|
||||
int mdio_clk;
|
||||
int spi0_sclk;
|
||||
int spi0_d0;
|
||||
int spi0_d1;
|
||||
int spi0_cs0;
|
||||
int spi0_cs1;
|
||||
int ecap0_in_pwm0_out;
|
||||
int uart0_ctsn;
|
||||
int uart0_rtsn;
|
||||
int uart0_rxd;
|
||||
int uart0_txd;
|
||||
int uart1_ctsn;
|
||||
int uart1_rtsn;
|
||||
int uart1_rxd;
|
||||
int uart1_txd;
|
||||
int i2c0_sda;
|
||||
int i2c0_scl;
|
||||
int mcasp0_aclkx;
|
||||
int mcasp0_fsx;
|
||||
int mcasp0_axr0;
|
||||
int mcasp0_ahclkr;
|
||||
int mcasp0_aclkr;
|
||||
int mcasp0_fsr;
|
||||
int mcasp0_axr1;
|
||||
int mcasp0_ahclkx;
|
||||
int cam0_hd;
|
||||
int cam0_vd;
|
||||
int cam0_field;
|
||||
int cam0_wen;
|
||||
int cam0_pclk;
|
||||
int cam0_data8;
|
||||
int cam0_data9;
|
||||
int cam1_data9;
|
||||
int cam1_data8;
|
||||
int cam1_hd;
|
||||
int cam1_vd;
|
||||
int cam1_pclk;
|
||||
int cam1_field;
|
||||
int cam1_wen;
|
||||
int cam1_data0;
|
||||
int cam1_data1;
|
||||
int cam1_data2;
|
||||
int cam1_data3;
|
||||
int cam1_data4;
|
||||
int cam1_data5;
|
||||
int cam1_data6;
|
||||
int cam1_data7;
|
||||
int cam0_data0;
|
||||
int cam0_data1;
|
||||
int cam0_data2;
|
||||
int cam0_data3;
|
||||
int cam0_data4;
|
||||
int cam0_data5;
|
||||
int cam0_data6;
|
||||
int cam0_data7;
|
||||
int uart3_rxd;
|
||||
int uart3_txd;
|
||||
int uart3_ctsn;
|
||||
int uart3_rtsn;
|
||||
int gpio5_8;
|
||||
int gpio5_9;
|
||||
int gpio5_10;
|
||||
int gpio5_11;
|
||||
int gpio5_12;
|
||||
int gpio5_13;
|
||||
int spi4_sclk;
|
||||
int spi4_d0;
|
||||
int spi4_d1;
|
||||
int spi4_cs0;
|
||||
int spi2_sclk;
|
||||
int spi2_d0;
|
||||
int spi2_d1;
|
||||
int spi2_cs0;
|
||||
int xdma_evt_intr0;
|
||||
int xdma_evt_intr1;
|
||||
int clkreq;
|
||||
int nresetin_out;
|
||||
int rsvd1;
|
||||
int nnmi;
|
||||
int rsvd2;
|
||||
int rsvd3;
|
||||
int tms;
|
||||
int tdi;
|
||||
int tdo;
|
||||
int tck;
|
||||
int ntrst;
|
||||
int emu0;
|
||||
int emu1;
|
||||
int osc1_in;
|
||||
int osc1_out;
|
||||
int rtc_porz;
|
||||
int ext_wakeup0;
|
||||
int pmic_power_en0;
|
||||
int usb0_drvvbus;
|
||||
int usb1_drvvbus;
|
||||
};
|
||||
|
||||
#endif /* _MUX_AM43XX_H_ */
|
||||
311
u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h
Normal file
311
u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h
Normal file
@@ -0,0 +1,311 @@
|
||||
/*
|
||||
* mux_ti814x.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_TI814X_H_
|
||||
#define _MUX_TI814X_H_
|
||||
|
||||
/* PAD Control Fields */
|
||||
#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */
|
||||
#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */
|
||||
#define PULLUDEN (0x0 << 16) /* Pull up enabled */
|
||||
#define PULLUDDIS (0x1 << 16) /* Pull up disabled */
|
||||
#define MODE(val) val /* used for Readability */
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
{ \
|
||||
int tmp; \
|
||||
tmp = __raw_readl(CTRL_BASE + offset); \
|
||||
tmp &= PINCNTL_RSV_MSK; \
|
||||
__raw_writel(tmp | value, (CTRL_BASE + offset));\
|
||||
}
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int pincntl1;
|
||||
int pincntl2;
|
||||
int pincntl3;
|
||||
int pincntl4;
|
||||
int pincntl5;
|
||||
int pincntl6;
|
||||
int pincntl7;
|
||||
int pincntl8;
|
||||
int pincntl9;
|
||||
int pincntl10;
|
||||
int pincntl11;
|
||||
int pincntl12;
|
||||
int pincntl13;
|
||||
int pincntl14;
|
||||
int pincntl15;
|
||||
int pincntl16;
|
||||
int pincntl17;
|
||||
int pincntl18;
|
||||
int pincntl19;
|
||||
int pincntl20;
|
||||
int pincntl21;
|
||||
int pincntl22;
|
||||
int pincntl23;
|
||||
int pincntl24;
|
||||
int pincntl25;
|
||||
int pincntl26;
|
||||
int pincntl27;
|
||||
int pincntl28;
|
||||
int pincntl29;
|
||||
int pincntl30;
|
||||
int pincntl31;
|
||||
int pincntl32;
|
||||
int pincntl33;
|
||||
int pincntl34;
|
||||
int pincntl35;
|
||||
int pincntl36;
|
||||
int pincntl37;
|
||||
int pincntl38;
|
||||
int pincntl39;
|
||||
int pincntl40;
|
||||
int pincntl41;
|
||||
int pincntl42;
|
||||
int pincntl43;
|
||||
int pincntl44;
|
||||
int pincntl45;
|
||||
int pincntl46;
|
||||
int pincntl47;
|
||||
int pincntl48;
|
||||
int pincntl49;
|
||||
int pincntl50;
|
||||
int pincntl51;
|
||||
int pincntl52;
|
||||
int pincntl53;
|
||||
int pincntl54;
|
||||
int pincntl55;
|
||||
int pincntl56;
|
||||
int pincntl57;
|
||||
int pincntl58;
|
||||
int pincntl59;
|
||||
int pincntl60;
|
||||
int pincntl61;
|
||||
int pincntl62;
|
||||
int pincntl63;
|
||||
int pincntl64;
|
||||
int pincntl65;
|
||||
int pincntl66;
|
||||
int pincntl67;
|
||||
int pincntl68;
|
||||
int pincntl69;
|
||||
int pincntl70;
|
||||
int pincntl71;
|
||||
int pincntl72;
|
||||
int pincntl73;
|
||||
int pincntl74;
|
||||
int pincntl75;
|
||||
int pincntl76;
|
||||
int pincntl77;
|
||||
int pincntl78;
|
||||
int pincntl79;
|
||||
int pincntl80;
|
||||
int pincntl81;
|
||||
int pincntl82;
|
||||
int pincntl83;
|
||||
int pincntl84;
|
||||
int pincntl85;
|
||||
int pincntl86;
|
||||
int pincntl87;
|
||||
int pincntl88;
|
||||
int pincntl89;
|
||||
int pincntl90;
|
||||
int pincntl91;
|
||||
int pincntl92;
|
||||
int pincntl93;
|
||||
int pincntl94;
|
||||
int pincntl95;
|
||||
int pincntl96;
|
||||
int pincntl97;
|
||||
int pincntl98;
|
||||
int pincntl99;
|
||||
int pincntl100;
|
||||
int pincntl101;
|
||||
int pincntl102;
|
||||
int pincntl103;
|
||||
int pincntl104;
|
||||
int pincntl105;
|
||||
int pincntl106;
|
||||
int pincntl107;
|
||||
int pincntl108;
|
||||
int pincntl109;
|
||||
int pincntl110;
|
||||
int pincntl111;
|
||||
int pincntl112;
|
||||
int pincntl113;
|
||||
int pincntl114;
|
||||
int pincntl115;
|
||||
int pincntl116;
|
||||
int pincntl117;
|
||||
int pincntl118;
|
||||
int pincntl119;
|
||||
int pincntl120;
|
||||
int pincntl121;
|
||||
int pincntl122;
|
||||
int pincntl123;
|
||||
int pincntl124;
|
||||
int pincntl125;
|
||||
int pincntl126;
|
||||
int pincntl127;
|
||||
int pincntl128;
|
||||
int pincntl129;
|
||||
int pincntl130;
|
||||
int pincntl131;
|
||||
int pincntl132;
|
||||
int pincntl133;
|
||||
int pincntl134;
|
||||
int pincntl135;
|
||||
int pincntl136;
|
||||
int pincntl137;
|
||||
int pincntl138;
|
||||
int pincntl139;
|
||||
int pincntl140;
|
||||
int pincntl141;
|
||||
int pincntl142;
|
||||
int pincntl143;
|
||||
int pincntl144;
|
||||
int pincntl145;
|
||||
int pincntl146;
|
||||
int pincntl147;
|
||||
int pincntl148;
|
||||
int pincntl149;
|
||||
int pincntl150;
|
||||
int pincntl151;
|
||||
int pincntl152;
|
||||
int pincntl153;
|
||||
int pincntl154;
|
||||
int pincntl155;
|
||||
int pincntl156;
|
||||
int pincntl157;
|
||||
int pincntl158;
|
||||
int pincntl159;
|
||||
int pincntl160;
|
||||
int pincntl161;
|
||||
int pincntl162;
|
||||
int pincntl163;
|
||||
int pincntl164;
|
||||
int pincntl165;
|
||||
int pincntl166;
|
||||
int pincntl167;
|
||||
int pincntl168;
|
||||
int pincntl169;
|
||||
int pincntl170;
|
||||
int pincntl171;
|
||||
int pincntl172;
|
||||
int pincntl173;
|
||||
int pincntl174;
|
||||
int pincntl175;
|
||||
int pincntl176;
|
||||
int pincntl177;
|
||||
int pincntl178;
|
||||
int pincntl179;
|
||||
int pincntl180;
|
||||
int pincntl181;
|
||||
int pincntl182;
|
||||
int pincntl183;
|
||||
int pincntl184;
|
||||
int pincntl185;
|
||||
int pincntl186;
|
||||
int pincntl187;
|
||||
int pincntl188;
|
||||
int pincntl189;
|
||||
int pincntl190;
|
||||
int pincntl191;
|
||||
int pincntl192;
|
||||
int pincntl193;
|
||||
int pincntl194;
|
||||
int pincntl195;
|
||||
int pincntl196;
|
||||
int pincntl197;
|
||||
int pincntl198;
|
||||
int pincntl199;
|
||||
int pincntl200;
|
||||
int pincntl201;
|
||||
int pincntl202;
|
||||
int pincntl203;
|
||||
int pincntl204;
|
||||
int pincntl205;
|
||||
int pincntl206;
|
||||
int pincntl207;
|
||||
int pincntl208;
|
||||
int pincntl209;
|
||||
int pincntl210;
|
||||
int pincntl211;
|
||||
int pincntl212;
|
||||
int pincntl213;
|
||||
int pincntl214;
|
||||
int pincntl215;
|
||||
int pincntl216;
|
||||
int pincntl217;
|
||||
int pincntl218;
|
||||
int pincntl219;
|
||||
int pincntl220;
|
||||
int pincntl221;
|
||||
int pincntl222;
|
||||
int pincntl223;
|
||||
int pincntl224;
|
||||
int pincntl225;
|
||||
int pincntl226;
|
||||
int pincntl227;
|
||||
int pincntl228;
|
||||
int pincntl229;
|
||||
int pincntl230;
|
||||
int pincntl231;
|
||||
int pincntl232;
|
||||
int pincntl233;
|
||||
int pincntl234;
|
||||
int pincntl235;
|
||||
int pincntl236;
|
||||
int pincntl237;
|
||||
int pincntl238;
|
||||
int pincntl239;
|
||||
int pincntl240;
|
||||
int pincntl241;
|
||||
int pincntl242;
|
||||
int pincntl243;
|
||||
int pincntl244;
|
||||
int pincntl245;
|
||||
int pincntl246;
|
||||
int pincntl247;
|
||||
int pincntl248;
|
||||
int pincntl249;
|
||||
int pincntl250;
|
||||
int pincntl251;
|
||||
int pincntl252;
|
||||
int pincntl253;
|
||||
int pincntl254;
|
||||
int pincntl255;
|
||||
int pincntl256;
|
||||
int pincntl257;
|
||||
int pincntl258;
|
||||
int pincntl259;
|
||||
int pincntl260;
|
||||
int pincntl261;
|
||||
int pincntl262;
|
||||
int pincntl263;
|
||||
int pincntl264;
|
||||
int pincntl265;
|
||||
int pincntl266;
|
||||
int pincntl267;
|
||||
int pincntl268;
|
||||
int pincntl269;
|
||||
int pincntl270;
|
||||
};
|
||||
|
||||
#endif /* endif _MUX_TI814X_H_ */
|
||||
363
u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
Normal file
363
u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
Normal file
@@ -0,0 +1,363 @@
|
||||
/*
|
||||
* mux_ti816x.h
|
||||
*
|
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
||||
* Antoine Tenart, <atenart@adeneo-embedded.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_TI816X_H_
|
||||
#define _MUX_TI816X_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
__raw_writel(value, (CTRL_BASE + offset));
|
||||
|
||||
#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
|
||||
#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
|
||||
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
|
||||
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
|
||||
#define MODE(val) (val) /* used for Readability */
|
||||
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int pincntl1;
|
||||
int pincntl2;
|
||||
int pincntl3;
|
||||
int pincntl4;
|
||||
int pincntl5;
|
||||
int pincntl6;
|
||||
int pincntl7;
|
||||
int pincntl8;
|
||||
int pincntl9;
|
||||
int pincntl10;
|
||||
int pincntl11;
|
||||
int pincntl12;
|
||||
int pincntl13;
|
||||
int pincntl14;
|
||||
int pincntl15;
|
||||
int pincntl16;
|
||||
int pincntl17;
|
||||
int pincntl18;
|
||||
int pincntl19;
|
||||
int pincntl20;
|
||||
int pincntl21;
|
||||
int pincntl22;
|
||||
int pincntl23;
|
||||
int pincntl24;
|
||||
int pincntl25;
|
||||
int pincntl26;
|
||||
int pincntl27;
|
||||
int pincntl28;
|
||||
int pincntl29;
|
||||
int pincntl30;
|
||||
int pincntl31;
|
||||
int pincntl32;
|
||||
int pincntl33;
|
||||
int pincntl34;
|
||||
int pincntl35;
|
||||
int pincntl36;
|
||||
int pincntl37;
|
||||
int pincntl38;
|
||||
int pincntl39;
|
||||
int pincntl40;
|
||||
int pincntl41;
|
||||
int pincntl42;
|
||||
int pincntl43;
|
||||
int pincntl44;
|
||||
int pincntl45;
|
||||
int pincntl46;
|
||||
int pincntl47;
|
||||
int pincntl48;
|
||||
int pincntl49;
|
||||
int pincntl50;
|
||||
int pincntl51;
|
||||
int pincntl52;
|
||||
int pincntl53;
|
||||
int pincntl54;
|
||||
int pincntl55;
|
||||
int pincntl56;
|
||||
int pincntl57;
|
||||
int pincntl58;
|
||||
int pincntl59;
|
||||
int pincntl60;
|
||||
int pincntl61;
|
||||
int pincntl62;
|
||||
int pincntl63;
|
||||
int pincntl64;
|
||||
int pincntl65;
|
||||
int pincntl66;
|
||||
int pincntl67;
|
||||
int pincntl68;
|
||||
int pincntl69;
|
||||
int pincntl70;
|
||||
int pincntl71;
|
||||
int pincntl72;
|
||||
int pincntl73;
|
||||
int pincntl74;
|
||||
int pincntl75;
|
||||
int pincntl76;
|
||||
int pincntl77;
|
||||
int pincntl78;
|
||||
int pincntl79;
|
||||
int pincntl80;
|
||||
int pincntl81;
|
||||
int pincntl82;
|
||||
int pincntl83;
|
||||
int pincntl84;
|
||||
int pincntl85;
|
||||
int pincntl86;
|
||||
int pincntl87;
|
||||
int pincntl88;
|
||||
int pincntl89;
|
||||
int pincntl90;
|
||||
int pincntl91;
|
||||
int pincntl92;
|
||||
int pincntl93;
|
||||
int pincntl94;
|
||||
int pincntl95;
|
||||
int pincntl96;
|
||||
int pincntl97;
|
||||
int pincntl98;
|
||||
int pincntl99;
|
||||
int pincntl100;
|
||||
int pincntl101;
|
||||
int pincntl102;
|
||||
int pincntl103;
|
||||
int pincntl104;
|
||||
int pincntl105;
|
||||
int pincntl106;
|
||||
int pincntl107;
|
||||
int pincntl108;
|
||||
int pincntl109;
|
||||
int pincntl110;
|
||||
int pincntl111;
|
||||
int pincntl112;
|
||||
int pincntl113;
|
||||
int pincntl114;
|
||||
int pincntl115;
|
||||
int pincntl116;
|
||||
int pincntl117;
|
||||
int pincntl118;
|
||||
int pincntl119;
|
||||
int pincntl120;
|
||||
int pincntl121;
|
||||
int pincntl122;
|
||||
int pincntl123;
|
||||
int pincntl124;
|
||||
int pincntl125;
|
||||
int pincntl126;
|
||||
int pincntl127;
|
||||
int pincntl128;
|
||||
int pincntl129;
|
||||
int pincntl130;
|
||||
int pincntl131;
|
||||
int pincntl132;
|
||||
int pincntl133;
|
||||
int pincntl134;
|
||||
int pincntl135;
|
||||
int pincntl136;
|
||||
int pincntl137;
|
||||
int pincntl138;
|
||||
int pincntl139;
|
||||
int pincntl140;
|
||||
int pincntl141;
|
||||
int pincntl142;
|
||||
int pincntl143;
|
||||
int pincntl144;
|
||||
int pincntl145;
|
||||
int pincntl146;
|
||||
int pincntl147;
|
||||
int pincntl148;
|
||||
int pincntl149;
|
||||
int pincntl150;
|
||||
int pincntl151;
|
||||
int pincntl152;
|
||||
int pincntl153;
|
||||
int pincntl154;
|
||||
int pincntl155;
|
||||
int pincntl156;
|
||||
int pincntl157;
|
||||
int pincntl158;
|
||||
int pincntl159;
|
||||
int pincntl160;
|
||||
int pincntl161;
|
||||
int pincntl162;
|
||||
int pincntl163;
|
||||
int pincntl164;
|
||||
int pincntl165;
|
||||
int pincntl166;
|
||||
int pincntl167;
|
||||
int pincntl168;
|
||||
int pincntl169;
|
||||
int pincntl170;
|
||||
int pincntl171;
|
||||
int pincntl172;
|
||||
int pincntl173;
|
||||
int pincntl174;
|
||||
int pincntl175;
|
||||
int pincntl176;
|
||||
int pincntl177;
|
||||
int pincntl178;
|
||||
int pincntl179;
|
||||
int pincntl180;
|
||||
int pincntl181;
|
||||
int pincntl182;
|
||||
int pincntl183;
|
||||
int pincntl184;
|
||||
int pincntl185;
|
||||
int pincntl186;
|
||||
int pincntl187;
|
||||
int pincntl188;
|
||||
int pincntl189;
|
||||
int pincntl190;
|
||||
int pincntl191;
|
||||
int pincntl192;
|
||||
int pincntl193;
|
||||
int pincntl194;
|
||||
int pincntl195;
|
||||
int pincntl196;
|
||||
int pincntl197;
|
||||
int pincntl198;
|
||||
int pincntl199;
|
||||
int pincntl200;
|
||||
int pincntl201;
|
||||
int pincntl202;
|
||||
int pincntl203;
|
||||
int pincntl204;
|
||||
int pincntl205;
|
||||
int pincntl206;
|
||||
int pincntl207;
|
||||
int pincntl208;
|
||||
int pincntl209;
|
||||
int pincntl210;
|
||||
int pincntl211;
|
||||
int pincntl212;
|
||||
int pincntl213;
|
||||
int pincntl214;
|
||||
int pincntl215;
|
||||
int pincntl216;
|
||||
int pincntl217;
|
||||
int pincntl218;
|
||||
int pincntl219;
|
||||
int pincntl220;
|
||||
int pincntl221;
|
||||
int pincntl222;
|
||||
int pincntl223;
|
||||
int pincntl224;
|
||||
int pincntl225;
|
||||
int pincntl226;
|
||||
int pincntl227;
|
||||
int pincntl228;
|
||||
int pincntl229;
|
||||
int pincntl230;
|
||||
int pincntl231;
|
||||
int pincntl232;
|
||||
int pincntl233;
|
||||
int pincntl234;
|
||||
int pincntl235;
|
||||
int pincntl236;
|
||||
int pincntl237;
|
||||
int pincntl238;
|
||||
int pincntl239;
|
||||
int pincntl240;
|
||||
int pincntl241;
|
||||
int pincntl242;
|
||||
int pincntl243;
|
||||
int pincntl244;
|
||||
int pincntl245;
|
||||
int pincntl246;
|
||||
int pincntl247;
|
||||
int pincntl248;
|
||||
int pincntl249;
|
||||
int pincntl250;
|
||||
int pincntl251;
|
||||
int pincntl252;
|
||||
int pincntl253;
|
||||
int pincntl254;
|
||||
int pincntl255;
|
||||
int pincntl256;
|
||||
int pincntl257;
|
||||
int pincntl258;
|
||||
int pincntl259;
|
||||
int pincntl260;
|
||||
int pincntl261;
|
||||
int pincntl262;
|
||||
int pincntl263;
|
||||
int pincntl264;
|
||||
int pincntl265;
|
||||
int pincntl266;
|
||||
int pincntl267;
|
||||
int pincntl268;
|
||||
int pincntl269;
|
||||
int pincntl270;
|
||||
int pincntl271;
|
||||
int pincntl272;
|
||||
int pincntl273;
|
||||
int pincntl274;
|
||||
int pincntl275;
|
||||
int pincntl276;
|
||||
int pincntl277;
|
||||
int pincntl278;
|
||||
int pincntl279;
|
||||
int pincntl280;
|
||||
int pincntl281;
|
||||
int pincntl282;
|
||||
int pincntl283;
|
||||
int pincntl284;
|
||||
int pincntl285;
|
||||
int pincntl286;
|
||||
int pincntl287;
|
||||
int pincntl288;
|
||||
int pincntl289;
|
||||
int pincntl290;
|
||||
int pincntl291;
|
||||
int pincntl292;
|
||||
int pincntl293;
|
||||
int pincntl294;
|
||||
int pincntl295;
|
||||
int pincntl296;
|
||||
int pincntl297;
|
||||
int pincntl298;
|
||||
int pincntl299;
|
||||
int pincntl300;
|
||||
int pincntl301;
|
||||
int pincntl302;
|
||||
int pincntl303;
|
||||
int pincntl304;
|
||||
int pincntl305;
|
||||
int pincntl306;
|
||||
int pincntl307;
|
||||
int pincntl308;
|
||||
int pincntl309;
|
||||
int pincntl310;
|
||||
int pincntl311;
|
||||
int pincntl312;
|
||||
int pincntl313;
|
||||
int pincntl314;
|
||||
int pincntl315;
|
||||
int pincntl316;
|
||||
int pincntl317;
|
||||
int pincntl318;
|
||||
int pincntl319;
|
||||
int pincntl320;
|
||||
int pincntl321;
|
||||
int pincntl322;
|
||||
int pincntl323;
|
||||
};
|
||||
|
||||
#endif /* endif _MUX_TI816X_H_ */
|
||||
47
u-boot/arch/arm/include/asm/arch-am33xx/omap.h
Normal file
47
u-boot/arch/arm/include/asm/arch-am33xx/omap.h
Normal file
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* omap.h
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Author:
|
||||
* Chandan Nath <chandan.nath@ti.com>
|
||||
*
|
||||
* Derived from OMAP4 work by
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _OMAP_H_
|
||||
#define _OMAP_H_
|
||||
|
||||
#ifdef CONFIG_AM33XX
|
||||
#define NON_SECURE_SRAM_START 0x402F0400
|
||||
#define NON_SECURE_SRAM_END 0x40310000
|
||||
#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800
|
||||
#elif defined(CONFIG_TI81XX)
|
||||
#define NON_SECURE_SRAM_START 0x40300000
|
||||
#define NON_SECURE_SRAM_END 0x40320000
|
||||
#define SRAM_SCRATCH_SPACE_ADDR 0x4031B800
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#define NON_SECURE_SRAM_START 0x402F0400
|
||||
#define NON_SECURE_SRAM_END 0x40340000
|
||||
#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
|
||||
#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
|
||||
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
|
||||
#define AM4372_BOARD_VERSION_START SRAM_SCRATCH_SPACE_ADDR + 0xD
|
||||
#define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14
|
||||
#define QSPI_BASE 0x47900000
|
||||
#endif
|
||||
|
||||
/* Boot parameters */
|
||||
#ifndef __ASSEMBLY__
|
||||
struct omap_boot_parameters {
|
||||
unsigned int reserved;
|
||||
unsigned int boot_device_descriptor;
|
||||
unsigned char boot_device;
|
||||
unsigned char reset_reason;
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif
|
||||
72
u-boot/arch/arm/include/asm/arch-am33xx/spl.h
Normal file
72
u-boot/arch/arm/include/asm/arch-am33xx/spl.h
Normal file
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_NONE 0x00
|
||||
#define BOOT_DEVICE_MMC2_2 0xFF
|
||||
|
||||
#if defined(CONFIG_TI814X)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x05
|
||||
#define BOOT_DEVICE_NAND_I2C 0x06
|
||||
#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */
|
||||
#define BOOT_DEVICE_MMC1 0x09
|
||||
#define BOOT_DEVICE_SPI 0x15
|
||||
#define BOOT_DEVICE_UART 0x41
|
||||
#define BOOT_DEVICE_USBETH 0x44
|
||||
#define BOOT_DEVICE_CPGMAC 0x46
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x03
|
||||
#define BOOT_DEVICE_ONENAD 0x04
|
||||
#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */
|
||||
#define BOOT_DEVICE_MMC1 0x06
|
||||
#define BOOT_DEVICE_UART 0x43
|
||||
#define BOOT_DEVICE_USB 0x45
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
|
||||
#elif defined(CONFIG_AM33XX)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x05
|
||||
#define BOOT_DEVICE_NAND_I2C 0x06
|
||||
#define BOOT_DEVICE_MMC1 0x08
|
||||
#define BOOT_DEVICE_MMC2 0x09
|
||||
#define BOOT_DEVICE_SPI 0x0B
|
||||
#define BOOT_DEVICE_UART 0x41
|
||||
#define BOOT_DEVICE_USBETH 0x44
|
||||
#define BOOT_DEVICE_CPGMAC 0x46
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#define BOOT_DEVICE_NOR 0x01
|
||||
#define BOOT_DEVICE_NAND 0x05
|
||||
#define BOOT_DEVICE_MMC1 0x07
|
||||
#define BOOT_DEVICE_MMC2 0x08
|
||||
#define BOOT_DEVICE_SPI 0x0A
|
||||
#define BOOT_DEVICE_USB 0x0D
|
||||
#define BOOT_DEVICE_UART 0x41
|
||||
#define BOOT_DEVICE_USBETH 0x45
|
||||
#define BOOT_DEVICE_CPGMAC 0x47
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
|
||||
#ifdef CONFIG_SPL_USB_SUPPORT
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB
|
||||
#else
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
47
u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h
Normal file
47
u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h
Normal file
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* sys_proto.h
|
||||
*
|
||||
* System information header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
#include <linux/mtd/omap_gpmc.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
u32 get_cpu_rev(void);
|
||||
u32 get_sysboot_value(void);
|
||||
|
||||
extern struct ctrl_stat *cstat;
|
||||
u32 get_device_type(void);
|
||||
void save_omap_boot_params(void);
|
||||
void setup_clocks_for_console(void);
|
||||
void mpu_pll_config_val(int mpull_m);
|
||||
void ddr_pll_config(unsigned int ddrpll_M);
|
||||
|
||||
void sdelay(unsigned long);
|
||||
|
||||
struct gpmc_cs;
|
||||
void gpmc_init(void);
|
||||
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
|
||||
u32 size);
|
||||
void omap_nand_switch_ecc(uint32_t, uint32_t);
|
||||
|
||||
void set_uart_mux_conf(void);
|
||||
void set_mux_conf_regs(void);
|
||||
void sdram_init(void);
|
||||
u32 wait_on_value(u32, u32, void *, u32);
|
||||
#ifdef CONFIG_NOR_BOOT
|
||||
void enable_norboot_pin_mux(void);
|
||||
#endif
|
||||
void am33xx_spl_board_init(void);
|
||||
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
|
||||
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
|
||||
#endif
|
||||
|
||||
void enable_usb_clocks(int index);
|
||||
void disable_usb_clocks(int index);
|
||||
60
u-boot/arch/arm/include/asm/arch-armada100/armada100.h
Normal file
60
u-boot/arch/arm/include/asm/arch-armada100/armada100.h
Normal file
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
* Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_ARMADA100_H
|
||||
#define _ASM_ARCH_ARMADA100_H
|
||||
|
||||
#if defined (CONFIG_ARMADA100)
|
||||
|
||||
/* Common APB clock register bit definitions */
|
||||
#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
|
||||
#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
|
||||
#define APBC_RST (1<<2) /* Reset Generation */
|
||||
/* Functional Clock Selection Mask */
|
||||
#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
|
||||
|
||||
/* Fast Ethernet Controller Clock register definition */
|
||||
#define FE_CLK_RST 0x1
|
||||
#define FE_CLK_ENA 0x8
|
||||
|
||||
/* SSP2 Clock Control */
|
||||
#define SSP2_APBCLK 0x01
|
||||
#define SSP2_FNCLK 0x02
|
||||
|
||||
/* USB Clock/reset control bits */
|
||||
#define USB_SPH_AXICLK_EN 0x10
|
||||
#define USB_SPH_AXI_RST 0x02
|
||||
|
||||
/* MPMU Clocks */
|
||||
#define APB2_26M_EN (1 << 20)
|
||||
#define AP_26M (1 << 4)
|
||||
|
||||
/* Register Base Addresses */
|
||||
#define ARMD1_DRAM_BASE 0xB0000000
|
||||
#define ARMD1_FEC_BASE 0xC0800000
|
||||
#define ARMD1_TIMER_BASE 0xD4014000
|
||||
#define ARMD1_APBC1_BASE 0xD4015000
|
||||
#define ARMD1_APBC2_BASE 0xD4015800
|
||||
#define ARMD1_UART1_BASE 0xD4017000
|
||||
#define ARMD1_UART2_BASE 0xD4018000
|
||||
#define ARMD1_GPIO_BASE 0xD4019000
|
||||
#define ARMD1_SSP1_BASE 0xD401B000
|
||||
#define ARMD1_SSP2_BASE 0xD401C000
|
||||
#define ARMD1_MFPR_BASE 0xD401E000
|
||||
#define ARMD1_SSP3_BASE 0xD401F000
|
||||
#define ARMD1_SSP4_BASE 0xD4020000
|
||||
#define ARMD1_SSP5_BASE 0xD4021000
|
||||
#define ARMD1_UART3_BASE 0xD4026000
|
||||
#define ARMD1_MPMU_BASE 0xD4050000
|
||||
#define ARMD1_USB_HOST_BASE 0xD4209000
|
||||
#define ARMD1_APMU_BASE 0xD4282800
|
||||
#define ARMD1_CPU_BASE 0xD4282C00
|
||||
|
||||
#endif /* CONFIG_ARMADA100 */
|
||||
#endif /* _ASM_ARCH_ARMADA100_H */
|
||||
42
u-boot/arch/arm/include/asm/arch-armada100/config.h
Normal file
42
u-boot/arch/arm/include/asm/arch-armada100/config.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Lei Wen <leiwen@marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file should be included in board config header file.
|
||||
*
|
||||
* It supports common definitions for Armada100 platform
|
||||
*/
|
||||
|
||||
#ifndef _ARMD1_CONFIG_H
|
||||
#define _ARMD1_CONFIG_H
|
||||
|
||||
#include <asm/arch/armada100.h>
|
||||
/* default Dcache Line length for armada100 */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
|
||||
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
|
||||
#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
|
||||
#define MV_MFPR_BASE ARMD1_MFPR_BASE
|
||||
#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
|
||||
#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
|
||||
represents UART Unit Enable */
|
||||
/*
|
||||
* I2C definition
|
||||
*/
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_I2C_MV 1
|
||||
#define CONFIG_MV_I2C_NUM 2
|
||||
#define CONFIG_I2C_MULTI_BUS 1
|
||||
#define CONFIG_MV_I2C_REG {0xd4011000, 0xd4025000}
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 0
|
||||
#define CONFIG_SYS_I2C_SLAVE 0xfe
|
||||
#endif
|
||||
|
||||
#endif /* _ARMD1_CONFIG_H */
|
||||
162
u-boot/arch/arm/include/asm/arch-armada100/cpu.h
Normal file
162
u-boot/arch/arm/include/asm/arch-armada100/cpu.h
Normal file
@@ -0,0 +1,162 @@
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ARMADA100CPU_H
|
||||
#define _ARMADA100CPU_H
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
/*
|
||||
* Main Power Management (MPMU) Registers
|
||||
* Refer Datasheet Appendix A.8
|
||||
*/
|
||||
struct armd1mpmu_registers {
|
||||
u8 pad0[0x08 - 0x00];
|
||||
u32 fccr; /*0x0008*/
|
||||
u32 pocr; /*0x000c*/
|
||||
u32 posr; /*0x0010*/
|
||||
u32 succr; /*0x0014*/
|
||||
u8 pad1[0x030 - 0x014 - 4];
|
||||
u32 gpcr; /*0x0030*/
|
||||
u8 pad2[0x200 - 0x030 - 4];
|
||||
u32 wdtpcr; /*0x0200*/
|
||||
u8 pad3[0x1000 - 0x200 - 4];
|
||||
u32 apcr; /*0x1000*/
|
||||
u32 apsr; /*0x1004*/
|
||||
u8 pad4[0x1020 - 0x1004 - 4];
|
||||
u32 aprr; /*0x1020*/
|
||||
u32 acgr; /*0x1024*/
|
||||
u32 arsr; /*0x1028*/
|
||||
};
|
||||
|
||||
/*
|
||||
* Application Subsystem Power Management
|
||||
* Refer Datasheet Appendix A.9
|
||||
*/
|
||||
struct armd1apmu_registers {
|
||||
u32 pcr; /* 0x000 */
|
||||
u32 ccr; /* 0x004 */
|
||||
u32 pad1;
|
||||
u32 ccsr; /* 0x00C */
|
||||
u32 fc_timer; /* 0x010 */
|
||||
u32 pad2;
|
||||
u32 ideal_cfg; /* 0x018 */
|
||||
u8 pad3[0x04C - 0x018 - 4];
|
||||
u32 lcdcrc; /* 0x04C */
|
||||
u32 cciccrc; /* 0x050 */
|
||||
u32 sd1crc; /* 0x054 */
|
||||
u32 sd2crc; /* 0x058 */
|
||||
u32 usbcrc; /* 0x05C */
|
||||
u32 nfccrc; /* 0x060 */
|
||||
u32 dmacrc; /* 0x064 */
|
||||
u32 pad4;
|
||||
u32 buscrc; /* 0x06C */
|
||||
u8 pad5[0x07C - 0x06C - 4];
|
||||
u32 wake_clr; /* 0x07C */
|
||||
u8 pad6[0x090 - 0x07C - 4];
|
||||
u32 core_status; /* 0x090 */
|
||||
u32 rfsc; /* 0x094 */
|
||||
u32 imr; /* 0x098 */
|
||||
u32 irwc; /* 0x09C */
|
||||
u32 isr; /* 0x0A0 */
|
||||
u8 pad7[0x0B0 - 0x0A0 - 4];
|
||||
u32 mhst; /* 0x0B0 */
|
||||
u32 msr; /* 0x0B4 */
|
||||
u8 pad8[0x0C0 - 0x0B4 - 4];
|
||||
u32 msst; /* 0x0C0 */
|
||||
u32 pllss; /* 0x0C4 */
|
||||
u32 smb; /* 0x0C8 */
|
||||
u32 gccrc; /* 0x0CC */
|
||||
u8 pad9[0x0D4 - 0x0CC - 4];
|
||||
u32 smccrc; /* 0x0D4 */
|
||||
u32 pad10;
|
||||
u32 xdcrc; /* 0x0DC */
|
||||
u32 sd3crc; /* 0x0E0 */
|
||||
u32 sd4crc; /* 0x0E4 */
|
||||
u8 pad11[0x0F0 - 0x0E4 - 4];
|
||||
u32 cfcrc; /* 0x0F0 */
|
||||
u32 mspcrc; /* 0x0F4 */
|
||||
u32 cmucrc; /* 0x0F8 */
|
||||
u32 fecrc; /* 0x0FC */
|
||||
u32 pciecrc; /* 0x100 */
|
||||
u32 epdcrc; /* 0x104 */
|
||||
};
|
||||
|
||||
/*
|
||||
* APB1 Clock Reset/Control Registers
|
||||
* Refer Datasheet Appendix A.10
|
||||
*/
|
||||
struct armd1apb1_registers {
|
||||
u32 uart1; /*0x000*/
|
||||
u32 uart2; /*0x004*/
|
||||
u32 gpio; /*0x008*/
|
||||
u32 pwm1; /*0x00c*/
|
||||
u32 pwm2; /*0x010*/
|
||||
u32 pwm3; /*0x014*/
|
||||
u32 pwm4; /*0x018*/
|
||||
u8 pad0[0x028 - 0x018 - 4];
|
||||
u32 rtc; /*0x028*/
|
||||
u32 twsi0; /*0x02c*/
|
||||
u32 kpc; /*0x030*/
|
||||
u32 timers; /*0x034*/
|
||||
u8 pad1[0x03c - 0x034 - 4];
|
||||
u32 aib; /*0x03c*/
|
||||
u32 sw_jtag; /*0x040*/
|
||||
u32 timer1; /*0x044*/
|
||||
u32 onewire; /*0x048*/
|
||||
u8 pad2[0x050 - 0x048 - 4];
|
||||
u32 asfar; /*0x050 AIB Secure First Access Reg*/
|
||||
u32 assar; /*0x054 AIB Secure Second Access Reg*/
|
||||
u8 pad3[0x06c - 0x054 - 4];
|
||||
u32 twsi1; /*0x06c*/
|
||||
u32 uart3; /*0x070*/
|
||||
u8 pad4[0x07c - 0x070 - 4];
|
||||
u32 timer2; /*0x07C*/
|
||||
u8 pad5[0x084 - 0x07c - 4];
|
||||
u32 ac97; /*0x084*/
|
||||
};
|
||||
|
||||
/*
|
||||
* APB2 Clock Reset/Control Registers
|
||||
* Refer Datasheet Appendix A.11
|
||||
*/
|
||||
struct armd1apb2_registers {
|
||||
u32 pad1[0x01C - 0x000];
|
||||
u32 ssp1_clkrst; /* 0x01C */
|
||||
u32 ssp2_clkrst; /* 0x020 */
|
||||
u32 pad2[0x04C - 0x020 - 4];
|
||||
u32 ssp3_clkrst; /* 0x04C */
|
||||
u32 pad3[0x058 - 0x04C - 4];
|
||||
u32 ssp4_clkrst; /* 0x058 */
|
||||
u32 ssp5_clkrst; /* 0x05C */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPU Interface Registers
|
||||
* Refer Datasheet Appendix A.2
|
||||
*/
|
||||
struct armd1cpu_registers {
|
||||
u32 chip_id; /* Chip Id Reg */
|
||||
u32 pad;
|
||||
u32 cpu_conf; /* CPU Conf Reg */
|
||||
u32 pad1;
|
||||
u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
|
||||
u32 pad2;
|
||||
u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
|
||||
u32 mcb_conf; /* MCB Conf Reg */
|
||||
u32 sys_boot_ctl; /* Sytem Boot Control */
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
u32 armd1_sdram_base(int);
|
||||
u32 armd1_sdram_size(int);
|
||||
|
||||
#endif /* _ARMADA100CPU_H */
|
||||
32
u-boot/arch/arm/include/asm/arch-armada100/gpio.h
Normal file
32
u-boot/arch/arm/include/asm/arch-armada100/gpio.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* eInfochips Ltd. <www.einfochips.com>
|
||||
* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_GPIO_H
|
||||
#define _ASM_ARCH_GPIO_H
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/arch/armada100.h>
|
||||
|
||||
#define GPIO_HIGH 1
|
||||
#define GPIO_LOW 0
|
||||
|
||||
#define GPIO_TO_REG(gp) (gp >> 5)
|
||||
#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F))
|
||||
#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
|
||||
|
||||
static inline void *get_gpio_base(int bank)
|
||||
{
|
||||
const unsigned int offset[4] = {0, 4, 8, 0x100};
|
||||
/* gpio register bank offset - refer Appendix A.36 */
|
||||
return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
|
||||
}
|
||||
|
||||
#endif /* _ASM_ARCH_GPIO_H */
|
||||
80
u-boot/arch/arm/include/asm/arch-armada100/mfp.h
Normal file
80
u-boot/arch/arm/include/asm/arch-armada100/mfp.h
Normal file
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
|
||||
* (C) Copyright 2007
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* 2007-08-21: eric miao <eric.miao@marvell.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
* Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARMADA100_MFP_H
|
||||
#define __ARMADA100_MFP_H
|
||||
|
||||
/*
|
||||
* Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
|
||||
*
|
||||
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
|
||||
*/
|
||||
/* UART1 */
|
||||
#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
|
||||
#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
|
||||
#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
|
||||
#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
|
||||
#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* UART2 */
|
||||
#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* UART3 */
|
||||
#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* I2c */
|
||||
#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* Fast Ethernet */
|
||||
#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* SPI */
|
||||
#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* More macros can be defined here... */
|
||||
|
||||
#define MFP_PIN_MAX 117
|
||||
|
||||
#endif /* __ARMADA100_MFP_H */
|
||||
79
u-boot/arch/arm/include/asm/arch-armada100/spi.h
Normal file
79
u-boot/arch/arm/include/asm/arch-armada100/spi.h
Normal file
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* eInfochips Ltd. <www.einfochips.com>
|
||||
* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARMADA100_SPI_H_
|
||||
#define __ARMADA100_SPI_H_
|
||||
|
||||
#include <asm/arch/armada100.h>
|
||||
|
||||
#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
|
||||
#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
|
||||
|
||||
/*
|
||||
* SSP Serial Port Registers
|
||||
* refer Appendix A.26
|
||||
*/
|
||||
struct ssp_reg {
|
||||
u32 sscr0; /* SSP Control Register 0 - 0x000 */
|
||||
u32 sscr1; /* SSP Control Register 1 - 0x004 */
|
||||
u32 sssr; /* SSP Status Register - 0x008 */
|
||||
u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
|
||||
u32 ssdr; /* SSP Data Register - 0x010 */
|
||||
u32 pad1[5];
|
||||
u32 ssto; /* SSP Timeout Register - 0x028 */
|
||||
u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
|
||||
u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
|
||||
u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
|
||||
u32 sstss; /* SSP Timeslot Status Register - 0x038 */
|
||||
};
|
||||
|
||||
#define DEFAULT_WORD_LEN 8
|
||||
#define SSP_FLUSH_NUM 0x2000
|
||||
#define RX_THRESH_DEF 8
|
||||
#define TX_THRESH_DEF 8
|
||||
#define TIMEOUT_DEF 1000
|
||||
|
||||
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
|
||||
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
|
||||
#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
|
||||
#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
|
||||
setting */
|
||||
#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
|
||||
#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
|
||||
#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
|
||||
#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
|
||||
|
||||
#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
|
||||
#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
|
||||
#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
|
||||
Interrupt enable */
|
||||
|
||||
#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
|
||||
#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
|
||||
#define SSCR0_FRF 0x30 /* FRame Format (mask) */
|
||||
#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
|
||||
Peripheral Interface */
|
||||
#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
|
||||
Serial Protocol (SSP) */
|
||||
#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
|
||||
#define SSCR0_ECS (1 << 6) /* External clock select */
|
||||
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
|
||||
Enable */
|
||||
|
||||
#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
|
||||
#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
|
||||
#define SSSR_BSY (1 << 4) /* SSP Busy */
|
||||
#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
|
||||
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
|
||||
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
|
||||
#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
|
||||
|
||||
#endif /* __ARMADA100_SPI_H_ */
|
||||
63
u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h
Normal file
63
u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h
Normal file
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* eInfochips Ltd. <www.einfochips.com>
|
||||
* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
|
||||
*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __UTMI_ARMADA100__
|
||||
#define __UTMI_ARMADA100__
|
||||
|
||||
#define UTMI_PHY_BASE 0xD4206000
|
||||
|
||||
/* utmi_ctrl - bits */
|
||||
#define INPKT_DELAY_SOF (1 << 28)
|
||||
#define PLL_PWR_UP 2
|
||||
#define PHY_PWR_UP 1
|
||||
|
||||
/* utmi_pll - bits */
|
||||
#define PLL_FBDIV_MASK 0x00000FF0
|
||||
#define PLL_FBDIV 4
|
||||
#define PLL_REFDIV_MASK 0x0000000F
|
||||
#define PLL_REFDIV 0
|
||||
#define PLL_READY 0x800000
|
||||
#define VCOCAL_START (1 << 21)
|
||||
|
||||
#define N_DIVIDER 0xEE
|
||||
#define M_DIVIDER 0x0B
|
||||
|
||||
/* utmi_tx - bits */
|
||||
#define CK60_PHSEL 17
|
||||
#define PHSEL_VAL 0x4
|
||||
#define RCAL_START (1 << 12)
|
||||
|
||||
/*
|
||||
* USB PHY registers
|
||||
* Refer Datasheet Appendix A.21
|
||||
*/
|
||||
struct armd1usb_phy_reg {
|
||||
u32 utmi_rev; /* USB PHY Revision */
|
||||
u32 utmi_ctrl; /* USB PHY Control register */
|
||||
u32 utmi_pll; /* PLL register */
|
||||
u32 utmi_tx; /* Tx register */
|
||||
u32 utmi_rx; /* Rx register */
|
||||
u32 utmi_ivref; /* IVREF register */
|
||||
u32 utmi_tst_g0; /* Test group 0 register */
|
||||
u32 utmi_tst_g1; /* Test group 1 register */
|
||||
u32 utmi_tst_g2; /* Test group 2 register */
|
||||
u32 utmi_tst_g3; /* Test group 3 register */
|
||||
u32 utmi_tst_g4; /* Test group 4 register */
|
||||
u32 utmi_tst_g5; /* Test group 5 register */
|
||||
u32 utmi_reserve; /* Reserve Register */
|
||||
u32 utmi_usb_int; /* USB interuppt register */
|
||||
u32 utmi_dbg_ctl; /* Debug control register */
|
||||
u32 utmi_otg_addon; /* OTG addon register */
|
||||
};
|
||||
|
||||
int utmi_init(void);
|
||||
|
||||
#endif /* __UTMI_ARMADA100__ */
|
||||
50
u-boot/arch/arm/include/asm/arch-armv7/generictimer.h
Normal file
50
u-boot/arch/arm/include/asm/arch-armv7/generictimer.h
Normal file
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - ARM Ltd
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
* Based on code by Carl van Schaik <carl@ok-labs.com>.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _GENERICTIMER_H_
|
||||
#define _GENERICTIMER_H_
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* This macro provide a physical timer that can be used for delay in the code.
|
||||
* The macro is moved from sunxi/psci_sun7i.S
|
||||
*
|
||||
* reg: is used in this macro.
|
||||
* ticks: The freq is based on generic timer.
|
||||
*/
|
||||
.macro timer_wait reg, ticks
|
||||
movw \reg, #(\ticks & 0xffff)
|
||||
movt \reg, #(\ticks >> 16)
|
||||
mcr p15, 0, \reg, c14, c2, 0
|
||||
isb
|
||||
mov \reg, #3
|
||||
mcr p15, 0, \reg, c14, c2, 1
|
||||
1 : isb
|
||||
mrc p15, 0, \reg, c14, c2, 1
|
||||
ands \reg, \reg, #4
|
||||
bne 1b
|
||||
mov \reg, #0
|
||||
mcr p15, 0, \reg, c14, c2, 1
|
||||
isb
|
||||
.endm
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _GENERICTIMER_H_ */
|
||||
20
u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h
Normal file
20
u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
* (C) Copyright 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _GLOBALTIMER_H_
|
||||
#define _GLOBALTIMER_H_
|
||||
|
||||
struct globaltimer {
|
||||
u32 cnt_l; /* 0x00 */
|
||||
u32 cnt_h;
|
||||
u32 ctl;
|
||||
u32 stat;
|
||||
u32 cmp_l; /* 0x10 */
|
||||
u32 cmp_h;
|
||||
u32 inc;
|
||||
};
|
||||
|
||||
#endif /* _GLOBALTIMER_H_ */
|
||||
54
u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h
Normal file
54
u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h
Normal file
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* (C) Copyright 2010 Linaro
|
||||
* Matt Waddel, <matt.waddel@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _SYSCTRL_H_
|
||||
#define _SYSCTRL_H_
|
||||
|
||||
/* System controller (SP810) register definitions */
|
||||
#define SP810_TIMER0_ENSEL (1 << 15)
|
||||
#define SP810_TIMER1_ENSEL (1 << 17)
|
||||
#define SP810_TIMER2_ENSEL (1 << 19)
|
||||
#define SP810_TIMER3_ENSEL (1 << 21)
|
||||
|
||||
struct sysctrl {
|
||||
u32 scctrl; /* 0x000 */
|
||||
u32 scsysstat;
|
||||
u32 scimctrl;
|
||||
u32 scimstat;
|
||||
u32 scxtalctrl;
|
||||
u32 scpllctrl;
|
||||
u32 scpllfctrl;
|
||||
u32 scperctrl0;
|
||||
u32 scperctrl1;
|
||||
u32 scperen;
|
||||
u32 scperdis;
|
||||
u32 scperclken;
|
||||
u32 scperstat;
|
||||
u32 res1[0x006];
|
||||
u32 scflashctrl; /* 0x04c */
|
||||
u32 res2[0x3a4];
|
||||
u32 scsysid0; /* 0xee0 */
|
||||
u32 scsysid1;
|
||||
u32 scsysid2;
|
||||
u32 scsysid3;
|
||||
u32 scitcr;
|
||||
u32 scitir0;
|
||||
u32 scitir1;
|
||||
u32 scitor;
|
||||
u32 sccntctrl;
|
||||
u32 sccntdata;
|
||||
u32 sccntstep;
|
||||
u32 res3[0x32];
|
||||
u32 scperiphid0; /* 0xfe0 */
|
||||
u32 scperiphid1;
|
||||
u32 scperiphid2;
|
||||
u32 scperiphid3;
|
||||
u32 scpcellid0;
|
||||
u32 scpcellid1;
|
||||
u32 scpcellid2;
|
||||
u32 scpcellid3;
|
||||
};
|
||||
#endif /* _SYSCTRL_H_ */
|
||||
36
u-boot/arch/arm/include/asm/arch-armv7/systimer.h
Normal file
36
u-boot/arch/arm/include/asm/arch-armv7/systimer.h
Normal file
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* (C) Copyright 2010 Linaro
|
||||
* Matt Waddel, <matt.waddel@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _SYSTIMER_H_
|
||||
#define _SYSTIMER_H_
|
||||
|
||||
/* AMBA timer register base address */
|
||||
#define SYSTIMER_BASE 0x10011000
|
||||
|
||||
#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */
|
||||
#define SYSTIMER_RELOAD 0xFFFFFFFF
|
||||
#define SYSTIMER_EN (1 << 7)
|
||||
#define SYSTIMER_32BIT (1 << 1)
|
||||
#define SYSTIMER_PRESC_16 (1 << 2)
|
||||
#define SYSTIMER_PRESC_256 (1 << 3)
|
||||
|
||||
struct systimer {
|
||||
u32 timer0load; /* 0x00 */
|
||||
u32 timer0value;
|
||||
u32 timer0control;
|
||||
u32 timer0intclr;
|
||||
u32 timer0ris;
|
||||
u32 timer0mis;
|
||||
u32 timer0bgload;
|
||||
u32 timer1load; /* 0x20 */
|
||||
u32 timer1value;
|
||||
u32 timer1control;
|
||||
u32 timer1intclr;
|
||||
u32 timer1ris;
|
||||
u32 timer1mis;
|
||||
u32 timer1bgload;
|
||||
};
|
||||
#endif /* _SYSTIMER_H_ */
|
||||
39
u-boot/arch/arm/include/asm/arch-armv7/wdt.h
Normal file
39
u-boot/arch/arm/include/asm/arch-armv7/wdt.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Matt Waddel, <matt.waddel@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _WDT_H_
|
||||
#define _WDT_H_
|
||||
|
||||
/* Watchdog timer (SP805) register base address */
|
||||
#define WDT_BASE 0x100E5000
|
||||
|
||||
#define WDT_EN 0x2
|
||||
#define WDT_RESET_LOAD 0x0
|
||||
|
||||
struct wdt {
|
||||
u32 wdogload; /* 0x000 */
|
||||
u32 wdogvalue;
|
||||
u32 wdogcontrol;
|
||||
u32 wdogintclr;
|
||||
u32 wdogris;
|
||||
u32 wdogmis;
|
||||
u32 res1[0x2F9];
|
||||
u32 wdoglock; /* 0xC00 */
|
||||
u32 res2[0xBE];
|
||||
u32 wdogitcr; /* 0xF00 */
|
||||
u32 wdogitop;
|
||||
u32 res3[0x35];
|
||||
u32 wdogperiphid0; /* 0xFE0 */
|
||||
u32 wdogperiphid1;
|
||||
u32 wdogperiphid2;
|
||||
u32 wdogperiphid3;
|
||||
u32 wdogpcellid0;
|
||||
u32 wdogpcellid1;
|
||||
u32 wdogpcellid2;
|
||||
u32 wdogpcellid3;
|
||||
};
|
||||
|
||||
#endif /* _WDT_H_ */
|
||||
15
u-boot/arch/arm/include/asm/arch-bcm235xx/boot0.h
Normal file
15
u-boot/arch/arm/include/asm/arch-bcm235xx/boot0.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright 2016 Broadcom Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __BOOT0_H
|
||||
#define __BOOT0_H
|
||||
|
||||
/* BOOT0 header information */
|
||||
#define ARM_SOC_BOOT0_HOOK \
|
||||
.word 0xbabeface; \
|
||||
.word _end - _start
|
||||
|
||||
#endif /* __BOOT0_H */
|
||||
15
u-boot/arch/arm/include/asm/arch-bcm235xx/gpio.h
Normal file
15
u-boot/arch/arm/include/asm/arch-bcm235xx/gpio.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM235XX_GPIO_H
|
||||
#define __ARCH_BCM235XX_GPIO_H
|
||||
|
||||
/*
|
||||
* Empty file - cmd_gpio.c requires this. The implementation
|
||||
* is in drivers/gpio/kona_gpio.c instead of inlined here.
|
||||
*/
|
||||
|
||||
#endif
|
||||
31
u-boot/arch/arm/include/asm/arch-bcm235xx/sysmap.h
Normal file
31
u-boot/arch/arm/include/asm/arch-bcm235xx/sysmap.h
Normal file
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM235XX_SYSMAP_H
|
||||
|
||||
#define BSC1_BASE_ADDR 0x3e016000
|
||||
#define BSC2_BASE_ADDR 0x3e017000
|
||||
#define BSC3_BASE_ADDR 0x3e018000
|
||||
#define GPIO2_BASE_ADDR 0x35003000
|
||||
#define HSOTG_BASE_ADDR 0x3f120000
|
||||
#define HSOTG_CTRL_BASE_ADDR 0x3f130000
|
||||
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
|
||||
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
|
||||
#define PMU_BSC_BASE_ADDR 0x3500d000
|
||||
#define SDIO1_BASE_ADDR 0x3f180000
|
||||
#define SDIO2_BASE_ADDR 0x3f190000
|
||||
#define SDIO3_BASE_ADDR 0x3f1a0000
|
||||
#define SDIO4_BASE_ADDR 0x3f1b0000
|
||||
#define TIMER_BASE_ADDR 0x3e00d000
|
||||
|
||||
#define HSOTG_DCTL_OFFSET 0x00000804
|
||||
#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
|
||||
|
||||
#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
|
||||
#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
|
||||
#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
|
||||
|
||||
#endif
|
||||
15
u-boot/arch/arm/include/asm/arch-bcm281xx/boot0.h
Normal file
15
u-boot/arch/arm/include/asm/arch-bcm281xx/boot0.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright 2016 Broadcom Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __BOOT0_H
|
||||
#define __BOOT0_H
|
||||
|
||||
/* BOOT0 header information */
|
||||
#define ARM_SOC_BOOT0_HOOK \
|
||||
.word 0xbabeface; \
|
||||
.word _end - _start
|
||||
|
||||
#endif /* __BOOT0_H */
|
||||
15
u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h
Normal file
15
u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM281XX_GPIO_H
|
||||
#define __ARCH_BCM281XX_GPIO_H
|
||||
|
||||
/*
|
||||
* Empty file - cmd_gpio.c requires this. The implementation
|
||||
* is in drivers/gpio/kona_gpio.c instead of inlined here.
|
||||
*/
|
||||
|
||||
#endif
|
||||
37
u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h
Normal file
37
u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h
Normal file
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM281XX_SYSMAP_H
|
||||
|
||||
#define BSC1_BASE_ADDR 0x3e016000
|
||||
#define BSC2_BASE_ADDR 0x3e017000
|
||||
#define BSC3_BASE_ADDR 0x3e018000
|
||||
#define DWDMA_AHB_BASE_ADDR 0x38100000
|
||||
#define ESUB_CLK_BASE_ADDR 0x38000000
|
||||
#define ESW_CONTRL_BASE_ADDR 0x38200000
|
||||
#define GPIO2_BASE_ADDR 0x35003000
|
||||
#define HSOTG_BASE_ADDR 0x3f120000
|
||||
#define HSOTG_CTRL_BASE_ADDR 0x3f130000
|
||||
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
|
||||
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
|
||||
#define PMU_BSC_BASE_ADDR 0x3500d000
|
||||
#define PWRMGR_BASE_ADDR 0x35010000
|
||||
#define SDIO1_BASE_ADDR 0x3f180000
|
||||
#define SDIO2_BASE_ADDR 0x3f190000
|
||||
#define SDIO3_BASE_ADDR 0x3f1a0000
|
||||
#define SDIO4_BASE_ADDR 0x3f1b0000
|
||||
#define SECWD_BASE_ADDR 0x3500c000
|
||||
#define SECWD2_BASE_ADDR 0x35002f40
|
||||
#define TIMER_BASE_ADDR 0x3e00d000
|
||||
|
||||
#define HSOTG_DCTL_OFFSET 0x00000804
|
||||
#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
|
||||
|
||||
#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
|
||||
#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
|
||||
#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
|
||||
|
||||
#endif
|
||||
33
u-boot/arch/arm/include/asm/arch-bcmcygnus/configs.h
Normal file
33
u-boot/arch/arm/include/asm/arch-bcmcygnus/configs.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright 2014 Broadcom Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_CONFIGS_H
|
||||
#define __ARCH_CONFIGS_H
|
||||
|
||||
#include <asm/iproc-common/configs.h>
|
||||
|
||||
/* uArchitecture specifics */
|
||||
|
||||
/* Serial Info */
|
||||
/* Post pad 3 bytes after each reg addr */
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_MEM32
|
||||
|
||||
#define CONFIG_SYS_NS16550_CLK 100000000
|
||||
#define CONFIG_SYS_NS16550_CLK_DIV 54
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
#define CONFIG_SYS_NS16550_COM3 0x18023000
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_BCM_SF2_ETH
|
||||
#define CONFIG_BCM_SF2_ETH_GMAC
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_BROADCOM
|
||||
#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
|
||||
|
||||
#endif /* __ARCH_CONFIGS_H */
|
||||
22
u-boot/arch/arm/include/asm/arch-bcmnsp/configs.h
Normal file
22
u-boot/arch/arm/include/asm/arch-bcmnsp/configs.h
Normal file
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright 2014 Broadcom Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_CONFIGS_H
|
||||
#define __ARCH_CONFIGS_H
|
||||
|
||||
#include <asm/iproc-common/configs.h>
|
||||
|
||||
/* uArchitecture specifics */
|
||||
|
||||
/* Serial Info */
|
||||
/* no padding */
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
|
||||
#define CONFIG_SYS_NS16550_CLK 0x03b9aca0
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550_COM1 0x18000300
|
||||
|
||||
#endif /* __ARCH_CONFIGS_H */
|
||||
667
u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h
Normal file
667
u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h
Normal file
@@ -0,0 +1,667 @@
|
||||
/*
|
||||
* Cirrus Logic EP93xx register definitions.
|
||||
*
|
||||
* Copyright (C) 2013
|
||||
* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
|
||||
*
|
||||
* Copyright (C) 2009
|
||||
* Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*
|
||||
* Copyright (C) 2006
|
||||
* Dominic Rath <Dominic.Rath@gmx.de>
|
||||
*
|
||||
* Copyright (C) 2004, 2005
|
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
|
||||
*
|
||||
* Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
|
||||
*
|
||||
* Copyright (C) 2004 Ray Lehtiniemi
|
||||
* Copyright (C) 2003 Cirrus Logic, Inc
|
||||
* Copyright (C) 1999 ARM Limited.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#define EP93XX_AHB_BASE 0x80000000
|
||||
#define EP93XX_APB_BASE 0x80800000
|
||||
|
||||
/*
|
||||
* 0x80000000 - 0x8000FFFF: DMA
|
||||
*/
|
||||
#define DMA_OFFSET 0x000000
|
||||
#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct dma_channel {
|
||||
uint32_t control;
|
||||
uint32_t interrupt;
|
||||
uint32_t ppalloc;
|
||||
uint32_t status;
|
||||
uint32_t reserved0;
|
||||
uint32_t remain;
|
||||
uint32_t reserved1[2];
|
||||
uint32_t maxcnt0;
|
||||
uint32_t base0;
|
||||
uint32_t current0;
|
||||
uint32_t reserved2;
|
||||
uint32_t maxcnt1;
|
||||
uint32_t base1;
|
||||
uint32_t current1;
|
||||
uint32_t reserved3;
|
||||
};
|
||||
|
||||
struct dma_regs {
|
||||
struct dma_channel m2p_channel_0;
|
||||
struct dma_channel m2p_channel_1;
|
||||
struct dma_channel m2p_channel_2;
|
||||
struct dma_channel m2p_channel_3;
|
||||
struct dma_channel m2m_channel_0;
|
||||
struct dma_channel m2m_channel_1;
|
||||
struct dma_channel reserved0[2];
|
||||
struct dma_channel m2p_channel_5;
|
||||
struct dma_channel m2p_channel_4;
|
||||
struct dma_channel m2p_channel_7;
|
||||
struct dma_channel m2p_channel_6;
|
||||
struct dma_channel m2p_channel_9;
|
||||
struct dma_channel m2p_channel_8;
|
||||
uint32_t channel_arbitration;
|
||||
uint32_t reserved[15];
|
||||
uint32_t global_interrupt;
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80010000 - 0x8001FFFF: Ethernet MAC
|
||||
*/
|
||||
#define MAC_OFFSET 0x010000
|
||||
#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mac_queue {
|
||||
uint32_t badd;
|
||||
union { /* deal with half-word aligned registers */
|
||||
uint32_t blen;
|
||||
union {
|
||||
uint16_t filler;
|
||||
uint16_t curlen;
|
||||
};
|
||||
};
|
||||
uint32_t curadd;
|
||||
};
|
||||
|
||||
struct mac_regs {
|
||||
uint32_t rxctl;
|
||||
uint32_t txctl;
|
||||
uint32_t testctl;
|
||||
uint32_t reserved0;
|
||||
uint32_t miicmd;
|
||||
uint32_t miidata;
|
||||
uint32_t miists;
|
||||
uint32_t reserved1;
|
||||
uint32_t selfctl;
|
||||
uint32_t inten;
|
||||
uint32_t intstsp;
|
||||
uint32_t intstsc;
|
||||
uint32_t reserved2[2];
|
||||
uint32_t diagad;
|
||||
uint32_t diagdata;
|
||||
uint32_t gt;
|
||||
uint32_t fct;
|
||||
uint32_t fcf;
|
||||
uint32_t afp;
|
||||
union {
|
||||
struct {
|
||||
uint32_t indad;
|
||||
uint32_t indad_upper;
|
||||
};
|
||||
uint32_t hashtbl;
|
||||
};
|
||||
uint32_t reserved3[2];
|
||||
uint32_t giintsts;
|
||||
uint32_t giintmsk;
|
||||
uint32_t giintrosts;
|
||||
uint32_t giintfrc;
|
||||
uint32_t txcollcnt;
|
||||
uint32_t rxmissnct;
|
||||
uint32_t rxruntcnt;
|
||||
uint32_t reserved4;
|
||||
uint32_t bmctl;
|
||||
uint32_t bmsts;
|
||||
uint32_t rxbca;
|
||||
uint32_t reserved5;
|
||||
struct mac_queue rxdq;
|
||||
uint32_t rxdqenq;
|
||||
struct mac_queue rxstsq;
|
||||
uint32_t rxstsqenq;
|
||||
struct mac_queue txdq;
|
||||
uint32_t txdqenq;
|
||||
struct mac_queue txstsq;
|
||||
uint32_t reserved6;
|
||||
uint32_t rxbufthrshld;
|
||||
uint32_t txbufthrshld;
|
||||
uint32_t rxststhrshld;
|
||||
uint32_t txststhrshld;
|
||||
uint32_t rxdthrshld;
|
||||
uint32_t txdthrshld;
|
||||
uint32_t maxfrmlen;
|
||||
uint32_t maxhdrlen;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define SELFCTL_RWP (1 << 7)
|
||||
#define SELFCTL_GPO0 (1 << 5)
|
||||
#define SELFCTL_PUWE (1 << 4)
|
||||
#define SELFCTL_PDWE (1 << 3)
|
||||
#define SELFCTL_MIIL (1 << 2)
|
||||
#define SELFCTL_RESET (1 << 0)
|
||||
|
||||
#define INTSTS_RWI (1 << 30)
|
||||
#define INTSTS_RXMI (1 << 29)
|
||||
#define INTSTS_RXBI (1 << 28)
|
||||
#define INTSTS_RXSQI (1 << 27)
|
||||
#define INTSTS_TXLEI (1 << 26)
|
||||
#define INTSTS_ECIE (1 << 25)
|
||||
#define INTSTS_TXUHI (1 << 24)
|
||||
#define INTSTS_MOI (1 << 18)
|
||||
#define INTSTS_TXCOI (1 << 17)
|
||||
#define INTSTS_RXROI (1 << 16)
|
||||
#define INTSTS_MIII (1 << 12)
|
||||
#define INTSTS_PHYI (1 << 11)
|
||||
#define INTSTS_TI (1 << 10)
|
||||
#define INTSTS_AHBE (1 << 8)
|
||||
#define INTSTS_OTHER (1 << 4)
|
||||
#define INTSTS_TXSQ (1 << 3)
|
||||
#define INTSTS_RXSQ (1 << 2)
|
||||
|
||||
#define BMCTL_MT (1 << 13)
|
||||
#define BMCTL_TT (1 << 12)
|
||||
#define BMCTL_UNH (1 << 11)
|
||||
#define BMCTL_TXCHR (1 << 10)
|
||||
#define BMCTL_TXDIS (1 << 9)
|
||||
#define BMCTL_TXEN (1 << 8)
|
||||
#define BMCTL_EH2 (1 << 6)
|
||||
#define BMCTL_EH1 (1 << 5)
|
||||
#define BMCTL_EEOB (1 << 4)
|
||||
#define BMCTL_RXCHR (1 << 2)
|
||||
#define BMCTL_RXDIS (1 << 1)
|
||||
#define BMCTL_RXEN (1 << 0)
|
||||
|
||||
#define BMSTS_TXACT (1 << 7)
|
||||
#define BMSTS_TP (1 << 4)
|
||||
#define BMSTS_RXACT (1 << 3)
|
||||
#define BMSTS_QID_MASK 0x07
|
||||
#define BMSTS_QID_RXDATA 0x00
|
||||
#define BMSTS_QID_TXDATA 0x01
|
||||
#define BMSTS_QID_RXSTS 0x02
|
||||
#define BMSTS_QID_TXSTS 0x03
|
||||
#define BMSTS_QID_RXDESC 0x04
|
||||
#define BMSTS_QID_TXDESC 0x05
|
||||
|
||||
#define AFP_MASK 0x07
|
||||
#define AFP_IAPRIMARY 0x00
|
||||
#define AFP_IASECONDARY1 0x01
|
||||
#define AFP_IASECONDARY2 0x02
|
||||
#define AFP_IASECONDARY3 0x03
|
||||
#define AFP_TX 0x06
|
||||
#define AFP_HASH 0x07
|
||||
|
||||
#define RXCTL_PAUSEA (1 << 20)
|
||||
#define RXCTL_RXFCE1 (1 << 19)
|
||||
#define RXCTL_RXFCE0 (1 << 18)
|
||||
#define RXCTL_BCRC (1 << 17)
|
||||
#define RXCTL_SRXON (1 << 16)
|
||||
#define RXCTL_RCRCA (1 << 13)
|
||||
#define RXCTL_RA (1 << 12)
|
||||
#define RXCTL_PA (1 << 11)
|
||||
#define RXCTL_BA (1 << 10)
|
||||
#define RXCTL_MA (1 << 9)
|
||||
#define RXCTL_IAHA (1 << 8)
|
||||
#define RXCTL_IA3 (1 << 3)
|
||||
#define RXCTL_IA2 (1 << 2)
|
||||
#define RXCTL_IA1 (1 << 1)
|
||||
#define RXCTL_IA0 (1 << 0)
|
||||
|
||||
#define TXCTL_DEFDIS (1 << 7)
|
||||
#define TXCTL_MBE (1 << 6)
|
||||
#define TXCTL_ICRC (1 << 5)
|
||||
#define TXCTL_TPD (1 << 4)
|
||||
#define TXCTL_OCOLL (1 << 3)
|
||||
#define TXCTL_SP (1 << 2)
|
||||
#define TXCTL_PB (1 << 1)
|
||||
#define TXCTL_STXON (1 << 0)
|
||||
|
||||
#define MIICMD_REGAD_MASK (0x001F)
|
||||
#define MIICMD_PHYAD_MASK (0x03E0)
|
||||
#define MIICMD_OPCODE_MASK (0xC000)
|
||||
#define MIICMD_PHYAD_8950 (0x0000)
|
||||
#define MIICMD_OPCODE_READ (0x8000)
|
||||
#define MIICMD_OPCODE_WRITE (0x4000)
|
||||
|
||||
#define MIISTS_BUSY (1 << 0)
|
||||
|
||||
/*
|
||||
* 0x80020000 - 0x8002FFFF: USB OHCI
|
||||
*/
|
||||
#define USB_OFFSET 0x020000
|
||||
#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80030000 - 0x8003FFFF: Raster engine
|
||||
*/
|
||||
#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
|
||||
#define RASTER_OFFSET 0x030000
|
||||
#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80040000 - 0x8004FFFF: Graphics accelerator
|
||||
*/
|
||||
#if defined(CONFIG_EP9315)
|
||||
#define GFX_OFFSET 0x040000
|
||||
#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80050000 - 0x8005FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80060000 - 0x8006FFFF: SDRAM controller
|
||||
*/
|
||||
#define SDRAM_OFFSET 0x060000
|
||||
#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct sdram_regs {
|
||||
uint32_t reserved;
|
||||
uint32_t glconfig;
|
||||
uint32_t refrshtimr;
|
||||
uint32_t bootsts;
|
||||
uint32_t devcfg0;
|
||||
uint32_t devcfg1;
|
||||
uint32_t devcfg2;
|
||||
uint32_t devcfg3;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
|
||||
#define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
|
||||
#define SDRAM_DEVCFG_SROMLL (1 << 5)
|
||||
#define SDRAM_DEVCFG_CASLAT_2 0x00010000
|
||||
#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
|
||||
|
||||
#define SDRAM_OFF_GLCONFIG 0x0004
|
||||
#define SDRAM_OFF_REFRSHTIMR 0x0008
|
||||
|
||||
#define SDRAM_OFF_DEVCFG0 0x0010
|
||||
#define SDRAM_OFF_DEVCFG1 0x0014
|
||||
#define SDRAM_OFF_DEVCFG2 0x0018
|
||||
#define SDRAM_OFF_DEVCFG3 0x001C
|
||||
|
||||
#define SDRAM_DEVCFG0_BASE 0xC0000000
|
||||
#define SDRAM_DEVCFG1_BASE 0xD0000000
|
||||
#define SDRAM_DEVCFG2_BASE 0xE0000000
|
||||
#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
|
||||
#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
|
||||
|
||||
#define GLCONFIG_INIT (1 << 0)
|
||||
#define GLCONFIG_MRS (1 << 1)
|
||||
#define GLCONFIG_SMEMBUSY (1 << 5)
|
||||
#define GLCONFIG_LCR (1 << 6)
|
||||
#define GLCONFIG_REARBEN (1 << 7)
|
||||
#define GLCONFIG_CLKSHUTDOWN (1 << 30)
|
||||
#define GLCONFIG_CKE (1 << 31)
|
||||
|
||||
#define EP93XX_SDRAMCTRL 0x80060000
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
|
||||
|
||||
#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
|
||||
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
|
||||
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
|
||||
|
||||
/*
|
||||
* 0x80070000 - 0x8007FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
|
||||
*/
|
||||
#define SMC_OFFSET 0x080000
|
||||
#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct smc_regs {
|
||||
uint32_t bcr0;
|
||||
uint32_t bcr1;
|
||||
uint32_t bcr2;
|
||||
uint32_t bcr3;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t bcr6;
|
||||
uint32_t bcr7;
|
||||
#if defined(CONFIG_EP9315)
|
||||
uint32_t pcattribute;
|
||||
uint32_t pccommon;
|
||||
uint32_t pcio;
|
||||
uint32_t reserved1[5];
|
||||
uint32_t pcmciactrl;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#define EP93XX_OFF_SMCBCR0 0x00
|
||||
#define EP93XX_OFF_SMCBCR1 0x04
|
||||
#define EP93XX_OFF_SMCBCR2 0x08
|
||||
#define EP93XX_OFF_SMCBCR3 0x0C
|
||||
#define EP93XX_OFF_SMCBCR6 0x18
|
||||
#define EP93XX_OFF_SMCBCR7 0x1C
|
||||
|
||||
#define SMC_BCR_IDCY_SHIFT 0
|
||||
#define SMC_BCR_WST1_SHIFT 5
|
||||
#define SMC_BCR_BLE (1 << 10)
|
||||
#define SMC_BCR_WST2_SHIFT 11
|
||||
#define SMC_BCR_MW_SHIFT 28
|
||||
|
||||
/*
|
||||
* 0x80090000 - 0x8009FFFF: Boot ROM
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800A0000 - 0x800AFFFF: IDE interface
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800B0000 - 0x800BFFFF: VIC1
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800C0000 - 0x800CFFFF: VIC2
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800D0000 - 0x800FFFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80800000 - 0x8080FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80810000 - 0x8081FFFF: Timers
|
||||
*/
|
||||
#define TIMER_OFFSET 0x010000
|
||||
#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct timer {
|
||||
uint32_t load;
|
||||
uint32_t value;
|
||||
uint32_t control;
|
||||
uint32_t clear;
|
||||
};
|
||||
|
||||
struct timer4 {
|
||||
uint32_t value_low;
|
||||
uint32_t value_high;
|
||||
};
|
||||
|
||||
struct timer_regs {
|
||||
struct timer timer1;
|
||||
uint32_t reserved0[4];
|
||||
struct timer timer2;
|
||||
uint32_t reserved1[12];
|
||||
struct timer4 timer4;
|
||||
uint32_t reserved2[6];
|
||||
struct timer timer3;
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80820000 - 0x8082FFFF: I2S
|
||||
*/
|
||||
#define I2S_OFFSET 0x020000
|
||||
#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80830000 - 0x8083FFFF: Security
|
||||
*/
|
||||
#define SECURITY_OFFSET 0x030000
|
||||
#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
|
||||
|
||||
#define EXTENSIONID (SECURITY_BASE + 0x2714)
|
||||
|
||||
/*
|
||||
* 0x80840000 - 0x8084FFFF: GPIO
|
||||
*/
|
||||
#define GPIO_OFFSET 0x040000
|
||||
#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gpio_int {
|
||||
uint32_t inttype1;
|
||||
uint32_t inttype2;
|
||||
uint32_t eoi;
|
||||
uint32_t inten;
|
||||
uint32_t intsts;
|
||||
uint32_t rawintsts;
|
||||
uint32_t db;
|
||||
};
|
||||
|
||||
struct gpio_regs {
|
||||
uint32_t padr;
|
||||
uint32_t pbdr;
|
||||
uint32_t pcdr;
|
||||
uint32_t pddr;
|
||||
uint32_t paddr;
|
||||
uint32_t pbddr;
|
||||
uint32_t pcddr;
|
||||
uint32_t pdddr;
|
||||
uint32_t pedr;
|
||||
uint32_t peddr;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t pfdr;
|
||||
uint32_t pfddr;
|
||||
uint32_t pgdr;
|
||||
uint32_t pgddr;
|
||||
uint32_t phdr;
|
||||
uint32_t phddr;
|
||||
uint32_t reserved1;
|
||||
uint32_t finttype1;
|
||||
uint32_t finttype2;
|
||||
uint32_t reserved2;
|
||||
struct gpio_int pfint;
|
||||
uint32_t reserved3[10];
|
||||
struct gpio_int paint;
|
||||
struct gpio_int pbint;
|
||||
uint32_t eedrive;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define EP93XX_LED_DATA 0x80840020
|
||||
#define EP93XX_LED_GREEN_ON 0x0001
|
||||
#define EP93XX_LED_RED_ON 0x0002
|
||||
|
||||
#define EP93XX_LED_DDR 0x80840024
|
||||
#define EP93XX_LED_GREEN_ENABLE 0x0001
|
||||
#define EP93XX_LED_RED_ENABLE 0x00020000
|
||||
|
||||
/*
|
||||
* 0x80850000 - 0x8087FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80880000 - 0x8088FFFF: AAC
|
||||
*/
|
||||
#define AAC_OFFSET 0x080000
|
||||
#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80890000 - 0x8089FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x808A0000 - 0x808AFFFF: SPI
|
||||
*/
|
||||
#define SPI_OFFSET 0x0A0000
|
||||
#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808B0000 - 0x808BFFFF: IrDA
|
||||
*/
|
||||
#define IRDA_OFFSET 0x0B0000
|
||||
#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808C0000 - 0x808CFFFF: UART1
|
||||
*/
|
||||
#define UART1_OFFSET 0x0C0000
|
||||
#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808D0000 - 0x808DFFFF: UART2
|
||||
*/
|
||||
#define UART2_OFFSET 0x0D0000
|
||||
#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808E0000 - 0x808EFFFF: UART3
|
||||
*/
|
||||
#define UART3_OFFSET 0x0E0000
|
||||
#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808F0000 - 0x808FFFFF: Key Matrix
|
||||
*/
|
||||
#define KEY_OFFSET 0x0F0000
|
||||
#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80900000 - 0x8090FFFF: Touchscreen
|
||||
*/
|
||||
#define TOUCH_OFFSET 0x900000
|
||||
#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80910000 - 0x8091FFFF: Pulse Width Modulation
|
||||
*/
|
||||
#define PWM_OFFSET 0x910000
|
||||
#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80920000 - 0x8092FFFF: Real time clock
|
||||
*/
|
||||
#define RTC_OFFSET 0x920000
|
||||
#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80930000 - 0x8093FFFF: Syscon
|
||||
*/
|
||||
#define SYSCON_OFFSET 0x930000
|
||||
#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
|
||||
|
||||
/* Security */
|
||||
#define SECURITY_EXTENSIONID 0x80832714
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct syscon_regs {
|
||||
uint32_t pwrsts;
|
||||
uint32_t pwrcnt;
|
||||
uint32_t halt;
|
||||
uint32_t stby;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t teoi;
|
||||
uint32_t stfclr;
|
||||
uint32_t clkset1;
|
||||
uint32_t clkset2;
|
||||
uint32_t reserved1[6];
|
||||
uint32_t scratch0;
|
||||
uint32_t scratch1;
|
||||
uint32_t reserved2[2];
|
||||
uint32_t apbwait;
|
||||
uint32_t bustmstrarb;
|
||||
uint32_t bootmodeclr;
|
||||
uint32_t reserved3[9];
|
||||
uint32_t devicecfg;
|
||||
uint32_t vidclkdiv;
|
||||
uint32_t mirclkdiv;
|
||||
uint32_t i2sclkdiv;
|
||||
uint32_t keytchclkdiv;
|
||||
uint32_t chipid;
|
||||
uint32_t reserved4;
|
||||
uint32_t syscfg;
|
||||
uint32_t reserved5[8];
|
||||
uint32_t sysswlock;
|
||||
};
|
||||
#else
|
||||
#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
|
||||
#endif
|
||||
|
||||
#define SYSCON_OFF_CLKSET1 0x0020
|
||||
#define SYSCON_OFF_SYSCFG 0x009c
|
||||
|
||||
#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
|
||||
#define SYSCON_PWRCNT_USH_EN (1 << 28)
|
||||
|
||||
#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
|
||||
#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
|
||||
#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
|
||||
#define SYSCON_CLKSET_PLL_PS_SHIFT 16
|
||||
#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
|
||||
#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
|
||||
#define SYSCON_CLKSET1_NBYP1 (1 << 23)
|
||||
#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
|
||||
|
||||
#define SYSCON_CLKSET2_PLL2_EN (1 << 18)
|
||||
#define SYSCON_CLKSET2_NBYP2 (1 << 19)
|
||||
#define SYSCON_CLKSET2_USB_DIV_SHIFT 28
|
||||
|
||||
#define SYSCON_CHIPID_REV_MASK 0xF0000000
|
||||
#define SYSCON_DEVICECFG_SWRST (1 << 31)
|
||||
|
||||
#define SYSCON_SYSCFG_LASDO 0x00000020
|
||||
|
||||
/*
|
||||
* 0x80930000 - 0x8093FFFF: Watchdog Timer
|
||||
*/
|
||||
#define WATCHDOG_OFFSET 0x940000
|
||||
#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80950000 - 0x9000FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* During low_level init we store memory layout in memory at specific location
|
||||
*/
|
||||
#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
|
||||
#define UBOOT_MEMORYCNF_BANK_MASK 0x2004
|
||||
#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008
|
||||
24
u-boot/arch/arm/include/asm/arch-fsl-layerscape/clock.h
Normal file
24
u-boot/arch/arm/include/asm/arch-fsl-layerscape/clock.h
Normal file
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
|
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
|
||||
|
||||
#include <common.h>
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_BUS_CLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_DSPI_CLK,
|
||||
};
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
|
||||
236
u-boot/arch/arm/include/asm/arch-fsl-layerscape/config.h
Normal file
236
u-boot/arch/arm/include/asm/arch-fsl-layerscape/config.h
Normal file
@@ -0,0 +1,236 @@
|
||||
/*
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
|
||||
|
||||
#include <fsl_ddrc_version.h>
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LS1012A
|
||||
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Reserve secure memory
|
||||
* To be aligned with MMU block size
|
||||
*/
|
||||
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
|
||||
|
||||
#ifdef CONFIG_LS2080A
|
||||
#define CONFIG_MAX_CPUS 16
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 3
|
||||
#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
|
||||
#define SRDS_MAX_LANES 8
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_FSL_DDR_LE
|
||||
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
#define CONFIG_SYS_FSL_IFC_LE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_LE
|
||||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06100000
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* SEC */
|
||||
#define CONFIG_SYS_FSL_SEC_LE
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
|
||||
/* Cache Coherent Interconnect */
|
||||
#define CCI_MN_BASE 0x04000000
|
||||
#define CCI_MN_RNF_NODEID_LIST 0x180
|
||||
#define CCI_MN_DVM_DOMAIN_CTL 0x200
|
||||
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
|
||||
|
||||
#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
|
||||
#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
|
||||
#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
|
||||
#define CCN_HN_F_SAM_NODEID_MASK 0x7f
|
||||
#define CCN_HN_F_SAM_NODEID_DDR0 0x4
|
||||
#define CCN_HN_F_SAM_NODEID_DDR1 0xe
|
||||
|
||||
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
|
||||
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
|
||||
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
|
||||
#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
|
||||
#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
|
||||
#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
|
||||
|
||||
#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
|
||||
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
|
||||
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
|
||||
|
||||
#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
||||
|
||||
#define DCSR_CGACRE5 0x700070914ULL
|
||||
#define EPU_EPCMPR5 0x700060914ULL
|
||||
#define EPU_EPCCR5 0x700060814ULL
|
||||
#define EPU_EPSMCR5 0x700060228ULL
|
||||
#define EPU_EPECR5 0x700060314ULL
|
||||
#define EPU_EPCTR5 0x700060a14ULL
|
||||
#define EPU_EPGCR 0x700060000ULL
|
||||
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008336
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008511
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008514
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008585
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009635
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009663
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009801
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009803
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009942
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A010165
|
||||
|
||||
/* ARM A57 CORE ERRATA */
|
||||
#define CONFIG_ARM_ERRATA_826974
|
||||
#define CONFIG_ARM_ERRATA_828024
|
||||
#define CONFIG_ARM_ERRATA_829520
|
||||
#define CONFIG_ARM_ERRATA_833471
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#elif defined(CONFIG_LS1043A)
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 7
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
|
||||
#define CONFIG_SYS_FSL_DDR_BE
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_BE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
#define CONFIG_SYS_FSL_QSPI_BE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_BE
|
||||
|
||||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
#define CONFIG_SYS_FSL_SEC_BE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x09000000
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008850
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009663
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009929
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009942
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009660
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#elif defined(CONFIG_LS1012A)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
||||
#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
|
||||
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_BE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
#define CONFIG_SYS_FSL_QSPI_BE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_BE
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
#define CONFIG_SYS_FSL_SEC_BE
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
|
||||
275
u-boot/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Normal file
275
u-boot/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Normal file
@@ -0,0 +1,275 @@
|
||||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_CPU_H
|
||||
#define _FSL_LAYERSCAPE_CPU_H
|
||||
|
||||
static struct cpu_type cpu_type_list[] = {
|
||||
CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
|
||||
CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
|
||||
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
|
||||
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
|
||||
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
|
||||
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
|
||||
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
|
||||
};
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define SECTION_SHIFT_L0 39UL
|
||||
#define SECTION_SHIFT_L1 30UL
|
||||
#define SECTION_SHIFT_L2 21UL
|
||||
#define BLOCK_SIZE_L0 0x8000000000
|
||||
#define BLOCK_SIZE_L1 0x40000000
|
||||
#define BLOCK_SIZE_L2 0x200000
|
||||
#define NUM_OF_ENTRY 512
|
||||
#define TCR_EL2_PS_40BIT (2 << 16)
|
||||
|
||||
#define LAYERSCAPE_VA_BITS (40)
|
||||
#define LAYERSCAPE_TCR (TCR_TG0_4K | \
|
||||
TCR_EL2_PS_40BIT | \
|
||||
TCR_SHARED_NON | \
|
||||
TCR_ORGN_NC | \
|
||||
TCR_IRGN_NC | \
|
||||
TCR_T0SZ(LAYERSCAPE_VA_BITS))
|
||||
#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
|
||||
TCR_EL2_PS_40BIT | \
|
||||
TCR_SHARED_OUTER | \
|
||||
TCR_ORGN_WBWA | \
|
||||
TCR_IRGN_WBWA | \
|
||||
TCR_T0SZ(LAYERSCAPE_VA_BITS))
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
|
||||
#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
|
||||
#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_NI_BASE 0x810000000
|
||||
#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
|
||||
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
|
||||
#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
|
||||
#endif
|
||||
|
||||
struct sys_mmu_table {
|
||||
u64 virt_addr;
|
||||
u64 phys_addr;
|
||||
u64 size;
|
||||
u64 memory_type;
|
||||
u64 attribute;
|
||||
};
|
||||
|
||||
struct table_info {
|
||||
u64 *ptr;
|
||||
u64 table_base;
|
||||
u64 entry_size;
|
||||
};
|
||||
|
||||
static const struct sys_mmu_table early_mmu_table[] = {
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE},
|
||||
/* For IFC Region #1, only the first 4MB is cache-enabled */
|
||||
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
|
||||
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
|
||||
CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
|
||||
MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
|
||||
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct sys_mmu_table final_mmu_table[] = {
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE},
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
|
||||
CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
|
||||
CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
|
||||
CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
/* For QBMAN portal, only the first 64MB is cache-enabled */
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS },
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
#ifdef CONFIG_LS2080A
|
||||
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
#endif
|
||||
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
|
||||
CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
|
||||
CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
|
||||
CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
|
||||
CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
|
||||
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
int fsl_qoriq_core_to_cluster(unsigned int core);
|
||||
u32 cpu_mask(void);
|
||||
#endif /* _FSL_LAYERSCAPE_CPU_H */
|
||||
15
u-boot/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
Normal file
15
u-boot/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
|
||||
void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
|
||||
void append_mmu_masters(void *blob, const char *smmu_path,
|
||||
const char *master_name, u32 *stream_ids, int count);
|
||||
void fdt_fixup_smmu_pcie(void *blob);
|
||||
void fdt_fixup_board_enet(void *fdt);
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
|
||||
158
u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
Normal file
158
u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
Normal file
@@ -0,0 +1,158 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H__
|
||||
#define __FSL_SERDES_H__
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#ifdef CONFIG_LS2080A
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
SATA1,
|
||||
SATA2,
|
||||
XAUI1,
|
||||
XAUI2,
|
||||
XFI1,
|
||||
XFI2,
|
||||
XFI3,
|
||||
XFI4,
|
||||
XFI5,
|
||||
XFI6,
|
||||
XFI7,
|
||||
XFI8,
|
||||
SGMII1,
|
||||
SGMII2,
|
||||
SGMII3,
|
||||
SGMII4,
|
||||
SGMII5,
|
||||
SGMII6,
|
||||
SGMII7,
|
||||
SGMII8,
|
||||
SGMII9,
|
||||
SGMII10,
|
||||
SGMII11,
|
||||
SGMII12,
|
||||
SGMII13,
|
||||
SGMII14,
|
||||
SGMII15,
|
||||
SGMII16,
|
||||
QSGMII_A, /* A indicates MACs 1-4 */
|
||||
QSGMII_B, /* B indicates MACs 5-8 */
|
||||
QSGMII_C, /* C indicates MACs 9-12 */
|
||||
QSGMII_D, /* D indicates MACs 12-16 */
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
SATA1,
|
||||
SATA2,
|
||||
SRIO1,
|
||||
SRIO2,
|
||||
SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3,
|
||||
SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5,
|
||||
SGMII_FM1_DTSEC6,
|
||||
SGMII_FM1_DTSEC9,
|
||||
SGMII_FM1_DTSEC10,
|
||||
SGMII_FM2_DTSEC1,
|
||||
SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3,
|
||||
SGMII_FM2_DTSEC4,
|
||||
SGMII_FM2_DTSEC5,
|
||||
SGMII_FM2_DTSEC6,
|
||||
SGMII_FM2_DTSEC9,
|
||||
SGMII_FM2_DTSEC10,
|
||||
SGMII_TSEC1,
|
||||
SGMII_TSEC2,
|
||||
SGMII_TSEC3,
|
||||
SGMII_TSEC4,
|
||||
XAUI_FM1,
|
||||
XAUI_FM2,
|
||||
AURORA,
|
||||
CPRI1,
|
||||
CPRI2,
|
||||
CPRI3,
|
||||
CPRI4,
|
||||
CPRI5,
|
||||
CPRI6,
|
||||
CPRI7,
|
||||
CPRI8,
|
||||
XAUI_FM1_MAC9,
|
||||
XAUI_FM1_MAC10,
|
||||
XAUI_FM2_MAC9,
|
||||
XAUI_FM2_MAC10,
|
||||
HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC10,
|
||||
HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC10,
|
||||
QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
|
||||
QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
|
||||
QSGMII_FM2_A,
|
||||
QSGMII_FM2_B,
|
||||
XFI_FM1_MAC1,
|
||||
XFI_FM1_MAC2,
|
||||
XFI_FM1_MAC9,
|
||||
XFI_FM1_MAC10,
|
||||
XFI_FM2_MAC9,
|
||||
XFI_FM2_MAC10,
|
||||
INTERLAKEN,
|
||||
QSGMII_SW1_A, /* Indicates ports on L2 Switch */
|
||||
QSGMII_SW1_B,
|
||||
SGMII_2500_FM1_DTSEC1,
|
||||
SGMII_2500_FM1_DTSEC2,
|
||||
SGMII_2500_FM1_DTSEC3,
|
||||
SGMII_2500_FM1_DTSEC4,
|
||||
SGMII_2500_FM1_DTSEC5,
|
||||
SGMII_2500_FM1_DTSEC6,
|
||||
SGMII_2500_FM1_DTSEC9,
|
||||
SGMII_2500_FM1_DTSEC10,
|
||||
SGMII_2500_FM2_DTSEC1,
|
||||
SGMII_2500_FM2_DTSEC2,
|
||||
SGMII_2500_FM2_DTSEC3,
|
||||
SGMII_2500_FM2_DTSEC4,
|
||||
SGMII_2500_FM2_DTSEC5,
|
||||
SGMII_2500_FM2_DTSEC6,
|
||||
SGMII_2500_FM2_DTSEC9,
|
||||
SGMII_2500_FM2_DTSEC10,
|
||||
TX_CLK,
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
void fsl_serdes_init(void);
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
|
||||
|
||||
#ifdef CONFIG_LS1043A
|
||||
const char *serdes_clock_to_string(u32 clock);
|
||||
int get_serdes_protocol(void);
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_SERDES_H__ */
|
||||
601
u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Normal file
601
u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Normal file
@@ -0,0 +1,601 @@
|
||||
/*
|
||||
* Copyright 2013-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_FSL_LSCH2_IMMAP_H__
|
||||
#define __ARCH_FSL_LSCH2_IMMAP_H__
|
||||
|
||||
#include <fsl_immap.h>
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_DCSRBAR 0x20000000
|
||||
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
|
||||
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
|
||||
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
|
||||
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
|
||||
#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
|
||||
#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
|
||||
#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
|
||||
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
|
||||
|
||||
#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
|
||||
|
||||
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
|
||||
|
||||
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
|
||||
|
||||
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
|
||||
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
|
||||
/* LUT registers */
|
||||
#ifdef CONFIG_LS1012A
|
||||
#define PCIE_LUT_BASE 0xC0000
|
||||
#else
|
||||
#define PCIE_LUT_BASE 0x10000
|
||||
#endif
|
||||
#define PCIE_LUT_LCTRL0 0x7F8
|
||||
#define PCIE_LUT_DBG 0x7FC
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
|
||||
#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
|
||||
/*
|
||||
* Define default values for some CCSR macros to make header files cleaner*
|
||||
*
|
||||
* To completely disable CCSR relocation in a board header file, define
|
||||
* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
|
||||
* to a value that is the same as CONFIG_SYS_CCSRBAR.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_CCSRBAR_PHYS
|
||||
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
|
||||
CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
|
||||
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
||||
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR
|
||||
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
|
||||
CONFIG_SYS_CCSRBAR_PHYS_LOW)
|
||||
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
unsigned long freq_localbus;
|
||||
unsigned long freq_sdhc;
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
|
||||
#endif
|
||||
unsigned long freq_qman;
|
||||
};
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
|
||||
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
|
||||
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
|
||||
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
|
||||
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
|
||||
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
|
||||
#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
|
||||
#define CONFIG_SYS_FSL_FM1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
|
||||
/* Device Configuration and Pin Control */
|
||||
struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2;
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
u8 res_02c[0x70-0x2c];
|
||||
u32 devdisr; /* Device disable control */
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
u32 devdisr4; /* Device disable control 4 */
|
||||
u32 devdisr5; /* Device disable control 5 */
|
||||
u32 devdisr6; /* Device disable control 6 */
|
||||
u32 devdisr7; /* Device disable control 7 */
|
||||
u8 res_08c[0x94-0x8c];
|
||||
u32 coredisru; /* uppper portion for support of 64 cores */
|
||||
u32 coredisrl; /* lower portion for support of 64 cores */
|
||||
u8 res_09c[0xa0-0x9c];
|
||||
u32 pvr; /* Processor version */
|
||||
u32 svr; /* System version */
|
||||
u32 mvr; /* Manufacturing version */
|
||||
u8 res_0ac[0xb0-0xac];
|
||||
u32 rstcr; /* Reset control */
|
||||
u32 rstrqpblsr; /* Reset request preboot loader status */
|
||||
u8 res_0b8[0xc0-0xb8];
|
||||
u32 rstrqmr1; /* Reset request mask */
|
||||
u8 res_0c4[0xc8-0xc4];
|
||||
u32 rstrqsr1; /* Reset request status */
|
||||
u8 res_0cc[0xd4-0xcc];
|
||||
u32 rstrqwdtmrl; /* Reset request WDT mask */
|
||||
u8 res_0d8[0xdc-0xd8];
|
||||
u32 rstrqwdtsrl; /* Reset request WDT status */
|
||||
u8 res_0e0[0xe4-0xe0];
|
||||
u32 brrl; /* Boot release */
|
||||
u8 res_0e8[0x100-0xe8];
|
||||
u32 rcwsr[16]; /* Reset control word status */
|
||||
#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
|
||||
#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
|
||||
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
|
||||
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
|
||||
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
|
||||
#define RCW_SB_EN_REG_INDEX 7
|
||||
#define RCW_SB_EN_MASK 0x00200000
|
||||
|
||||
u8 res_140[0x200-0x140];
|
||||
u32 scratchrw[4]; /* Scratch Read/Write */
|
||||
u8 res_210[0x300-0x210];
|
||||
u32 scratchw1r[4]; /* Scratch Read (Write once) */
|
||||
u8 res_310[0x400-0x310];
|
||||
u32 crstsr[12];
|
||||
u8 res_430[0x500-0x430];
|
||||
|
||||
/* PCI Express n Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_pex1liodnr;
|
||||
u32 dcfg_ccsr_pex2liodnr;
|
||||
u32 dcfg_ccsr_pex3liodnr;
|
||||
u32 dcfg_ccsr_pex4liodnr;
|
||||
/* RIO n Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_rio1liodnr;
|
||||
u32 dcfg_ccsr_rio2liodnr;
|
||||
u32 dcfg_ccsr_rio3liodnr;
|
||||
u32 dcfg_ccsr_rio4liodnr;
|
||||
/* USB Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_usb1liodnr;
|
||||
u32 dcfg_ccsr_usb2liodnr;
|
||||
u32 dcfg_ccsr_usb3liodnr;
|
||||
u32 dcfg_ccsr_usb4liodnr;
|
||||
/* SD/MMC Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_sdmmc1liodnr;
|
||||
u32 dcfg_ccsr_sdmmc2liodnr;
|
||||
u32 dcfg_ccsr_sdmmc3liodnr;
|
||||
u32 dcfg_ccsr_sdmmc4liodnr;
|
||||
/* RIO Message Unit Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_riomaintliodnr;
|
||||
|
||||
u8 res_544[0x550-0x544];
|
||||
u32 sataliodnr[4];
|
||||
u8 res_560[0x570-0x560];
|
||||
|
||||
u32 dcfg_ccsr_misc1liodnr;
|
||||
u32 dcfg_ccsr_misc2liodnr;
|
||||
u32 dcfg_ccsr_misc3liodnr;
|
||||
u32 dcfg_ccsr_misc4liodnr;
|
||||
u32 dcfg_ccsr_dma1liodnr;
|
||||
u32 dcfg_ccsr_dma2liodnr;
|
||||
u32 dcfg_ccsr_dma3liodnr;
|
||||
u32 dcfg_ccsr_dma4liodnr;
|
||||
u32 dcfg_ccsr_spare1liodnr;
|
||||
u32 dcfg_ccsr_spare2liodnr;
|
||||
u32 dcfg_ccsr_spare3liodnr;
|
||||
u32 dcfg_ccsr_spare4liodnr;
|
||||
u8 res_5a0[0x600-0x5a0];
|
||||
u32 dcfg_ccsr_pblsr;
|
||||
|
||||
u32 pamubypenr;
|
||||
u32 dmacr1;
|
||||
|
||||
u8 res_60c[0x610-0x60c];
|
||||
u32 dcfg_ccsr_gensr1;
|
||||
u32 dcfg_ccsr_gensr2;
|
||||
u32 dcfg_ccsr_gensr3;
|
||||
u32 dcfg_ccsr_gensr4;
|
||||
u32 dcfg_ccsr_gencr1;
|
||||
u32 dcfg_ccsr_gencr2;
|
||||
u32 dcfg_ccsr_gencr3;
|
||||
u32 dcfg_ccsr_gencr4;
|
||||
u32 dcfg_ccsr_gencr5;
|
||||
u32 dcfg_ccsr_gencr6;
|
||||
u32 dcfg_ccsr_gencr7;
|
||||
u8 res_63c[0x658-0x63c];
|
||||
u32 dcfg_ccsr_cgensr1;
|
||||
u32 dcfg_ccsr_cgensr0;
|
||||
u8 res_660[0x678-0x660];
|
||||
u32 dcfg_ccsr_cgencr1;
|
||||
|
||||
u32 dcfg_ccsr_cgencr0;
|
||||
u8 res_680[0x700-0x680];
|
||||
u32 dcfg_ccsr_sriopstecr;
|
||||
u32 dcfg_ccsr_dcsrcr;
|
||||
|
||||
u8 res_708[0x740-0x708]; /* add more registers when needed */
|
||||
u32 tp_ityp[64]; /* Topology Initiator Type Register */
|
||||
struct {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
} tp_cluster[16];
|
||||
u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
|
||||
u32 dcfg_ccsr_qmbm_warmrst;
|
||||
u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
|
||||
u32 dcfg_ccsr_reserved0;
|
||||
u32 dcfg_ccsr_reserved1;
|
||||
};
|
||||
|
||||
#define SCFG_QSPI_CLKSEL 0x40100000
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
|
||||
#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
|
||||
#define SCFG_USBPWRFAULT_SHARED 0x00000001
|
||||
#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
|
||||
#define SCFG_USBPWRFAULT_USB3_SHIFT 4
|
||||
#define SCFG_USBPWRFAULT_USB2_SHIFT 2
|
||||
#define SCFG_USBPWRFAULT_USB1_SHIFT 0
|
||||
|
||||
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
|
||||
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
|
||||
|
||||
/* Supplemental Configuration Unit */
|
||||
struct ccsr_scfg {
|
||||
u8 res_000[0x100-0x000];
|
||||
u32 usb2_icid;
|
||||
u32 usb3_icid;
|
||||
u8 res_108[0x114-0x108];
|
||||
u32 dma_icid;
|
||||
u32 sata_icid;
|
||||
u32 usb1_icid;
|
||||
u32 qe_icid;
|
||||
u32 sdhc_icid;
|
||||
u32 edma_icid;
|
||||
u32 etr_icid;
|
||||
u32 core_sft_rst[4];
|
||||
u8 res_140[0x158-0x140];
|
||||
u32 altcbar;
|
||||
u32 qspi_cfg;
|
||||
u8 res_160[0x180-0x160];
|
||||
u32 dmamcr;
|
||||
u8 res_184[0x18c-0x184];
|
||||
u32 debug_icid;
|
||||
u8 res_190[0x1a4-0x190];
|
||||
u32 snpcnfgcr;
|
||||
u8 res_1a8[0x1ac-0x1a8];
|
||||
u32 intpcr;
|
||||
u8 res_1b0[0x204-0x1b0];
|
||||
u32 coresrencr;
|
||||
u8 res_208[0x220-0x208];
|
||||
u32 rvbar0_0;
|
||||
u32 rvbar0_1;
|
||||
u32 rvbar1_0;
|
||||
u32 rvbar1_1;
|
||||
u32 rvbar2_0;
|
||||
u32 rvbar2_1;
|
||||
u32 rvbar3_0;
|
||||
u32 rvbar3_1;
|
||||
u32 lpmcsr;
|
||||
u8 res_244[0x400-0x244];
|
||||
u32 qspidqscr;
|
||||
u32 ecgtxcmcr;
|
||||
u32 sdhciovselcr;
|
||||
u32 rcwpmuxcr0;
|
||||
u32 usbdrvvbus_selcr;
|
||||
u32 usbpwrfault_selcr;
|
||||
u32 usb_refclk_selcr1;
|
||||
u32 usb_refclk_selcr2;
|
||||
u32 usb_refclk_selcr3;
|
||||
u8 res_424[0x600-0x424];
|
||||
u32 scratchrw[4];
|
||||
u8 res_610[0x680-0x610];
|
||||
u32 corebcr;
|
||||
u8 res_684[0x1000-0x684];
|
||||
u32 pex1msiir;
|
||||
u32 pex1msir;
|
||||
u8 res_1008[0x2000-0x1008];
|
||||
u32 pex2;
|
||||
u32 pex2msir;
|
||||
u8 res_2008[0x3000-0x2008];
|
||||
u32 pex3msiir;
|
||||
u32 pex3msir;
|
||||
};
|
||||
|
||||
/* Clocking */
|
||||
struct ccsr_clk {
|
||||
struct {
|
||||
u32 clkcncsr; /* core cluster n clock control status */
|
||||
u8 res_004[0x0c];
|
||||
u32 clkcghwacsr; /* Clock generator n hardware accelerator */
|
||||
u8 res_014[0x0c];
|
||||
} clkcsr[4];
|
||||
u8 res_040[0x780]; /* 0x100 */
|
||||
struct {
|
||||
u32 pllcngsr;
|
||||
u8 res_804[0x1c];
|
||||
} pllcgsr[2];
|
||||
u8 res_840[0x1c0];
|
||||
u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
|
||||
u8 res_a04[0x1fc];
|
||||
u32 pllpgsr; /* 0xc00 Platform PLL General Status */
|
||||
u8 res_c04[0x1c];
|
||||
u32 plldgsr; /* 0xc20 DDR PLL General Status */
|
||||
u8 res_c24[0x3dc];
|
||||
};
|
||||
|
||||
/* System Counter */
|
||||
struct sctr_regs {
|
||||
u32 cntcr;
|
||||
u32 cntsr;
|
||||
u32 cntcv1;
|
||||
u32 cntcv2;
|
||||
u32 resv1[4];
|
||||
u32 cntfid0;
|
||||
u32 cntfid1;
|
||||
u32 resv2[1002];
|
||||
u32 counterid[12];
|
||||
};
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
struct ccsr_serdes {
|
||||
struct {
|
||||
u32 rstctl; /* Reset Control Register */
|
||||
#define SRDS_RSTCTL_RST 0x80000000
|
||||
#define SRDS_RSTCTL_RSTDONE 0x40000000
|
||||
#define SRDS_RSTCTL_RSTERR 0x20000000
|
||||
#define SRDS_RSTCTL_SWRST 0x10000000
|
||||
#define SRDS_RSTCTL_SDEN 0x00000020
|
||||
#define SRDS_RSTCTL_SDRST_B 0x00000040
|
||||
#define SRDS_RSTCTL_PLLRST_B 0x00000080
|
||||
u32 pllcr0; /* PLL Control Register 0 */
|
||||
#define SRDS_PLLCR0_POFF 0x80000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
|
||||
#define SRDS_PLLCR0_PLL_LCK 0x00800000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
|
||||
u32 pllcr1; /* PLL Control Register 1 */
|
||||
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
|
||||
u32 res_0c; /* 0x00c */
|
||||
u32 pllcr3;
|
||||
u32 pllcr4;
|
||||
u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
|
||||
u8 res_1c[0x20-0x1c];
|
||||
} bank[2];
|
||||
u8 res_40[0x90-0x40];
|
||||
u32 srdstcalcr; /* 0x90 TX Calibration Control */
|
||||
u8 res_94[0xa0-0x94];
|
||||
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
|
||||
u8 res_a4[0xb0-0xa4];
|
||||
u32 srdsgr0; /* 0xb0 General Register 0 */
|
||||
u8 res_b4[0x100-0xb4];
|
||||
struct {
|
||||
u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */
|
||||
u8 res_104[0x120-0x104];
|
||||
} lnpssr[4]; /* Lane A, B, C, D */
|
||||
u8 res_180[0x200-0x180];
|
||||
u32 srdspccr0; /* 0x200 Protocol Configuration 0 */
|
||||
u32 srdspccr1; /* 0x204 Protocol Configuration 1 */
|
||||
u32 srdspccr2; /* 0x208 Protocol Configuration 2 */
|
||||
u32 srdspccr3; /* 0x20c Protocol Configuration 3 */
|
||||
u32 srdspccr4; /* 0x210 Protocol Configuration 4 */
|
||||
u32 srdspccr5; /* 0x214 Protocol Configuration 5 */
|
||||
u32 srdspccr6; /* 0x218 Protocol Configuration 6 */
|
||||
u32 srdspccr7; /* 0x21c Protocol Configuration 7 */
|
||||
u32 srdspccr8; /* 0x220 Protocol Configuration 8 */
|
||||
u32 srdspccr9; /* 0x224 Protocol Configuration 9 */
|
||||
u32 srdspccra; /* 0x228 Protocol Configuration A */
|
||||
u32 srdspccrb; /* 0x22c Protocol Configuration B */
|
||||
u8 res_230[0x800-0x230];
|
||||
struct {
|
||||
u32 gcr0; /* 0x800 General Control Register 0 */
|
||||
u32 gcr1; /* 0x804 General Control Register 1 */
|
||||
u32 gcr2; /* 0x808 General Control Register 2 */
|
||||
u32 sscr0;
|
||||
u32 recr0; /* 0x810 Receive Equalization Control */
|
||||
u32 recr1;
|
||||
u32 tecr0; /* 0x818 Transmit Equalization Control */
|
||||
u32 sscr1;
|
||||
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
|
||||
u8 res_824[0x83c-0x824];
|
||||
u32 tcsr3;
|
||||
} lane[4]; /* Lane A, B, C, D */
|
||||
u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */
|
||||
struct {
|
||||
u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
|
||||
u8 res_1004[0x1040-0x1004];
|
||||
} pcie[3];
|
||||
u8 res_10c0[0x1800-0x10c0];
|
||||
struct {
|
||||
u8 res_1800[0x1804-0x1800];
|
||||
u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */
|
||||
u8 res_1808[0x180c-0x1808];
|
||||
u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */
|
||||
} sgmii[4]; /* Lane A, B, C, D */
|
||||
u8 res_1840[0x1880-0x1840];
|
||||
struct {
|
||||
u8 res_1880[0x1884-0x1880];
|
||||
u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */
|
||||
u8 res_1888[0x188c-0x1888];
|
||||
u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */
|
||||
} qsgmii[2]; /* Lane A, B */
|
||||
u8 res_18a0[0x1980-0x18a0];
|
||||
struct {
|
||||
u8 res_1980[0x1984-0x1980];
|
||||
u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
|
||||
u8 res_1988[0x198c-0x1988];
|
||||
u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
|
||||
} xfi[2]; /* Lane A, B */
|
||||
u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
|
||||
};
|
||||
|
||||
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
|
||||
#define CCI400_CTRLORD_EN_BARRIER 0
|
||||
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
|
||||
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
|
||||
#define CCI400_SNOOP_REQ_EN 0x00000001
|
||||
|
||||
/* CCI-400 registers */
|
||||
struct ccsr_cci400 {
|
||||
u32 ctrl_ord; /* Control Override */
|
||||
u32 spec_ctrl; /* Speculation Control */
|
||||
u32 secure_access; /* Secure Access */
|
||||
u32 status; /* Status */
|
||||
u32 impr_err; /* Imprecise Error */
|
||||
u8 res_14[0x100 - 0x14];
|
||||
u32 pmcr; /* Performance Monitor Control */
|
||||
u8 res_104[0xfd0 - 0x104];
|
||||
u32 pid[8]; /* Peripheral ID */
|
||||
u32 cid[4]; /* Component ID */
|
||||
struct {
|
||||
u32 snoop_ctrl; /* Snoop Control */
|
||||
u32 sha_ord; /* Shareable Override */
|
||||
u8 res_1008[0x1100 - 0x1008];
|
||||
u32 rc_qos_ord; /* read channel QoS Value Override */
|
||||
u32 wc_qos_ord; /* read channel QoS Value Override */
|
||||
u8 res_1108[0x110c - 0x1108];
|
||||
u32 qos_ctrl; /* QoS Control */
|
||||
u32 max_ot; /* Max OT */
|
||||
u8 res_1114[0x1130 - 0x1114];
|
||||
u32 target_lat; /* Target Latency */
|
||||
u32 latency_regu; /* Latency Regulation */
|
||||
u32 qos_range; /* QoS Range */
|
||||
u8 res_113c[0x2000 - 0x113c];
|
||||
} slave[5]; /* Slave Interface */
|
||||
u8 res_6000[0x9004 - 0x6000];
|
||||
u32 cycle_counter; /* Cycle counter */
|
||||
u32 count_ctrl; /* Count Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_9010[0xa000 - 0x9010];
|
||||
struct {
|
||||
u32 event_select; /* Event Select */
|
||||
u32 event_count; /* Event Count */
|
||||
u32 counter_ctrl; /* Counter Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_a010[0xb000 - 0xa010];
|
||||
} pcounter[4]; /* Performance Counter */
|
||||
u8 res_e004[0x10000 - 0xe004];
|
||||
};
|
||||
|
||||
/* MMU 500 */
|
||||
#define SMMU_SCR0 (SMMU_BASE + 0x0)
|
||||
#define SMMU_SCR1 (SMMU_BASE + 0x4)
|
||||
#define SMMU_SCR2 (SMMU_BASE + 0x8)
|
||||
#define SMMU_SACR (SMMU_BASE + 0x10)
|
||||
#define SMMU_IDR0 (SMMU_BASE + 0x20)
|
||||
#define SMMU_IDR1 (SMMU_BASE + 0x24)
|
||||
|
||||
#define SMMU_NSCR0 (SMMU_BASE + 0x400)
|
||||
#define SMMU_NSCR2 (SMMU_BASE + 0x408)
|
||||
#define SMMU_NSACR (SMMU_BASE + 0x410)
|
||||
|
||||
#define SCR0_CLIENTPD_MASK 0x00000001
|
||||
#define SCR0_USFCFG_MASK 0x00000400
|
||||
|
||||
uint get_svr(void);
|
||||
|
||||
#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
|
||||
330
u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
Normal file
330
u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
Normal file
@@ -0,0 +1,330 @@
|
||||
/*
|
||||
* LayerScape Internal Memory Map
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
#define __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
|
||||
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
|
||||
0x18A0)
|
||||
#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
|
||||
|
||||
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
|
||||
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
|
||||
|
||||
/* SP (Cortex-A5) related */
|
||||
#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
|
||||
#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
|
||||
|
||||
#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
/* SATA */
|
||||
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
|
||||
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
|
||||
|
||||
/* SEC */
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
|
||||
|
||||
/* MMU 500 */
|
||||
#define SMMU_SCR0 (SMMU_BASE + 0x0)
|
||||
#define SMMU_SCR1 (SMMU_BASE + 0x4)
|
||||
#define SMMU_SCR2 (SMMU_BASE + 0x8)
|
||||
#define SMMU_SACR (SMMU_BASE + 0x10)
|
||||
#define SMMU_IDR0 (SMMU_BASE + 0x20)
|
||||
#define SMMU_IDR1 (SMMU_BASE + 0x24)
|
||||
|
||||
#define SMMU_NSCR0 (SMMU_BASE + 0x400)
|
||||
#define SMMU_NSCR2 (SMMU_BASE + 0x408)
|
||||
#define SMMU_NSACR (SMMU_BASE + 0x410)
|
||||
|
||||
#define SCR0_CLIENTPD_MASK 0x00000001
|
||||
#define SCR0_USFCFG_MASK 0x00000400
|
||||
|
||||
|
||||
/* PCIe */
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
|
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
|
||||
/* LUT registers */
|
||||
#define PCIE_LUT_BASE 0x80000
|
||||
#define PCIE_LUT_LCTRL0 0x7F8
|
||||
#define PCIE_LUT_DBG 0x7FC
|
||||
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
|
||||
#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
|
||||
#define PCIE_LUT_ENABLE (1 << 31)
|
||||
#define PCIE_LUT_ENTRY_COUNT 32
|
||||
|
||||
/* Device Configuration */
|
||||
#define DCFG_BASE 0x01e00000
|
||||
#define DCFG_PORSR1 0x000
|
||||
#define DCFG_PORSR1_RCW_SRC 0xff800000
|
||||
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
|
||||
#define DCFG_RCWSR13 0x130
|
||||
#define DCFG_RCWSR13_DSPI (0 << 8)
|
||||
#define DCFG_RCWSR15 0x138
|
||||
#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
|
||||
|
||||
#define DCFG_DCSR_BASE 0X700100000ULL
|
||||
#define DCFG_DCSR_PORCR1 0x000
|
||||
|
||||
/* Interrupt Sampling Control */
|
||||
#define ISC_BASE 0x01F70000
|
||||
#define IRQCR_OFFSET 0x14
|
||||
|
||||
/* Supplemental Configuration */
|
||||
#define SCFG_BASE 0x01fc0000
|
||||
#define SCFG_USB3PRM1CR 0x000
|
||||
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
|
||||
#define SCFG_QSPICLKCTLR 0x10
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
|
||||
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
/* This is chassis generation 3 */
|
||||
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||
unsigned long freq_ddrbus2;
|
||||
#endif
|
||||
unsigned long freq_localbus;
|
||||
unsigned long freq_qe;
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
unsigned long freq_qman;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DPAA_PME
|
||||
unsigned long freq_pme;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Global Utilities Block */
|
||||
struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2; /* General-purpose POR configuration 2 */
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
u32 gpporcr3;
|
||||
u32 gpporcr4;
|
||||
u8 res_034[0x70-0x34];
|
||||
u32 devdisr; /* Device disable control */
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
u32 devdisr4; /* Device disable control 4 */
|
||||
u32 devdisr5; /* Device disable control 5 */
|
||||
u32 devdisr6; /* Device disable control 6 */
|
||||
u32 devdisr7; /* Device disable control 7 */
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
|
||||
u8 res_08c[0x90-0x8c];
|
||||
u32 coredisru; /* uppper portion for support of 64 cores */
|
||||
u32 coredisrl; /* lower portion for support of 64 cores */
|
||||
u8 res_098[0xa0-0x98];
|
||||
u32 pvr; /* Processor version */
|
||||
u32 svr; /* System version */
|
||||
u32 mvr; /* Manufacturing version */
|
||||
u8 res_0ac[0x100-0xac];
|
||||
u32 rcwsr[32]; /* Reset control word status */
|
||||
|
||||
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
|
||||
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
|
||||
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
|
||||
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
|
||||
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
|
||||
#define RCW_SB_EN_REG_INDEX 9
|
||||
#define RCW_SB_EN_MASK 0x00000400
|
||||
|
||||
u8 res_180[0x200-0x180];
|
||||
u32 scratchrw[32]; /* Scratch Read/Write */
|
||||
u8 res_280[0x300-0x280];
|
||||
u32 scratchw1r[4]; /* Scratch Read (Write once) */
|
||||
u8 res_310[0x400-0x310];
|
||||
u32 bootlocptrl; /* Boot location pointer low-order addr */
|
||||
u32 bootlocptrh; /* Boot location pointer high-order addr */
|
||||
u8 res_408[0x500-0x408];
|
||||
u8 res_500[0x740-0x500]; /* add more registers when needed */
|
||||
u32 tp_ityp[64]; /* Topology Initiator Type Register */
|
||||
struct {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
} tp_cluster[3]; /* Core Cluster n Topology Register */
|
||||
u8 res_858[0x1000-0x858];
|
||||
};
|
||||
|
||||
|
||||
struct ccsr_clk_cluster_group {
|
||||
struct {
|
||||
u8 res_00[0x10];
|
||||
u32 csr;
|
||||
u8 res_14[0x20-0x14];
|
||||
} hwncsr[3];
|
||||
u8 res_60[0x80-0x60];
|
||||
struct {
|
||||
u32 gsr;
|
||||
u8 res_84[0xa0-0x84];
|
||||
} pllngsr[3];
|
||||
u8 res_e0[0x100-0xe0];
|
||||
};
|
||||
|
||||
struct ccsr_clk_ctrl {
|
||||
struct {
|
||||
u32 csr; /* core cluster n clock control status */
|
||||
u8 res_04[0x20-0x04];
|
||||
} clkcncsr[8];
|
||||
};
|
||||
|
||||
struct ccsr_reset {
|
||||
u32 rstcr; /* 0x000 */
|
||||
u32 rstcrsp; /* 0x004 */
|
||||
u8 res_008[0x10-0x08]; /* 0x008 */
|
||||
u32 rstrqmr1; /* 0x010 */
|
||||
u32 rstrqmr2; /* 0x014 */
|
||||
u32 rstrqsr1; /* 0x018 */
|
||||
u32 rstrqsr2; /* 0x01c */
|
||||
u32 rstrqwdtmrl; /* 0x020 */
|
||||
u32 rstrqwdtmru; /* 0x024 */
|
||||
u8 res_028[0x30-0x28]; /* 0x028 */
|
||||
u32 rstrqwdtsrl; /* 0x030 */
|
||||
u32 rstrqwdtsru; /* 0x034 */
|
||||
u8 res_038[0x60-0x38]; /* 0x038 */
|
||||
u32 brrl; /* 0x060 */
|
||||
u32 brru; /* 0x064 */
|
||||
u8 res_068[0x80-0x68]; /* 0x068 */
|
||||
u32 pirset; /* 0x080 */
|
||||
u32 pirclr; /* 0x084 */
|
||||
u8 res_088[0x90-0x88]; /* 0x088 */
|
||||
u32 brcorenbr; /* 0x090 */
|
||||
u8 res_094[0x100-0x94]; /* 0x094 */
|
||||
u32 rcw_reqr; /* 0x100 */
|
||||
u32 rcw_completion; /* 0x104 */
|
||||
u8 res_108[0x110-0x108]; /* 0x108 */
|
||||
u32 pbi_reqr; /* 0x110 */
|
||||
u32 pbi_completion; /* 0x114 */
|
||||
u8 res_118[0xa00-0x118]; /* 0x118 */
|
||||
u32 qmbm_warmrst; /* 0xa00 */
|
||||
u32 soc_warmrst; /* 0xa04 */
|
||||
u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
|
||||
u32 ip_rev1; /* 0xbf8 */
|
||||
u32 ip_rev2; /* 0xbfc */
|
||||
};
|
||||
|
||||
uint get_svr(void);
|
||||
|
||||
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
|
||||
55
u-boot/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
Normal file
55
u-boot/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
|
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#ifdef CONFIG_FSL_LPUART
|
||||
#ifdef CONFIG_LPUART_32B_REG
|
||||
struct lpuart_fsl {
|
||||
u32 baud;
|
||||
u32 stat;
|
||||
u32 ctrl;
|
||||
u32 data;
|
||||
u32 match;
|
||||
u32 modir;
|
||||
u32 fifo;
|
||||
u32 water;
|
||||
};
|
||||
#else
|
||||
struct lpuart_fsl {
|
||||
u8 ubdh;
|
||||
u8 ubdl;
|
||||
u8 uc1;
|
||||
u8 uc2;
|
||||
u8 us1;
|
||||
u8 us2;
|
||||
u8 uc3;
|
||||
u8 ud;
|
||||
u8 uma1;
|
||||
u8 uma2;
|
||||
u8 uc4;
|
||||
u8 uc5;
|
||||
u8 ued;
|
||||
u8 umodem;
|
||||
u8 uir;
|
||||
u8 reserved;
|
||||
u8 upfifo;
|
||||
u8 ucfifo;
|
||||
u8 usfifo;
|
||||
u8 utwfifo;
|
||||
u8 utcfifo;
|
||||
u8 urwfifo;
|
||||
u8 urcfifo;
|
||||
u8 rsvd[28];
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_FSL_LPUART */
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
|
||||
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
#ifndef __FSL_STREAM_ID_H
|
||||
#define __FSL_STREAM_ID_H
|
||||
|
||||
/*
|
||||
* Stream IDs on ls2080a devices are not hardwired and are
|
||||
* programmed by sw. There are a limited number of stream IDs
|
||||
* available, and the partitioning of them is scenario dependent.
|
||||
* This header defines the partitioning between legacy, PCI,
|
||||
* and DPAA2 devices.
|
||||
*
|
||||
* This partitioning can be customized in this file depending
|
||||
* on the specific hardware config:
|
||||
*
|
||||
* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
|
||||
* -all legacy devices get a unique stream ID assigned and programmed in
|
||||
* their AMQR registers by u-boot
|
||||
*
|
||||
* -PCIe
|
||||
* -there is a range of stream IDs set aside for PCI in this
|
||||
* file. U-boot will scan the PCI bus and for each device discovered:
|
||||
* -allocate a streamID
|
||||
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
|
||||
* -set a msi-map entry in the PEXn controller node in the
|
||||
* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
|
||||
* for more info on the msi-map definition)
|
||||
*
|
||||
* -DPAA2
|
||||
* -u-boot will allocate a range of stream IDs to be used by the Management
|
||||
* Complex for containers and will set these values in the MC DPC image.
|
||||
* -the MC is responsible for allocating and setting up 'isolation context
|
||||
* IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
|
||||
*
|
||||
* On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
|
||||
* each of the different bus masters. The relationship between
|
||||
* the AMQ registers and stream IDs is defined in the table below:
|
||||
* AMQ bit streamID bit
|
||||
* ---------------------------
|
||||
* PL[18] 9 // privilege bit
|
||||
* BMT[17] 8 // bypass translation
|
||||
* VA[16] 7 // reserved
|
||||
* [15] - // unused
|
||||
* ICID[14:7] - // unused
|
||||
* ICID[6:0] 6-0 // isolation context id
|
||||
* ----------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
|
||||
#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
|
||||
|
||||
#define FSL_INVALID_STREAM_ID 0
|
||||
|
||||
#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
|
||||
|
||||
/* legacy devices */
|
||||
#define FSL_USB1_STREAM_ID 1
|
||||
#define FSL_USB2_STREAM_ID 2
|
||||
#define FSL_SDMMC_STREAM_ID 3
|
||||
#define FSL_SATA1_STREAM_ID 4
|
||||
#define FSL_SATA2_STREAM_ID 5
|
||||
#define FSL_DMA_STREAM_ID 6
|
||||
|
||||
/* PCI - programmed in PEXn_LUT */
|
||||
#define FSL_PEX_STREAM_ID_START 7
|
||||
#define FSL_PEX_STREAM_ID_END 22
|
||||
|
||||
/* DPAA2 - set in MC DPC and alloced by MC */
|
||||
#define FSL_DPAA2_STREAM_ID_START 23
|
||||
#define FSL_DPAA2_STREAM_ID_END 63
|
||||
|
||||
#endif
|
||||
10
u-boot/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
Normal file
10
u-boot/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
|
||||
#include <asm/arch-armv8/mmu.h>
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
|
||||
38
u-boot/arch/arm/include/asm/arch-fsl-layerscape/mp.h
Normal file
38
u-boot/arch/arm/include/asm/arch-fsl-layerscape/mp.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_MP_H
|
||||
#define _FSL_LAYERSCAPE_MP_H
|
||||
|
||||
/*
|
||||
* Each spin table element is defined as
|
||||
* struct {
|
||||
* uint64_t entry_addr;
|
||||
* uint64_t status;
|
||||
* uint64_t lpid;
|
||||
* };
|
||||
* we pad this struct to 64 bytes so each entry is in its own cacheline
|
||||
* the actual spin table is an array of these structures
|
||||
*/
|
||||
#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
|
||||
#define SPIN_TABLE_ELEM_STATUS_IDX 1
|
||||
#define SPIN_TABLE_ELEM_LPID_IDX 2
|
||||
#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
|
||||
#define SPIN_TABLE_ELEM_SIZE 64
|
||||
|
||||
#define id_to_core(x) ((x & 3) | (x >> 6))
|
||||
#ifndef __ASSEMBLY__
|
||||
extern u64 __spin_table[];
|
||||
extern u64 __real_cntfrq;
|
||||
extern u64 *secondary_boot_code;
|
||||
extern size_t __secondary_boot_code_size;
|
||||
int fsl_layerscape_wake_seconday_cores(void);
|
||||
void *get_spin_tbl_addr(void);
|
||||
phys_addr_t determine_mp_bootpg(void);
|
||||
void secondary_boot_func(void);
|
||||
int is_core_online(u64 cpu_id);
|
||||
#endif
|
||||
#endif /* _FSL_LAYERSCAPE_MP_H */
|
||||
168
u-boot/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
Normal file
168
u-boot/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
Normal file
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_NS_ACCESS_H_
|
||||
#define __FSL_NS_ACCESS_H_
|
||||
|
||||
enum csu_cslx_ind {
|
||||
CSU_CSLX_PCIE2_IO = 0,
|
||||
CSU_CSLX_PCIE1_IO,
|
||||
CSU_CSLX_MG2TPR_IP,
|
||||
CSU_CSLX_IFC_MEM,
|
||||
CSU_CSLX_OCRAM,
|
||||
CSU_CSLX_GIC,
|
||||
CSU_CSLX_PCIE1,
|
||||
CSU_CSLX_OCRAM2,
|
||||
CSU_CSLX_QSPI_MEM,
|
||||
CSU_CSLX_PCIE2,
|
||||
CSU_CSLX_SATA,
|
||||
CSU_CSLX_USB1,
|
||||
CSU_CSLX_QM_BM_SWPORTAL,
|
||||
CSU_CSLX_PCIE3 = 16,
|
||||
CSU_CSLX_PCIE3_IO,
|
||||
CSU_CSLX_USB3 = 20,
|
||||
CSU_CSLX_USB2,
|
||||
CSU_CSLX_SERDES = 32,
|
||||
CSU_CSLX_QDMA,
|
||||
CSU_CSLX_LPUART2,
|
||||
CSU_CSLX_LPUART1,
|
||||
CSU_CSLX_LPUART4,
|
||||
CSU_CSLX_LPUART3,
|
||||
CSU_CSLX_LPUART6,
|
||||
CSU_CSLX_LPUART5,
|
||||
CSU_CSLX_DSPI1 = 41,
|
||||
CSU_CSLX_QSPI,
|
||||
CSU_CSLX_ESDHC,
|
||||
CSU_CSLX_IFC = 45,
|
||||
CSU_CSLX_I2C1,
|
||||
CSU_CSLX_I2C3 = 48,
|
||||
CSU_CSLX_I2C2,
|
||||
CSU_CSLX_DUART2 = 50,
|
||||
CSU_CSLX_DUART1,
|
||||
CSU_CSLX_WDT2,
|
||||
CSU_CSLX_WDT1,
|
||||
CSU_CSLX_EDMA,
|
||||
CSU_CSLX_SYS_CNT,
|
||||
CSU_CSLX_DMA_MUX2,
|
||||
CSU_CSLX_DMA_MUX1,
|
||||
CSU_CSLX_DDR,
|
||||
CSU_CSLX_QUICC,
|
||||
CSU_CSLX_DCFG_CCU_RCPM = 60,
|
||||
CSU_CSLX_SECURE_BOOTROM,
|
||||
CSU_CSLX_SFP,
|
||||
CSU_CSLX_TMU,
|
||||
CSU_CSLX_SECURE_MONITOR,
|
||||
CSU_CSLX_SCFG,
|
||||
CSU_CSLX_FM = 66,
|
||||
CSU_CSLX_SEC5_5,
|
||||
CSU_CSLX_BM,
|
||||
CSU_CSLX_QM,
|
||||
CSU_CSLX_GPIO2 = 70,
|
||||
CSU_CSLX_GPIO1,
|
||||
CSU_CSLX_GPIO4,
|
||||
CSU_CSLX_GPIO3,
|
||||
CSU_CSLX_PLATFORM_CONT,
|
||||
CSU_CSLX_CSU,
|
||||
CSU_CSLX_IIC4 = 77,
|
||||
CSU_CSLX_WDT4,
|
||||
CSU_CSLX_WDT3,
|
||||
CSU_CSLX_ESDHC2 = 80,
|
||||
CSU_CSLX_WDT5 = 81,
|
||||
CSU_CSLX_SAI2,
|
||||
CSU_CSLX_SAI1,
|
||||
CSU_CSLX_SAI4,
|
||||
CSU_CSLX_SAI3,
|
||||
CSU_CSLX_FTM2 = 86,
|
||||
CSU_CSLX_FTM1,
|
||||
CSU_CSLX_FTM4,
|
||||
CSU_CSLX_FTM3,
|
||||
CSU_CSLX_FTM6 = 90,
|
||||
CSU_CSLX_FTM5,
|
||||
CSU_CSLX_FTM8,
|
||||
CSU_CSLX_FTM7,
|
||||
CSU_CSLX_DSCR = 121,
|
||||
};
|
||||
|
||||
static struct csu_ns_dev ns_dev[] = {
|
||||
{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
|
||||
{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
|
||||
{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
|
||||
{CSU_CSLX_OCRAM, CSU_ALL_RW},
|
||||
{CSU_CSLX_GIC, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE1, CSU_ALL_RW},
|
||||
{CSU_CSLX_OCRAM2, CSU_ALL_RW},
|
||||
{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE2, CSU_ALL_RW},
|
||||
{CSU_CSLX_SATA, CSU_ALL_RW},
|
||||
{CSU_CSLX_USB1, CSU_ALL_RW},
|
||||
{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE3, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
|
||||
{CSU_CSLX_USB3, CSU_ALL_RW},
|
||||
{CSU_CSLX_USB2, CSU_ALL_RW},
|
||||
{CSU_CSLX_SERDES, CSU_ALL_RW},
|
||||
{CSU_CSLX_QDMA, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART2, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART1, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART4, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART3, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART6, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART5, CSU_ALL_RW},
|
||||
{CSU_CSLX_DSPI1, CSU_ALL_RW},
|
||||
{CSU_CSLX_QSPI, CSU_ALL_RW},
|
||||
{CSU_CSLX_ESDHC, CSU_ALL_RW},
|
||||
{CSU_CSLX_IFC, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C1, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C3, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DUART2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DUART1, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT2, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT1, CSU_ALL_RW},
|
||||
{CSU_CSLX_EDMA, CSU_ALL_RW},
|
||||
{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
|
||||
{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
|
||||
{CSU_CSLX_DDR, CSU_ALL_RW},
|
||||
{CSU_CSLX_QUICC, CSU_ALL_RW},
|
||||
{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SFP, CSU_ALL_RW},
|
||||
{CSU_CSLX_TMU, CSU_ALL_RW},
|
||||
{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
|
||||
{CSU_CSLX_SCFG, CSU_ALL_RW},
|
||||
{CSU_CSLX_FM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SEC5_5, CSU_ALL_RW},
|
||||
{CSU_CSLX_BM, CSU_ALL_RW},
|
||||
{CSU_CSLX_QM, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO2, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO1, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO4, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO3, CSU_ALL_RW},
|
||||
{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
|
||||
{CSU_CSLX_CSU, CSU_ALL_RW},
|
||||
{CSU_CSLX_IIC4, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT4, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT3, CSU_ALL_RW},
|
||||
{CSU_CSLX_ESDHC2, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT5, CSU_ALL_RW},
|
||||
{CSU_CSLX_SAI2, CSU_ALL_RW},
|
||||
{CSU_CSLX_SAI1, CSU_ALL_RW},
|
||||
{CSU_CSLX_SAI4, CSU_ALL_RW},
|
||||
{CSU_CSLX_SAI3, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM2, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM1, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM4, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM3, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM6, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM5, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM8, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM7, CSU_ALL_RW},
|
||||
{CSU_CSLX_DSCR, CSU_ALL_RW},
|
||||
};
|
||||
|
||||
#endif
|
||||
103
u-boot/arch/arm/include/asm/arch-fsl-layerscape/soc.h
Normal file
103
u-boot/arch/arm/include/asm/arch-fsl-layerscape/soc.h
Normal file
@@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define gur_in32(a) in_le32(a)
|
||||
#define gur_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
|
||||
#define gur_in32(a) in_be32(a)
|
||||
#define gur_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define scfg_in32(a) in_le32(a)
|
||||
#define scfg_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
|
||||
#define scfg_in32(a) in_be32(a)
|
||||
#define scfg_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
|
||||
#define pex_lut_in32(a) in_le32(a)
|
||||
#define pex_lut_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
|
||||
#define pex_lut_in32(a) in_be32(a)
|
||||
#define pex_lut_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
|
||||
struct cpu_type {
|
||||
char name[15];
|
||||
u32 soc_ver;
|
||||
u32 num_cores;
|
||||
};
|
||||
|
||||
#define CPU_TYPE_ENTRY(n, v, nc) \
|
||||
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
|
||||
|
||||
#define SVR_WO_E 0xFFFFFE
|
||||
#define SVR_LS1012A 0x870400
|
||||
#define SVR_LS1043A 0x879200
|
||||
#define SVR_LS1023A 0x879208
|
||||
#define SVR_LS2045A 0x870120
|
||||
#define SVR_LS2080A 0x870110
|
||||
#define SVR_LS2085A 0x870100
|
||||
#define SVR_LS2040A 0x870130
|
||||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
|
||||
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
|
||||
#define IS_SVR_REV(svr, maj, min) \
|
||||
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
|
||||
|
||||
/* ahci port register default value */
|
||||
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
|
||||
#define AHCI_PORT_PHY_2_CFG 0x28184d1f
|
||||
#define AHCI_PORT_PHY_3_CFG 0x0e081509
|
||||
#define AHCI_PORT_TRANS_CFG 0x08000029
|
||||
|
||||
/* AHCI (sata) register map */
|
||||
struct ccsr_ahci {
|
||||
u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
|
||||
u32 pcfg; /* port config */
|
||||
u32 ppcfg; /* port phy1 config */
|
||||
u32 pp2c; /* port phy2 config */
|
||||
u32 pp3c; /* port phy3 config */
|
||||
u32 pp4c; /* port phy4 config */
|
||||
u32 pp5c; /* port phy5 config */
|
||||
u32 axicc; /* AXI cache control */
|
||||
u32 paxic; /* port AXI config */
|
||||
u32 axipc; /* AXI PROT control */
|
||||
u32 ptc; /* port Trans Config */
|
||||
u32 pts; /* port Trans Status */
|
||||
u32 plc; /* port link config */
|
||||
u32 plc1; /* port link config1 */
|
||||
u32 plc2; /* port link config2 */
|
||||
u32 pls; /* port link status */
|
||||
u32 pls1; /* port link status1 */
|
||||
u32 pcmdc; /* port CMD config */
|
||||
u32 ppcs; /* port phy control status */
|
||||
u32 pberr; /* port 0/1 BIST error */
|
||||
u32 cmds; /* port 0/1 CMD status error */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
void fsl_lsch3_early_init_f(void);
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
void fsl_lsch2_early_init_f(void);
|
||||
#endif
|
||||
|
||||
void cpu_name(char *name);
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
|
||||
void erratum_a009635(void);
|
||||
#endif
|
||||
|
||||
bool soc_has_dp_ddr(void);
|
||||
bool soc_has_aiop(void);
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
|
||||
10
u-boot/arch/arm/include/asm/arch-fsl-layerscape/speed.h
Normal file
10
u-boot/arch/arm/include/asm/arch-fsl-layerscape/speed.h
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_SPEED_H
|
||||
#define _FSL_LAYERSCAPE_SPEED_H
|
||||
void get_sys_info(struct sys_info *sys_info);
|
||||
#endif /* _FSL_LAYERSCAPE_SPEED_H */
|
||||
8
u-boot/arch/arm/include/asm/arch-hi6220/dwmmc.h
Normal file
8
u-boot/arch/arm/include/asm/arch-hi6220/dwmmc.h
Normal file
@@ -0,0 +1,8 @@
|
||||
/*
|
||||
* (C) Copyright 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
|
||||
27
u-boot/arch/arm/include/asm/arch-hi6220/gpio.h
Normal file
27
u-boot/arch/arm/include/asm/arch-hi6220/gpio.h
Normal file
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _HI6220_GPIO_H_
|
||||
#define _HI6220_GPIO_H_
|
||||
|
||||
#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
|
||||
0xf7020000 - 0x4000) + (0x1000 * bank))
|
||||
|
||||
#define HI6220_GPIO_PER_BANK 8
|
||||
#define HI6220_GPIO_DIR 0x400
|
||||
|
||||
struct gpio_bank {
|
||||
u8 *base; /* address of registers in physical memory */
|
||||
};
|
||||
|
||||
/* Information about a GPIO bank */
|
||||
struct hikey_gpio_platdata {
|
||||
int bank_index;
|
||||
ulong base; /* address of registers in physical memory */
|
||||
};
|
||||
|
||||
#endif /* _HI6220_GPIO_H_ */
|
||||
390
u-boot/arch/arm/include/asm/arch-hi6220/hi6220.h
Normal file
390
u-boot/arch/arm/include/asm/arch-hi6220/hi6220.h
Normal file
@@ -0,0 +1,390 @@
|
||||
/*
|
||||
* (C) Copyright 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __HI6220_H__
|
||||
#define __HI6220_H__
|
||||
|
||||
#include "hi6220_regs_alwayson.h"
|
||||
|
||||
#define HI6220_MMC0_BASE 0xF723D000
|
||||
#define HI6220_MMC1_BASE 0xF723E000
|
||||
|
||||
#define HI6220_UART0_BASE 0xF8015000
|
||||
#define HI6220_UART3_BASE 0xF7113000
|
||||
|
||||
#define HI6220_PMUSSI_BASE 0xF8000000
|
||||
|
||||
#define HI6220_PERI_BASE 0xF7030000
|
||||
|
||||
struct peri_sc_periph_regs {
|
||||
u32 ctrl1; /*0x0*/
|
||||
u32 ctrl2;
|
||||
u32 ctrl3;
|
||||
u32 ctrl4;
|
||||
u32 ctrl5;
|
||||
u32 ctrl6;
|
||||
u32 ctrl8;
|
||||
u32 ctrl9;
|
||||
u32 ctrl10;
|
||||
u32 ctrl12;
|
||||
u32 ctrl13;
|
||||
u32 ctrl14;
|
||||
|
||||
u32 unknown_1[8];
|
||||
|
||||
u32 ddr_ctrl0; /*0x50*/
|
||||
|
||||
u32 unknown_2[16];
|
||||
|
||||
u32 stat1; /*0x94*/
|
||||
|
||||
u32 unknown_3[90];
|
||||
|
||||
u32 clk0_en; /*0x200*/
|
||||
u32 clk0_dis;
|
||||
u32 clk0_stat;
|
||||
|
||||
u32 unknown_4;
|
||||
|
||||
u32 clk1_en; /*0x210*/
|
||||
u32 clk1_dis;
|
||||
u32 clk1_stat;
|
||||
|
||||
u32 unknown_5;
|
||||
|
||||
u32 clk2_en; /*0x220*/
|
||||
u32 clk2_dis;
|
||||
u32 clk2_stat;
|
||||
|
||||
u32 unknown_6;
|
||||
|
||||
u32 clk3_en; /*0x230*/
|
||||
u32 clk3_dis;
|
||||
u32 clk3_stat;
|
||||
|
||||
u32 unknown_7;
|
||||
|
||||
u32 clk8_en; /*0x240*/
|
||||
u32 clk8_dis;
|
||||
u32 clk8_stat;
|
||||
|
||||
u32 unknown_8;
|
||||
|
||||
u32 clk9_en; /*0x250*/
|
||||
u32 clk9_dis;
|
||||
u32 clk9_stat;
|
||||
|
||||
u32 unknown_9;
|
||||
|
||||
u32 clk10_en; /*0x260*/
|
||||
u32 clk10_dis;
|
||||
u32 clk10_stat;
|
||||
|
||||
u32 unknown_10;
|
||||
|
||||
u32 clk12_en; /*0x270*/
|
||||
u32 clk12_dis;
|
||||
u32 clk12_stat;
|
||||
|
||||
u32 unknown_11[33];
|
||||
|
||||
u32 rst0_en; /*0x300*/
|
||||
u32 rst0_dis;
|
||||
u32 rst0_stat;
|
||||
|
||||
u32 unknown_12;
|
||||
|
||||
u32 rst1_en; /*0x310*/
|
||||
u32 rst1_dis;
|
||||
u32 rst1_stat;
|
||||
|
||||
u32 unknown_13;
|
||||
|
||||
u32 rst2_en; /*0x320*/
|
||||
u32 rst2_dis;
|
||||
u32 rst2_stat;
|
||||
|
||||
u32 unknown_14;
|
||||
|
||||
u32 rst3_en; /*0x330*/
|
||||
u32 rst3_dis;
|
||||
u32 rst3_stat;
|
||||
|
||||
u32 unknown_15;
|
||||
|
||||
u32 rst8_en; /*0x340*/
|
||||
u32 rst8_dis;
|
||||
u32 rst8_stat;
|
||||
|
||||
u32 unknown_16[45];
|
||||
|
||||
u32 clk0_sel; /*0x400*/
|
||||
|
||||
u32 unknown_17[36];
|
||||
|
||||
u32 clkcfg8bit1; /*0x494*/
|
||||
u32 clkcfg8bit2;
|
||||
|
||||
u32 unknown_18[538];
|
||||
|
||||
u32 reserved8_addr; /*0xd04*/
|
||||
};
|
||||
|
||||
|
||||
/* CTRL1 bit definitions */
|
||||
|
||||
#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
|
||||
#define PERI_CTRL1_HIFI_INT_MASK (1 << 1)
|
||||
#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2)
|
||||
#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16)
|
||||
#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17)
|
||||
#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18)
|
||||
|
||||
|
||||
/* CTRL2 bit definitions */
|
||||
|
||||
#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0)
|
||||
#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2)
|
||||
#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6)
|
||||
#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7)
|
||||
#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8)
|
||||
#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9)
|
||||
#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12)
|
||||
#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28)
|
||||
|
||||
/* CTRL3 bit definitions */
|
||||
|
||||
#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0)
|
||||
#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12)
|
||||
#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24)
|
||||
|
||||
/* CTRL4 bit definitions */
|
||||
|
||||
#define PERI_CTRL4_PICO_FSELV (1 << 0)
|
||||
#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3)
|
||||
#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4)
|
||||
#define PERI_CTRL4_PICO_SIDDQ (1 << 6)
|
||||
#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7)
|
||||
#define PERI_CTRL4_PICO_OGDISABLE (1 << 8)
|
||||
#define PERI_CTRL4_PICO_COMMONONN (1 << 9)
|
||||
#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10)
|
||||
#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11)
|
||||
#define PERI_CTRL4_PICO_VATESTENB (1 << 12)
|
||||
#define PERI_CTRL4_PICO_SUSPENDM (1 << 14)
|
||||
#define PERI_CTRL4_PICO_SLEEPM (1 << 15)
|
||||
#define PERI_CTRL4_BC11_C (1 << 16)
|
||||
#define PERI_CTRL4_BC11_B (1 << 17)
|
||||
#define PERI_CTRL4_BC11_A (1 << 18)
|
||||
#define PERI_CTRL4_BC11_GND (1 << 19)
|
||||
#define PERI_CTRL4_BC11_FLOAT (1 << 20)
|
||||
#define PERI_CTRL4_OTG_PHY_SEL (1 << 21)
|
||||
#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22)
|
||||
#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24)
|
||||
#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25)
|
||||
#define PERI_CTRL4_OTG_IDPULLUP (1 << 26)
|
||||
#define PERI_CTRL4_OTG_DRVBUS (1 << 27)
|
||||
#define PERI_CTRL4_OTG_SESSEND (1 << 28)
|
||||
#define PERI_CTRL4_OTG_BVALID (1 << 29)
|
||||
#define PERI_CTRL4_OTG_AVALID (1 << 30)
|
||||
#define PERI_CTRL4_OTG_VBUSVALID (1 << 31)
|
||||
|
||||
/* CTRL5 bit definitions */
|
||||
|
||||
#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)
|
||||
#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4)
|
||||
#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5)
|
||||
#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6)
|
||||
#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7)
|
||||
#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8)
|
||||
#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9)
|
||||
#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10)
|
||||
#define PERI_CTRL5_DBG_MUX (1 << 11)
|
||||
|
||||
/* CTRL6 bit definitions */
|
||||
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12)
|
||||
|
||||
/* CTRL8 bit definitions */
|
||||
|
||||
#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0)
|
||||
#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2)
|
||||
#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4)
|
||||
#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6)
|
||||
#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8)
|
||||
#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11)
|
||||
#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12)
|
||||
#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16)
|
||||
#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20)
|
||||
#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28)
|
||||
|
||||
/* CTRL9 bit definitions */
|
||||
|
||||
#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0)
|
||||
#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1)
|
||||
#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4)
|
||||
#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8)
|
||||
|
||||
/* CLK0 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK0_MMC0 (1 << 0)
|
||||
#define PERI_CLK0_MMC1 (1 << 1)
|
||||
#define PERI_CLK0_MMC2 (1 << 2)
|
||||
#define PERI_CLK0_NANDC (1 << 3)
|
||||
#define PERI_CLK0_USBOTG (1 << 4)
|
||||
#define PERI_CLK0_PICOPHY (1 << 5)
|
||||
#define PERI_CLK0_PLL (1 << 6)
|
||||
|
||||
/* CLK1 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK1_HIFI (1 << 0)
|
||||
#define PERI_CLK1_DIGACODEC (1 << 5)
|
||||
|
||||
/* CLK2 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK2_IPF (1 << 0)
|
||||
#define PERI_CLK2_SOCP (1 << 1)
|
||||
#define PERI_CLK2_DMAC (1 << 2)
|
||||
#define PERI_CLK2_SECENG (1 << 3)
|
||||
#define PERI_CLK2_HPM0 (1 << 5)
|
||||
#define PERI_CLK2_HPM1 (1 << 6)
|
||||
#define PERI_CLK2_HPM2 (1 << 7)
|
||||
#define PERI_CLK2_HPM3 (1 << 8)
|
||||
|
||||
/* CLK8 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK8_RS0 (1 << 0)
|
||||
#define PERI_CLK8_RS2 (1 << 1)
|
||||
#define PERI_CLK8_RS3 (1 << 2)
|
||||
#define PERI_CLK8_MS0 (1 << 3)
|
||||
#define PERI_CLK8_MS2 (1 << 5)
|
||||
#define PERI_CLK8_XG2RAM0 (1 << 6)
|
||||
#define PERI_CLK8_X2SRAM (1 << 7)
|
||||
#define PERI_CLK8_SRAM (1 << 8)
|
||||
#define PERI_CLK8_ROM (1 << 9)
|
||||
#define PERI_CLK8_HARQ (1 << 10)
|
||||
#define PERI_CLK8_MMU (1 << 11)
|
||||
#define PERI_CLK8_DDRC (1 << 12)
|
||||
#define PERI_CLK8_DDRPHY (1 << 13)
|
||||
#define PERI_CLK8_DDRPHY_REF (1 << 14)
|
||||
#define PERI_CLK8_X2X_SYSNOC (1 << 15)
|
||||
#define PERI_CLK8_X2X_CCPU (1 << 16)
|
||||
#define PERI_CLK8_DDRT (1 << 17)
|
||||
#define PERI_CLK8_DDRPACK_RS (1 << 18)
|
||||
|
||||
/* CLK9 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK9_CARM_DAP (1 << 0)
|
||||
#define PERI_CLK9_CARM_ATB (1 << 1)
|
||||
#define PERI_CLK9_CARM_LBUS (1 << 2)
|
||||
#define PERI_CLK9_CARM_KERNEL (1 << 3)
|
||||
|
||||
/* CLK10 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK10_IPF_CCPU (1 << 0)
|
||||
#define PERI_CLK10_SOCP_CCPU (1 << 1)
|
||||
#define PERI_CLK10_SECENG_CCPU (1 << 2)
|
||||
#define PERI_CLK10_HARQ_CCPU (1 << 3)
|
||||
#define PERI_CLK10_IPF_MCU (1 << 16)
|
||||
#define PERI_CLK10_SOCP_MCU (1 << 17)
|
||||
#define PERI_CLK10_SECENG_MCU (1 << 18)
|
||||
#define PERI_CLK10_HARQ_MCU (1 << 19)
|
||||
|
||||
/* CLK12 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK12_HIFI_SRC (1 << 0)
|
||||
#define PERI_CLK12_MMC0_SRC (1 << 1)
|
||||
#define PERI_CLK12_MMC1_SRC (1 << 2)
|
||||
#define PERI_CLK12_MMC2_SRC (1 << 3)
|
||||
#define PERI_CLK12_SYSPLL_DIV (1 << 4)
|
||||
#define PERI_CLK12_TPIU_SRC (1 << 5)
|
||||
#define PERI_CLK12_MMC0_HF (1 << 6)
|
||||
#define PERI_CLK12_MMC1_HF (1 << 7)
|
||||
#define PERI_CLK12_PLL_TEST_SRC (1 << 8)
|
||||
#define PERI_CLK12_CODEC_SOC (1 << 9)
|
||||
#define PERI_CLK12_MEDIA (1 << 10)
|
||||
|
||||
/* RST0 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST0_MMC0 (1 << 0)
|
||||
#define PERI_RST0_MMC1 (1 << 1)
|
||||
#define PERI_RST0_MMC2 (1 << 2)
|
||||
#define PERI_RST0_NANDC (1 << 3)
|
||||
#define PERI_RST0_USBOTG_BUS (1 << 4)
|
||||
#define PERI_RST0_POR_PICOPHY (1 << 5)
|
||||
#define PERI_RST0_USBOTG (1 << 6)
|
||||
#define PERI_RST0_USBOTG_32K (1 << 7)
|
||||
|
||||
/* RST1 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST1_HIFI (1 << 0)
|
||||
#define PERI_RST1_DIGACODEC (1 << 5)
|
||||
|
||||
/* RST2 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST2_IPF (1 << 0)
|
||||
#define PERI_RST2_SOCP (1 << 1)
|
||||
#define PERI_RST2_DMAC (1 << 2)
|
||||
#define PERI_RST2_SECENG (1 << 3)
|
||||
#define PERI_RST2_ABB (1 << 4)
|
||||
#define PERI_RST2_HPM0 (1 << 5)
|
||||
#define PERI_RST2_HPM1 (1 << 6)
|
||||
#define PERI_RST2_HPM2 (1 << 7)
|
||||
#define PERI_RST2_HPM3 (1 << 8)
|
||||
|
||||
/* RST3 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST3_CSSYS (1 << 0)
|
||||
#define PERI_RST3_I2C0 (1 << 1)
|
||||
#define PERI_RST3_I2C1 (1 << 2)
|
||||
#define PERI_RST3_I2C2 (1 << 3)
|
||||
#define PERI_RST3_I2C3 (1 << 4)
|
||||
#define PERI_RST3_UART1 (1 << 5)
|
||||
#define PERI_RST3_UART2 (1 << 6)
|
||||
#define PERI_RST3_UART3 (1 << 7)
|
||||
#define PERI_RST3_UART4 (1 << 8)
|
||||
#define PERI_RST3_SSP (1 << 9)
|
||||
#define PERI_RST3_PWM (1 << 10)
|
||||
#define PERI_RST3_BLPWM (1 << 11)
|
||||
#define PERI_RST3_TSENSOR (1 << 12)
|
||||
#define PERI_RST3_DAPB (1 << 18)
|
||||
#define PERI_RST3_HKADC (1 << 19)
|
||||
#define PERI_RST3_CODEC (1 << 20)
|
||||
|
||||
/* RST8 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST8_RS0 (1 << 0)
|
||||
#define PERI_RST8_RS2 (1 << 1)
|
||||
#define PERI_RST8_RS3 (1 << 2)
|
||||
#define PERI_RST8_MS0 (1 << 3)
|
||||
#define PERI_RST8_MS2 (1 << 5)
|
||||
#define PERI_RST8_XG2RAM0 (1 << 6)
|
||||
#define PERI_RST8_X2SRAM_TZMA (1 << 7)
|
||||
#define PERI_RST8_SRAM (1 << 8)
|
||||
#define PERI_RST8_HARQ (1 << 10)
|
||||
#define PERI_RST8_DDRC (1 << 12)
|
||||
#define PERI_RST8_DDRC_APB (1 << 13)
|
||||
#define PERI_RST8_DDRPACK_APB (1 << 14)
|
||||
#define PERI_RST8_DDRT (1 << 17)
|
||||
|
||||
#endif /*__HI62220_H__*/
|
||||
420
u-boot/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h
Normal file
420
u-boot/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h
Normal file
@@ -0,0 +1,420 @@
|
||||
/*
|
||||
* (C) Copyright 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __HI6220_ALWAYSON_H__
|
||||
#define __HI6220_ALWAYSON_H__
|
||||
|
||||
#define ALWAYSON_CTRL_BASE 0xF7800000
|
||||
|
||||
struct alwayson_sc_regs {
|
||||
u32 ctrl0; /*0x0*/
|
||||
u32 ctrl1;
|
||||
u32 ctrl2;
|
||||
|
||||
u32 unknown;
|
||||
|
||||
u32 stat0; /*0x10*/
|
||||
u32 stat1;
|
||||
u32 mcu_imctrl;
|
||||
u32 mcu_imstat;
|
||||
|
||||
u32 unknown_1[9];
|
||||
|
||||
u32 secondary_int_en0; /*0x44*/
|
||||
u32 secondary_int_statr0;
|
||||
u32 secondary_int_statm0;
|
||||
|
||||
u32 unknown_2;
|
||||
|
||||
u32 mcu_wkup_int_en6; /*0x54*/
|
||||
u32 mcu_wkup_int_statr6;
|
||||
u32 mcu_wkup_int_statm6;
|
||||
|
||||
u32 unknown_3;
|
||||
|
||||
u32 mcu_wkup_int_en5; /*0x64*/
|
||||
u32 mcu_wkup_int_statr5;
|
||||
u32 mcu_wkup_int_statm5;
|
||||
|
||||
u32 unknown_4[9];
|
||||
|
||||
u32 mcu_wkup_int_en4; /*0x94*/
|
||||
u32 mcu_wkup_int_statr4;
|
||||
u32 mcu_wkup_int_statm4;
|
||||
|
||||
u32 unknown_5[2];
|
||||
|
||||
u32 mcu_wkup_int_en0; /*0xa8*/
|
||||
u32 mcu_wkup_int_statr0;
|
||||
u32 mcu_wkup_int_statm0;
|
||||
|
||||
u32 mcu_wkup_int_en1; /*0xb4*/
|
||||
u32 mcu_wkup_int_statr1;
|
||||
u32 mcu_wkup_int_statm1;
|
||||
|
||||
u32 unknown_6;
|
||||
|
||||
u32 int_statr; /*0xc4*/
|
||||
u32 int_statm;
|
||||
u32 int_clear;
|
||||
|
||||
u32 int_en_set; /*0xd0*/
|
||||
u32 int_en_dis;
|
||||
u32 int_en_stat;
|
||||
|
||||
u32 unknown_7[2];
|
||||
|
||||
u32 int_statr1; /*0xc4*/
|
||||
u32 int_statm1;
|
||||
u32 int_clear1;
|
||||
|
||||
u32 int_en_set1; /*0xf0*/
|
||||
u32 int_en_dis1;
|
||||
u32 int_en_stat1;
|
||||
|
||||
u32 unknown_8[53];
|
||||
|
||||
u32 timer_en0; /*0x1d0*/
|
||||
u32 timer_en1;
|
||||
|
||||
u32 unknown_9[6];
|
||||
|
||||
u32 timer_en4; /*0x1f0*/
|
||||
u32 timer_en5;
|
||||
|
||||
u32 unknown_10[130];
|
||||
|
||||
u32 mcu_subsys_ctrl0; /*0x400*/
|
||||
u32 mcu_subsys_ctrl1;
|
||||
u32 mcu_subsys_ctrl2;
|
||||
u32 mcu_subsys_ctrl3;
|
||||
u32 mcu_subsys_ctrl4;
|
||||
u32 mcu_subsys_ctrl5;
|
||||
u32 mcu_subsys_ctrl6;
|
||||
u32 mcu_subsys_ctrl7;
|
||||
|
||||
u32 unknown_10_1[8];
|
||||
|
||||
u32 mcu_subsys_stat0; /*0x440*/
|
||||
u32 mcu_subsys_stat1;
|
||||
u32 mcu_subsys_stat2;
|
||||
u32 mcu_subsys_stat3;
|
||||
u32 mcu_subsys_stat4;
|
||||
u32 mcu_subsys_stat5;
|
||||
u32 mcu_subsys_stat6;
|
||||
u32 mcu_subsys_stat7;
|
||||
|
||||
u32 unknown_11[116];
|
||||
|
||||
u32 clk4_en; /*0x630*/
|
||||
u32 clk4_dis;
|
||||
u32 clk4_stat;
|
||||
|
||||
u32 clk5_en; /*0x63c*/
|
||||
u32 clk5_dis;
|
||||
u32 clk5_stat;
|
||||
|
||||
u32 unknown_12[42];
|
||||
|
||||
u32 rst4_en; /*0x6f0*/
|
||||
u32 rst4_dis;
|
||||
u32 rst4_stat;
|
||||
|
||||
u32 rst5_en; /*0x6fc*/
|
||||
u32 rst5_dis;
|
||||
u32 rst5_stat;
|
||||
|
||||
u32 unknown_13[62];
|
||||
|
||||
u32 pw_clk0_en; /*0x800*/
|
||||
u32 pw_clk0_dis;
|
||||
u32 pw_clk0_stat;
|
||||
|
||||
u32 unknown_13_1;
|
||||
|
||||
u32 pw_rst0_en; /*0x810*/
|
||||
u32 pw_rst0_dis;
|
||||
u32 pw_rst0_stat;
|
||||
|
||||
u32 unknown_14;
|
||||
|
||||
u32 pw_isoen0; /*0x820*/
|
||||
u32 pw_isodis0;
|
||||
u32 pw_iso_stat0;
|
||||
|
||||
u32 unknown_14_1;
|
||||
|
||||
u32 pw_mtcmos_en0; /*0x830*/
|
||||
u32 pw_mtcmos_dis0;
|
||||
u32 pw_mtcmos_stat0;
|
||||
u32 pw_mtcmos_ack_stat0;
|
||||
u32 pw_mtcmos_timeout_stat0;
|
||||
|
||||
u32 unknown_14_2[3];
|
||||
|
||||
u32 pw_stat0; /*0x850*/
|
||||
u32 pw_stat1;
|
||||
|
||||
u32 unknown_15[10];
|
||||
|
||||
u32 systest_stat; /*0x880*/
|
||||
|
||||
u32 unknown_16[3];
|
||||
|
||||
u32 systest_slicer_cnt0;/*0x890*/
|
||||
u32 systest_slicer_cnt1;
|
||||
|
||||
u32 unknown_17[12];
|
||||
|
||||
u32 pw_ctrl1; /*0x8C8*/
|
||||
u32 pw_ctrl;
|
||||
|
||||
u32 mcpu_voteen;
|
||||
u32 mcpu_votedis;
|
||||
u32 mcpu_votestat;
|
||||
|
||||
u32 unknown_17_1;
|
||||
|
||||
u32 mcpu_vote_msk0; /*0x8E0*/
|
||||
u32 mcpu_vote_msk1;
|
||||
u32 mcpu_votestat0_msk;
|
||||
u32 mcpu_votestat1_msk;
|
||||
|
||||
u32 peri_voteen; /*0x8F0*/
|
||||
u32 peri_votedis;
|
||||
u32 peri_votestat;
|
||||
|
||||
u32 unknown_17_2;
|
||||
|
||||
u32 peri_vote_msk0; /*0x900*/
|
||||
u32 peri_vote_msk1;
|
||||
u32 peri_votestat0_msk;
|
||||
u32 erpi_votestat1_msk;
|
||||
u32 acpu_voteen;
|
||||
u32 acpu_votedis;
|
||||
u32 acpu_votestat;
|
||||
|
||||
u32 unknown_18;
|
||||
|
||||
u32 acpu_vote_msk0; /*0x920*/
|
||||
u32 acpu_vote_msk1;
|
||||
u32 acpu_votestat0_msk;
|
||||
u32 acpu_votestat1_msk;
|
||||
u32 mcu_voteen;
|
||||
u32 mcu_votedis;
|
||||
u32 mcu_votestat;
|
||||
|
||||
u32 unknown_18_1;
|
||||
|
||||
u32 mcu_vote_msk0; /*0x940*/
|
||||
u32 mcu_vote_msk1;
|
||||
u32 mcu_vote_votestat0_msk;
|
||||
u32 mcu_vote_votestat1_msk;
|
||||
|
||||
u32 unknown_18_1_2[4];
|
||||
|
||||
u32 mcu_vote_vote1en; /*0x960*/
|
||||
u32 mcu_vote_vote1dis;
|
||||
u32 mcu_vote_vote1stat;
|
||||
|
||||
u32 unknown_18_2;
|
||||
|
||||
u32 mcu_vote_vote1_msk0;/*0x970*/
|
||||
u32 mcu_vote_vote1_msk1;
|
||||
u32 mcu_vote_vote1stat0_msk;
|
||||
u32 mcu_vote_vote1stat1_msk;
|
||||
u32 mcu_vote_vote2en;
|
||||
u32 mcu_vote_vote2dis;
|
||||
u32 mcu_vote_vote2stat;
|
||||
|
||||
u32 unknown_18_3;
|
||||
|
||||
u32 mcu_vote2_msk0; /*0x990*/
|
||||
u32 mcu_vote2_msk1;
|
||||
u32 mcu_vote2stat0_msk;
|
||||
u32 mcu_vote2stat1_msk;
|
||||
u32 vote_ctrl;
|
||||
u32 vote_stat; /*0x9a4*/
|
||||
|
||||
u32 unknown_19[342];
|
||||
|
||||
u32 econum; /*0xf00*/
|
||||
|
||||
u32 unknown_20_1[3];
|
||||
|
||||
u32 scchipid; /*0xf10*/
|
||||
|
||||
u32 unknown_20_2[2];
|
||||
|
||||
u32 scsocid; /*0xf1c*/
|
||||
|
||||
u32 unknown_20[48];
|
||||
|
||||
u32 soc_fpga_rtl_def; /*0xfe0*/
|
||||
u32 soc_fpga_pr_def;
|
||||
u32 soc_fpga_res_def0;
|
||||
u32 soc_fpga_res_def1; /*0xfec*/
|
||||
};
|
||||
|
||||
/* ctrl0 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004
|
||||
#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007
|
||||
|
||||
/* ctrl1 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31)
|
||||
|
||||
/* ctrl2 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31)
|
||||
|
||||
/* stat0 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
|
||||
#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
|
||||
#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27)
|
||||
#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
|
||||
#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
|
||||
#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
|
||||
#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31)
|
||||
|
||||
/* stat1 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0)
|
||||
#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
|
||||
#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17)
|
||||
#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19)
|
||||
#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20)
|
||||
#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27)
|
||||
#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28)
|
||||
#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29)
|
||||
|
||||
/* ctrl3 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11)
|
||||
|
||||
/* clk4_en bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31)
|
||||
|
||||
/* clk5_en bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19)
|
||||
|
||||
/* rst4_dis bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30)
|
||||
|
||||
#define PCLK_TIMER1 (1 << 16)
|
||||
#define PCLK_TIMER0 (1 << 15)
|
||||
|
||||
#endif /* __HI6220_ALWAYSON_H__ */
|
||||
30
u-boot/arch/arm/include/asm/arch-hi6220/periph.h
Normal file
30
u-boot/arch/arm/include/asm/arch-hi6220/periph.h
Normal file
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_PERIPH_H
|
||||
#define __ASM_ARM_ARCH_PERIPH_H
|
||||
|
||||
/*
|
||||
* Peripherals required for pinmux configuration. List will
|
||||
* grow with support for more devices getting added.
|
||||
* Numbering based on interrupt table.
|
||||
*
|
||||
*/
|
||||
enum periph_id {
|
||||
PERIPH_ID_UART0 = 36,
|
||||
PERIPH_ID_UART1,
|
||||
PERIPH_ID_UART2,
|
||||
PERIPH_ID_UART3,
|
||||
PERIPH_ID_UART4,
|
||||
PERIPH_ID_UART5,
|
||||
PERIPH_ID_SDMMC0 = 72,
|
||||
PERIPH_ID_SDMMC1,
|
||||
|
||||
PERIPH_ID_NONE = -1,
|
||||
};
|
||||
|
||||
#endif /* __ASM_ARM_ARCH_PERIPH_H */
|
||||
82
u-boot/arch/arm/include/asm/arch-hi6220/pinmux.h
Normal file
82
u-boot/arch/arm/include/asm/arch-hi6220/pinmux.h
Normal file
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_PINMUX_H
|
||||
#define __ASM_ARM_ARCH_PINMUX_H
|
||||
|
||||
#include "periph.h"
|
||||
|
||||
|
||||
/* iomg bit definition */
|
||||
#define MUX_M0 0
|
||||
#define MUX_M1 1
|
||||
#define MUX_M2 2
|
||||
#define MUX_M3 3
|
||||
#define MUX_M4 4
|
||||
#define MUX_M5 5
|
||||
#define MUX_M6 6
|
||||
#define MUX_M7 7
|
||||
|
||||
/* iocg bit definition */
|
||||
#define PULL_MASK (3)
|
||||
#define PULL_DIS (0)
|
||||
#define PULL_UP (1 << 0)
|
||||
#define PULL_DOWN (1 << 1)
|
||||
|
||||
/* drive strength definition */
|
||||
#define DRIVE_MASK (7 << 4)
|
||||
#define DRIVE1_02MA (0 << 4)
|
||||
#define DRIVE1_04MA (1 << 4)
|
||||
#define DRIVE1_08MA (2 << 4)
|
||||
#define DRIVE1_10MA (3 << 4)
|
||||
#define DRIVE2_02MA (0 << 4)
|
||||
#define DRIVE2_04MA (1 << 4)
|
||||
#define DRIVE2_08MA (2 << 4)
|
||||
#define DRIVE2_10MA (3 << 4)
|
||||
#define DRIVE3_04MA (0 << 4)
|
||||
#define DRIVE3_08MA (1 << 4)
|
||||
#define DRIVE3_12MA (2 << 4)
|
||||
#define DRIVE3_16MA (3 << 4)
|
||||
#define DRIVE3_20MA (4 << 4)
|
||||
#define DRIVE3_24MA (5 << 4)
|
||||
#define DRIVE3_32MA (6 << 4)
|
||||
#define DRIVE3_40MA (7 << 4)
|
||||
#define DRIVE4_02MA (0 << 4)
|
||||
#define DRIVE4_04MA (2 << 4)
|
||||
#define DRIVE4_08MA (4 << 4)
|
||||
#define DRIVE4_10MA (6 << 4)
|
||||
|
||||
#define HI6220_PINMUX0_BASE 0xf7010000
|
||||
#define HI6220_PINMUX1_BASE 0xf7010800
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* maybe more registers, but highest used is 123 */
|
||||
#define REG_NUM 123
|
||||
|
||||
struct hi6220_pinmux0_regs {
|
||||
uint32_t iomg[REG_NUM];
|
||||
};
|
||||
|
||||
struct hi6220_pinmux1_regs {
|
||||
uint32_t iocfg[REG_NUM];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Configures the pinmux for a particular peripheral.
|
||||
*
|
||||
* This function will configure the peripheral pinmux along with
|
||||
* pull-up/down and drive strength.
|
||||
*
|
||||
* @param peripheral peripheral to be configured
|
||||
* @return 0 if ok, -1 on error (e.g. unsupported peripheral)
|
||||
*/
|
||||
int hi6220_pinmux_config(int peripheral);
|
||||
|
||||
#endif
|
||||
48
u-boot/arch/arm/include/asm/arch-imx/cpu.h
Normal file
48
u-boot/arch/arm/include/asm/arch-imx/cpu.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* (C) Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#define MXC_CPU_MX23 0x23
|
||||
#define MXC_CPU_MX25 0x25
|
||||
#define MXC_CPU_MX27 0x27
|
||||
#define MXC_CPU_MX28 0x28
|
||||
#define MXC_CPU_MX31 0x31
|
||||
#define MXC_CPU_MX35 0x35
|
||||
#define MXC_CPU_MX51 0x51
|
||||
#define MXC_CPU_MX53 0x53
|
||||
#define MXC_CPU_MX6SL 0x60
|
||||
#define MXC_CPU_MX6DL 0x61
|
||||
#define MXC_CPU_MX6SX 0x62
|
||||
#define MXC_CPU_MX6Q 0x63
|
||||
#define MXC_CPU_MX6UL 0x64
|
||||
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
|
||||
#define MXC_CPU_MX6D 0x67
|
||||
#define MXC_CPU_MX6DP 0x68
|
||||
#define MXC_CPU_MX6QP 0x69
|
||||
#define MXC_CPU_MX7S 0x71 /* dummy ID */
|
||||
#define MXC_CPU_MX7D 0x72
|
||||
#define MXC_CPU_VF610 0xF6 /* dummy ID */
|
||||
|
||||
#define MXC_SOC_MX6 0x60
|
||||
#define MXC_SOC_MX7 0x70
|
||||
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define CHIP_REV_1_1 0x11
|
||||
#define CHIP_REV_1_2 0x12
|
||||
#define CHIP_REV_1_5 0x15
|
||||
#define CHIP_REV_2_0 0x20
|
||||
#define CHIP_REV_2_5 0x25
|
||||
#define CHIP_REV_3_0 0x30
|
||||
|
||||
#define BOARD_REV_1_0 0x0
|
||||
#define BOARD_REV_2_0 0x1
|
||||
#define BOARD_VER_OFFSET 0x8
|
||||
|
||||
#define CS0_128 0
|
||||
#define CS0_64M_CS1_64M 1
|
||||
#define CS0_64M_CS1_32M_CS2_32M 2
|
||||
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
|
||||
|
||||
u32 get_imx_reset_cause(void);
|
||||
637
u-boot/arch/arm/include/asm/arch-imx/imx-regs.h
Normal file
637
u-boot/arch/arm/include/asm/arch-imx/imx-regs.h
Normal file
@@ -0,0 +1,637 @@
|
||||
#ifndef _IMX_REGS_H
|
||||
#define _IMX_REGS_H
|
||||
|
||||
#define ARCH_MXC
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* Motorola IMX system registers
|
||||
* ------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
|
||||
|
||||
# ifndef __ASSEMBLY__
|
||||
# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))
|
||||
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
|
||||
# else
|
||||
# define __REG(x) (x)
|
||||
# define __REG2(x,y) ((x)+(y))
|
||||
#endif
|
||||
|
||||
#define IMX_IO_BASE 0x00200000
|
||||
|
||||
/*
|
||||
* Register BASEs, based on OFFSETs
|
||||
*
|
||||
*/
|
||||
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
|
||||
#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
|
||||
#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
|
||||
#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
|
||||
#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
|
||||
#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
|
||||
#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
|
||||
#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
|
||||
#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
|
||||
#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
|
||||
#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
|
||||
#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
|
||||
#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
|
||||
#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
|
||||
#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
|
||||
#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
|
||||
#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
|
||||
#define I2C1_BASE_ADDR (0x17000 + IMX_IO_BASE)
|
||||
#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
|
||||
#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
|
||||
#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
|
||||
#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
|
||||
#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
|
||||
#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
|
||||
#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
|
||||
#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
|
||||
#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
|
||||
#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
|
||||
#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
|
||||
|
||||
/* Watchdog Registers*/
|
||||
|
||||
#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
|
||||
#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
|
||||
#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
|
||||
|
||||
/* SYSCTRL Registers */
|
||||
#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
|
||||
#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
|
||||
#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
|
||||
|
||||
/* Chip Select Registers */
|
||||
#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
|
||||
#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
|
||||
#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
|
||||
#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
|
||||
#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
|
||||
#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
|
||||
#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
|
||||
#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
|
||||
#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
|
||||
#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
|
||||
#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
|
||||
#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
|
||||
#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
|
||||
|
||||
/* SDRAM controller registers */
|
||||
|
||||
#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
|
||||
#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
|
||||
#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
|
||||
#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
|
||||
|
||||
/* PLL registers */
|
||||
#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
|
||||
#define CSCR_SPLL_RESTART (1<<22)
|
||||
#define CSCR_MPLL_RESTART (1<<21)
|
||||
#define CSCR_SYSTEM_SEL (1<<16)
|
||||
#define CSCR_BCLK_DIV (0xf<<10)
|
||||
#define CSCR_MPU_PRESC (1<<15)
|
||||
#define CSCR_SPEN (1<<1)
|
||||
#define CSCR_MPEN (1<<0)
|
||||
|
||||
#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
|
||||
#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
|
||||
#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
|
||||
#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
|
||||
#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
|
||||
|
||||
/*
|
||||
* GPIO Module and I/O Multiplexer
|
||||
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
|
||||
*/
|
||||
#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
|
||||
#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
|
||||
#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
|
||||
#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
|
||||
#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
|
||||
#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
|
||||
#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
|
||||
#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
|
||||
#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
|
||||
#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
|
||||
#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
|
||||
#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
|
||||
#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
|
||||
#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
|
||||
#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
|
||||
#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
|
||||
#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
|
||||
|
||||
#define GPIO_PORT_MAX 3
|
||||
|
||||
#define GPIO_PIN_MASK 0x1f
|
||||
#define GPIO_PORT_MASK (0x3 << 5)
|
||||
|
||||
#define GPIO_PORT_SHIFT 5
|
||||
#define GPIO_PORTA (0<<5)
|
||||
#define GPIO_PORTB (1<<5)
|
||||
#define GPIO_PORTC (2<<5)
|
||||
#define GPIO_PORTD (3<<5)
|
||||
|
||||
#define GPIO_OUT (1<<7)
|
||||
#define GPIO_IN (0<<7)
|
||||
#define GPIO_PUEN (1<<8)
|
||||
|
||||
#define GPIO_PF (0<<9)
|
||||
#define GPIO_AF (1<<9)
|
||||
|
||||
#define GPIO_OCR_SHIFT 10
|
||||
#define GPIO_OCR_MASK (3<<10)
|
||||
#define GPIO_AIN (0<<10)
|
||||
#define GPIO_BIN (1<<10)
|
||||
#define GPIO_CIN (2<<10)
|
||||
#define GPIO_DR (3<<10)
|
||||
|
||||
#define GPIO_AOUT_SHIFT 12
|
||||
#define GPIO_AOUT_MASK (3<<12)
|
||||
#define GPIO_AOUT (0<<12)
|
||||
#define GPIO_AOUT_ISR (1<<12)
|
||||
#define GPIO_AOUT_0 (2<<12)
|
||||
#define GPIO_AOUT_1 (3<<12)
|
||||
|
||||
#define GPIO_BOUT_SHIFT 14
|
||||
#define GPIO_BOUT_MASK (3<<14)
|
||||
#define GPIO_BOUT (0<<14)
|
||||
#define GPIO_BOUT_ISR (1<<14)
|
||||
#define GPIO_BOUT_0 (2<<14)
|
||||
#define GPIO_BOUT_1 (3<<14)
|
||||
|
||||
#define GPIO_GIUS (1<<16)
|
||||
|
||||
/* assignements for GPIO alternate/primary functions */
|
||||
|
||||
/* FIXME: This list is not completed. The correct directions are
|
||||
* missing on some (many) pins
|
||||
*/
|
||||
#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
|
||||
#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
|
||||
#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
|
||||
#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
|
||||
#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
|
||||
#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
|
||||
#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
|
||||
#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
|
||||
#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
|
||||
#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
|
||||
#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
|
||||
#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
|
||||
#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
|
||||
#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
|
||||
#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
|
||||
#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
|
||||
#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
|
||||
#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
|
||||
#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
|
||||
#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
|
||||
#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
|
||||
#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
|
||||
#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
|
||||
#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
|
||||
#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
|
||||
#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
|
||||
#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
|
||||
#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
|
||||
#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
|
||||
#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
|
||||
#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
|
||||
#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
|
||||
#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
|
||||
#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
|
||||
#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
|
||||
#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
|
||||
#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
|
||||
#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
|
||||
#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
|
||||
#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
|
||||
#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
|
||||
#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
|
||||
#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
|
||||
#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
|
||||
#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
|
||||
#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
|
||||
#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
|
||||
#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
|
||||
#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
|
||||
#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 )
|
||||
#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
|
||||
#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 )
|
||||
#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
|
||||
#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
|
||||
#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
|
||||
#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
|
||||
#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
|
||||
#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
|
||||
#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
|
||||
#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
|
||||
#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
|
||||
#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
|
||||
#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
|
||||
#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
|
||||
#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
|
||||
#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
|
||||
#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
|
||||
#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
|
||||
#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
|
||||
#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
|
||||
#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
|
||||
#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
|
||||
#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
|
||||
#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
|
||||
#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
|
||||
#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
|
||||
#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
|
||||
#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
|
||||
#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
|
||||
#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
|
||||
#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
|
||||
#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
|
||||
#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
|
||||
#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
|
||||
#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
|
||||
#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
|
||||
#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
|
||||
#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
|
||||
#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
|
||||
#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
|
||||
#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
|
||||
#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
|
||||
#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
|
||||
#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
|
||||
#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
|
||||
#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
|
||||
#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
|
||||
#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
|
||||
#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
|
||||
#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
|
||||
#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
|
||||
#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
|
||||
#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
|
||||
#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
|
||||
#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
|
||||
#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
|
||||
#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
|
||||
#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
|
||||
#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
|
||||
#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
|
||||
#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
|
||||
#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
|
||||
#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
|
||||
#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
|
||||
#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
|
||||
#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
|
||||
#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
|
||||
#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
|
||||
#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
|
||||
#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
|
||||
#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
|
||||
#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
|
||||
#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
|
||||
#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
|
||||
#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
|
||||
#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
|
||||
#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
|
||||
#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
|
||||
#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
|
||||
#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
|
||||
#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
|
||||
|
||||
/*
|
||||
* PWM controller
|
||||
*/
|
||||
#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */
|
||||
#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */
|
||||
#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */
|
||||
#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */
|
||||
|
||||
#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */
|
||||
#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */
|
||||
#define PWMC_SWR (0x01<<16) /* Software Reset */
|
||||
#define PWMC_CLKSRC (0x01<<15) /* Clock Source */
|
||||
#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */
|
||||
#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */
|
||||
#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */
|
||||
#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */
|
||||
#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */
|
||||
#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
|
||||
#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */
|
||||
|
||||
#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
|
||||
#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
|
||||
#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
|
||||
|
||||
/*
|
||||
* DMA Controller
|
||||
*/
|
||||
#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
|
||||
#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
|
||||
#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
|
||||
#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
|
||||
#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
|
||||
#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
|
||||
#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
|
||||
#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
|
||||
#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
|
||||
#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
|
||||
#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
|
||||
#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
|
||||
#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
|
||||
#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
|
||||
#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
|
||||
#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
|
||||
#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
|
||||
#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
|
||||
#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
|
||||
#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
|
||||
#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
|
||||
#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
|
||||
|
||||
/* TODO: define DMA_REQ lines */
|
||||
|
||||
#define DCR_DRST (1<<1)
|
||||
#define DCR_DEN (1<<0)
|
||||
#define DBTOCR_EN (1<<15)
|
||||
#define DBTOCR_CNT(x) ((x) & 0x7fff )
|
||||
#define CNTR_CNT(x) ((x) & 0xffffff )
|
||||
#define CCR_DMOD_LINEAR ( 0x0 << 12 )
|
||||
#define CCR_DMOD_2D ( 0x1 << 12 )
|
||||
#define CCR_DMOD_FIFO ( 0x2 << 12 )
|
||||
#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
|
||||
#define CCR_SMOD_LINEAR ( 0x0 << 10 )
|
||||
#define CCR_SMOD_2D ( 0x1 << 10 )
|
||||
#define CCR_SMOD_FIFO ( 0x2 << 10 )
|
||||
#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
|
||||
#define CCR_MDIR_DEC (1<<9)
|
||||
#define CCR_MSEL_B (1<<8)
|
||||
#define CCR_DSIZ_32 ( 0x0 << 6 )
|
||||
#define CCR_DSIZ_8 ( 0x1 << 6 )
|
||||
#define CCR_DSIZ_16 ( 0x2 << 6 )
|
||||
#define CCR_SSIZ_32 ( 0x0 << 4 )
|
||||
#define CCR_SSIZ_8 ( 0x1 << 4 )
|
||||
#define CCR_SSIZ_16 ( 0x2 << 4 )
|
||||
#define CCR_REN (1<<3)
|
||||
#define CCR_RPT (1<<2)
|
||||
#define CCR_FRC (1<<1)
|
||||
#define CCR_CEN (1<<0)
|
||||
#define RTOR_EN (1<<15)
|
||||
#define RTOR_CLK (1<<14)
|
||||
#define RTOR_PSC (1<<13)
|
||||
|
||||
/*
|
||||
* LCD Controller
|
||||
*/
|
||||
|
||||
#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
|
||||
|
||||
#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
|
||||
#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
|
||||
#define SIZE_YMAX(y) ( (y) & 0x1ff )
|
||||
|
||||
#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
|
||||
#define VPW_VPW(x) ( (x) & 0x3ff )
|
||||
|
||||
#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
|
||||
#define CPOS_CC1 (1<<31)
|
||||
#define CPOS_CC0 (1<<30)
|
||||
#define CPOS_OP (1<<28)
|
||||
#define CPOS_CXP(x) (((x) & 3ff) << 16)
|
||||
#define CPOS_CYP(y) ((y) & 0x1ff)
|
||||
|
||||
#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
|
||||
#define LCWHB_BK_EN (1<<31)
|
||||
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
|
||||
#define LCWHB_CH(h) (((h) & 0x1f) << 16)
|
||||
#define LCWHB_BD(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
|
||||
#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
|
||||
#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
|
||||
#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
|
||||
|
||||
#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
|
||||
#define PCR_TFT (1<<31)
|
||||
#define PCR_COLOR (1<<30)
|
||||
#define PCR_PBSIZ_1 (0<<28)
|
||||
#define PCR_PBSIZ_2 (1<<28)
|
||||
#define PCR_PBSIZ_4 (2<<28)
|
||||
#define PCR_PBSIZ_8 (3<<28)
|
||||
#define PCR_BPIX_1 (0<<25)
|
||||
#define PCR_BPIX_2 (1<<25)
|
||||
#define PCR_BPIX_4 (2<<25)
|
||||
#define PCR_BPIX_8 (3<<25)
|
||||
#define PCR_BPIX_12 (4<<25)
|
||||
#define PCR_BPIX_16 (4<<25)
|
||||
#define PCR_PIXPOL (1<<24)
|
||||
#define PCR_FLMPOL (1<<23)
|
||||
#define PCR_LPPOL (1<<22)
|
||||
#define PCR_CLKPOL (1<<21)
|
||||
#define PCR_OEPOL (1<<20)
|
||||
#define PCR_SCLKIDLE (1<<19)
|
||||
#define PCR_END_SEL (1<<18)
|
||||
#define PCR_END_BYTE_SWAP (1<<17)
|
||||
#define PCR_REV_VS (1<<16)
|
||||
#define PCR_ACD_SEL (1<<15)
|
||||
#define PCR_ACD(x) (((x) & 0x7f) << 8)
|
||||
#define PCR_SCLK_SEL (1<<7)
|
||||
#define PCR_SHARP (1<<6)
|
||||
#define PCR_PCD(x) ((x) & 0x3f)
|
||||
|
||||
#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
|
||||
#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
|
||||
#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
|
||||
#define HCR_H_WAIT_2(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
|
||||
#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
|
||||
#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
|
||||
#define VCR_V_WAIT_2(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
|
||||
#define POS_POS(x) ((x) & 1f)
|
||||
|
||||
#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
|
||||
#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
|
||||
#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
|
||||
#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
|
||||
#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
|
||||
#define LSCR1_GRAY1(x) (((x) & 0xf))
|
||||
|
||||
#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
|
||||
#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
|
||||
#define PWMR_LDMSK (1<<15)
|
||||
#define PWMR_SCR1 (1<<10)
|
||||
#define PWMR_SCR0 (1<<9)
|
||||
#define PWMR_CC_EN (1<<8)
|
||||
#define PWMR_PW(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
|
||||
#define DMACR_BURST (1<<31)
|
||||
#define DMACR_HM(x) (((x) & 0xf) << 16)
|
||||
#define DMACR_TM(x) ((x) &0xf)
|
||||
|
||||
#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
|
||||
#define RMCR_LCDC_EN (1<<1)
|
||||
#define RMCR_SELF_REF (1<<0)
|
||||
|
||||
#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
|
||||
#define LCDICR_INT_SYN (1<<2)
|
||||
#define LCDICR_INT_CON (1)
|
||||
|
||||
#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
|
||||
#define LCDISR_UDR_ERR (1<<3)
|
||||
#define LCDISR_ERR_RES (1<<2)
|
||||
#define LCDISR_EOF (1<<1)
|
||||
#define LCDISR_BOF (1<<0)
|
||||
/*
|
||||
* UART Module
|
||||
*/
|
||||
#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */
|
||||
#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */
|
||||
#define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */
|
||||
#define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */
|
||||
#define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */
|
||||
#define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */
|
||||
#define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */
|
||||
#define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */
|
||||
#define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */
|
||||
#define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */
|
||||
#define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */
|
||||
#define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */
|
||||
#define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */
|
||||
#define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */
|
||||
#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */
|
||||
#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */
|
||||
#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */
|
||||
#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */
|
||||
#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */
|
||||
#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */
|
||||
#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */
|
||||
#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */
|
||||
#define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */
|
||||
|
||||
/* UART Control Register Bit Fields.*/
|
||||
#define URXD_CHARRDY (1<<15)
|
||||
#define URXD_ERR (1<<14)
|
||||
#define URXD_OVRRUN (1<<13)
|
||||
#define URXD_FRMERR (1<<12)
|
||||
#define URXD_BRK (1<<11)
|
||||
#define URXD_PRERR (1<<10)
|
||||
#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
|
||||
#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
|
||||
#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
|
||||
#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
|
||||
#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
|
||||
#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
|
||||
#define UCR1_IREN (1<<7) /* Infrared interface enable */
|
||||
#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
|
||||
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
|
||||
#define UCR1_SNDBRK (1<<4) /* Send break */
|
||||
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
|
||||
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
|
||||
#define UCR1_DOZE (1<<1) /* Doze */
|
||||
#define UCR1_UARTEN (1<<0) /* UART enabled */
|
||||
#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
|
||||
#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
|
||||
#define UCR2_CTSC (1<<13) /* CTS pin control */
|
||||
#define UCR2_CTS (1<<12) /* Clear to send */
|
||||
#define UCR2_ESCEN (1<<11) /* Escape enable */
|
||||
#define UCR2_PREN (1<<8) /* Parity enable */
|
||||
#define UCR2_PROE (1<<7) /* Parity odd/even */
|
||||
#define UCR2_STPB (1<<6) /* Stop */
|
||||
#define UCR2_WS (1<<5) /* Word size */
|
||||
#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
|
||||
#define UCR2_TXEN (1<<2) /* Transmitter enabled */
|
||||
#define UCR2_RXEN (1<<1) /* Receiver enabled */
|
||||
#define UCR2_SRST (1<<0) /* SW reset */
|
||||
#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
|
||||
#define UCR3_PARERREN (1<<12) /* Parity enable */
|
||||
#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
|
||||
#define UCR3_DSR (1<<10) /* Data set ready */
|
||||
#define UCR3_DCD (1<<9) /* Data carrier detect */
|
||||
#define UCR3_RI (1<<8) /* Ring indicator */
|
||||
#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
|
||||
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
|
||||
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
|
||||
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
|
||||
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
|
||||
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
|
||||
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
|
||||
#define UCR3_BPEN (1<<0) /* Preset registers enable */
|
||||
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
|
||||
#define UCR4_INVR (1<<9) /* Inverted infrared reception */
|
||||
#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
|
||||
#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
|
||||
#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
|
||||
#define UCR4_IRSC (1<<5) /* IR special case */
|
||||
#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
|
||||
#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
|
||||
#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
|
||||
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
|
||||
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
|
||||
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
|
||||
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
|
||||
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
|
||||
#define USR1_RTSS (1<<14) /* RTS pin status */
|
||||
#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
|
||||
#define USR1_RTSD (1<<12) /* RTS delta */
|
||||
#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
|
||||
#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
|
||||
#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
|
||||
#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
|
||||
#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
|
||||
#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
|
||||
#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
|
||||
#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
|
||||
#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
|
||||
#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
|
||||
#define USR2_IDLE (1<<12) /* Idle condition */
|
||||
#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
|
||||
#define USR2_WAKE (1<<7) /* Wake */
|
||||
#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
|
||||
#define USR2_TXDC (1<<3) /* Transmitter complete */
|
||||
#define USR2_BRCD (1<<2) /* Break condition */
|
||||
#define USR2_ORE (1<<1) /* Overrun error */
|
||||
#define USR2_RDR (1<<0) /* Recv data ready */
|
||||
#define UTS_FRCPERR (1<<13) /* Force parity error */
|
||||
#define UTS_LOOP (1<<12) /* Loop tx and rx */
|
||||
#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
|
||||
#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
|
||||
#define UTS_TXFULL (1<<4) /* TxFIFO full */
|
||||
#define UTS_RXFULL (1<<3) /* RxFIFO full */
|
||||
#define UTS_SOFTRST (1<<0) /* Software reset */
|
||||
|
||||
/* General purpose timers registers */
|
||||
#define TCTL1 __REG(IMX_TIM1_BASE)
|
||||
#define TPRER1 __REG(IMX_TIM1_BASE + 0x4)
|
||||
#define TCMP1 __REG(IMX_TIM1_BASE + 0x8)
|
||||
#define TCR1 __REG(IMX_TIM1_BASE + 0xc)
|
||||
#define TCN1 __REG(IMX_TIM1_BASE + 0x10)
|
||||
#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14)
|
||||
#define TCTL2 __REG(IMX_TIM2_BASE)
|
||||
#define TPRER2 __REG(IMX_TIM2_BASE + 0x4)
|
||||
#define TCMP2 __REG(IMX_TIM2_BASE + 0x8)
|
||||
#define TCR2 __REG(IMX_TIM2_BASE + 0xc)
|
||||
#define TCN2 __REG(IMX_TIM2_BASE + 0x10)
|
||||
#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14)
|
||||
|
||||
/* General purpose timers bitfields */
|
||||
#define TCTL_SWR (1<<15) /* Software reset */
|
||||
#define TCTL_FRR (1<<8) /* Freerun / restart */
|
||||
#define TCTL_CAP (3<<6) /* Capture Edge */
|
||||
#define TCTL_OM (1<<5) /* output mode */
|
||||
#define TCTL_IRQEN (1<<4) /* interrupt enable */
|
||||
#define TCTL_CLKSOURCE (7<<1) /* Clock source */
|
||||
#define TCTL_TEN (1) /* Timer enable */
|
||||
#define TPRER_PRES (0xff) /* Prescale */
|
||||
#define TSTAT_CAPT (1<<1) /* Capture event */
|
||||
#define TSTAT_COMP (1) /* Compare event */
|
||||
|
||||
#endif /* _IMX_REGS_H */
|
||||
187
u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h
Normal file
187
u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h
Normal file
@@ -0,0 +1,187 @@
|
||||
/*
|
||||
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_CLK_H
|
||||
#define _LPC32XX_CLK_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
#define OSC_CLK_FREQUENCY 13000000
|
||||
#define RTC_CLK_FREQUENCY 32768
|
||||
|
||||
/* Clocking and Power Control Registers */
|
||||
struct clk_pm_regs {
|
||||
u32 reserved0[5];
|
||||
u32 boot_map; /* Boot Map Control Register */
|
||||
u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */
|
||||
u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
|
||||
/* Internal Start Signal Sources Registers */
|
||||
u32 start_er_int; /* Start Enable Register */
|
||||
u32 start_rsr_int; /* Start Raw Status Register */
|
||||
u32 start_sr_int; /* Start Status Register */
|
||||
u32 start_apr_int; /* Start Activation Polarity Register */
|
||||
/* Device Pin Start Signal Sources Registers */
|
||||
u32 start_er_pin; /* Start Enable Register */
|
||||
u32 start_rsr_pin; /* Start Raw Status Register */
|
||||
u32 start_sr_pin; /* Start Status Register */
|
||||
u32 start_apr_pin; /* Start Activation Polarity Register */
|
||||
/* Clock Control Registers */
|
||||
u32 hclkdiv_ctrl; /* HCLK Divider Control Register */
|
||||
u32 pwr_ctrl; /* Power Control Register */
|
||||
u32 pll397_ctrl; /* PLL397 Control Register */
|
||||
u32 osc_ctrl; /* Main Oscillator Control Register */
|
||||
u32 sysclk_ctrl; /* SYSCLK Control Register */
|
||||
u32 lcdclk_ctrl; /* LCD Clock Control Register */
|
||||
u32 hclkpll_ctrl; /* HCLK PLL Control Register */
|
||||
u32 reserved1;
|
||||
u32 adclk_ctrl1; /* ADC Clock Control1 Register */
|
||||
u32 usb_ctrl; /* USB Control Register */
|
||||
u32 sdramclk_ctrl; /* SDRAM Clock Control Register */
|
||||
u32 ddr_lap_nom; /* DDR Calibration Nominal Value */
|
||||
u32 ddr_lap_count; /* DDR Calibration Measured Value */
|
||||
u32 ddr_cal_delay; /* DDR Calibration Delay Value */
|
||||
u32 ssp_ctrl; /* SSP Control Register */
|
||||
u32 i2s_ctrl; /* I2S Clock Control Register */
|
||||
u32 ms_ctrl; /* Memory Card Control Register */
|
||||
u32 reserved2[3];
|
||||
u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */
|
||||
u32 reserved3[4];
|
||||
u32 test_clk; /* Test Clock Selection Register */
|
||||
u32 sw_int; /* Software Interrupt Register */
|
||||
u32 i2cclk_ctrl; /* I2C Clock Control Register */
|
||||
u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */
|
||||
u32 adclk_ctrl; /* ADC Clock Control Register */
|
||||
u32 pwmclk_ctrl; /* PWM Clock Control Register */
|
||||
u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */
|
||||
u32 timclk_ctrl1; /* Motor and Timer Clock Control */
|
||||
u32 spi_ctrl; /* SPI Control Register */
|
||||
u32 flashclk_ctrl; /* NAND Flash Clock Control Register */
|
||||
u32 reserved4;
|
||||
u32 u3clk; /* UART 3 Clock Control Register */
|
||||
u32 u4clk; /* UART 4 Clock Control Register */
|
||||
u32 u5clk; /* UART 5 Clock Control Register */
|
||||
u32 u6clk; /* UART 6 Clock Control Register */
|
||||
u32 irdaclk; /* IrDA Clock Control Register */
|
||||
u32 uartclk_ctrl; /* UART Clock Control Register */
|
||||
u32 dmaclk_ctrl; /* DMA Clock Control Register */
|
||||
u32 autoclk_ctrl; /* Autoclock Control Register */
|
||||
};
|
||||
|
||||
/* HCLK Divider Control Register bits */
|
||||
#define CLK_HCLK_DDRAM_MASK (0x3 << 7)
|
||||
#define CLK_HCLK_DDRAM_HALF (0x2 << 7)
|
||||
#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7)
|
||||
#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7)
|
||||
#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2)
|
||||
#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2)
|
||||
#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0)
|
||||
#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0)
|
||||
#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0)
|
||||
#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0)
|
||||
|
||||
/* Power Control Register bits */
|
||||
#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10)
|
||||
#define CLK_PWR_EMC_SREFREQ (1 << 9)
|
||||
#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8)
|
||||
#define CLK_PWR_SDRAM_SREFREQ (1 << 7)
|
||||
#define CLK_PWR_HIGHCORE_LEVEL (1 << 5)
|
||||
#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4)
|
||||
#define CLK_PWR_SYSCLKEN_CTRL (1 << 3)
|
||||
#define CLK_PWR_NORMAL_RUN (1 << 2)
|
||||
#define CLK_PWR_HIGHCORE_CTRL (1 << 1)
|
||||
#define CLK_PWR_STOP_MODE (1 << 0)
|
||||
|
||||
/* SYSCLK Control Register bits */
|
||||
#define CLK_SYSCLK_PLL397 (1 << 1)
|
||||
#define CLK_SYSCLK_MUX (1 << 0)
|
||||
|
||||
/* HCLK PLL Control Register bits */
|
||||
#define CLK_HCLK_PLL_OPERATING (1 << 16)
|
||||
#define CLK_HCLK_PLL_BYPASS (1 << 15)
|
||||
#define CLK_HCLK_PLL_DIRECT (1 << 14)
|
||||
#define CLK_HCLK_PLL_FEEDBACK (1 << 13)
|
||||
#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11)
|
||||
#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11)
|
||||
#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11)
|
||||
#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11)
|
||||
#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11)
|
||||
#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9)
|
||||
#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9)
|
||||
#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9)
|
||||
#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9)
|
||||
#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9)
|
||||
#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1)
|
||||
#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1)
|
||||
#define CLK_HCLK_PLL_LOCKED (1 << 0)
|
||||
|
||||
/* Ethernet MAC Clock Control Register bits */
|
||||
#define CLK_MAC_RMII (0x3 << 3)
|
||||
#define CLK_MAC_MII (0x1 << 3)
|
||||
#define CLK_MAC_MASTER (1 << 2)
|
||||
#define CLK_MAC_SLAVE (1 << 1)
|
||||
#define CLK_MAC_REG (1 << 0)
|
||||
|
||||
/* I2C Clock Control Register bits */
|
||||
#define CLK_I2C2_ENABLE (1 << 1)
|
||||
#define CLK_I2C1_ENABLE (1 << 0)
|
||||
|
||||
/* Timer Clock Control1 Register bits */
|
||||
#define CLK_TIMCLK_MOTOR (1 << 6)
|
||||
#define CLK_TIMCLK_TIMER3 (1 << 5)
|
||||
#define CLK_TIMCLK_TIMER2 (1 << 4)
|
||||
#define CLK_TIMCLK_TIMER1 (1 << 3)
|
||||
#define CLK_TIMCLK_TIMER0 (1 << 2)
|
||||
#define CLK_TIMCLK_TIMER5 (1 << 1)
|
||||
#define CLK_TIMCLK_TIMER4 (1 << 0)
|
||||
|
||||
/* Timer Clock Control Register bits */
|
||||
#define CLK_TIMCLK_HSTIMER (1 << 1)
|
||||
#define CLK_TIMCLK_WATCHDOG (1 << 0)
|
||||
|
||||
/* UART Clock Control Register bits */
|
||||
#define CLK_UART(n) (1 << ((n) - 3))
|
||||
|
||||
/* UARTn Clock Select Registers bits */
|
||||
#define CLK_UART_HCLK (1 << 16)
|
||||
#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8)
|
||||
#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0)
|
||||
|
||||
/* DMA Clock Control Register bits */
|
||||
#define CLK_DMA_ENABLE (1 << 0)
|
||||
|
||||
/* NAND Clock Control Register bits */
|
||||
#define CLK_NAND_SLC (1 << 0)
|
||||
#define CLK_NAND_MLC (1 << 1)
|
||||
#define CLK_NAND_SLC_SELECT (1 << 2)
|
||||
#define CLK_NAND_MLC_INT (1 << 5)
|
||||
|
||||
/* SSP Clock Control Register bits */
|
||||
#define CLK_SSP0_ENABLE_CLOCK (1 << 0)
|
||||
|
||||
/* SDRAMCLK register bits */
|
||||
#define CLK_SDRAM_DDR_SEL (1 << 1)
|
||||
|
||||
/* USB control register definitions */
|
||||
#define CLK_USBCTRL_PLL_STS (1 << 0)
|
||||
#define CLK_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1)
|
||||
#define CLK_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
|
||||
#define CLK_USBCTRL_PLL_PWRUP (1 << 16)
|
||||
#define CLK_USBCTRL_CLK_EN1 (1 << 17)
|
||||
#define CLK_USBCTRL_CLK_EN2 (1 << 18)
|
||||
#define CLK_USBCTRL_BUS_KEEPER (0x1 << 19)
|
||||
#define CLK_USBCTRL_USBHSTND_EN (1 << 21)
|
||||
#define CLK_USBCTRL_USBDVND_EN (1 << 22)
|
||||
#define CLK_USBCTRL_HCLK_EN (1 << 24)
|
||||
|
||||
unsigned int get_sys_clk_rate(void);
|
||||
unsigned int get_hclk_pll_rate(void);
|
||||
unsigned int get_hclk_clk_div(void);
|
||||
unsigned int get_hclk_clk_rate(void);
|
||||
unsigned int get_periph_clk_div(void);
|
||||
unsigned int get_periph_clk_rate(void);
|
||||
unsigned int get_sdram_clk_rate(void);
|
||||
|
||||
#endif /* _LPC32XX_CLK_H */
|
||||
86
u-boot/arch/arm/include/asm/arch-lpc32xx/config.h
Normal file
86
u-boot/arch/arm/include/asm/arch-lpc32xx/config.h
Normal file
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Common definitions for LPC32XX board configurations
|
||||
*
|
||||
* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_CONFIG_H
|
||||
#define _LPC32XX_CONFIG_H
|
||||
|
||||
|
||||
/* Basic CPU architecture */
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS_MAX 2
|
||||
|
||||
/* UART configuration */
|
||||
#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
|
||||
(CONFIG_SYS_LPC32XX_UART == 7)
|
||||
#if !defined(CONFIG_LPC32XX_HSUART)
|
||||
#define CONFIG_LPC32XX_HSUART
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SYS_NS16550_CLK)
|
||||
#define CONFIG_SYS_NS16550_CLK 13000000
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_LPC32XX_HSUART)
|
||||
#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
|
||||
#else
|
||||
#define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
|
||||
|
||||
/* Ethernet */
|
||||
#define LPC32XX_ETH_BASE ETHERNET_BASE
|
||||
|
||||
/* NAND */
|
||||
#if defined(CONFIG_NAND_LPC32XX_SLC)
|
||||
#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800
|
||||
#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
|
||||
|
||||
#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
|
||||
#endif
|
||||
|
||||
#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
48, 49, 50, 51, 52, 53, 54, 55, \
|
||||
56, 57, 58, 59, 60, 61, 62, 63, }
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 16
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#else
|
||||
#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 0x100
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#endif /* CONFIG_NAND_LPC32XX_SLC */
|
||||
|
||||
/* NOR Flash */
|
||||
#if defined(CONFIG_SYS_FLASH_CFI)
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
#endif
|
||||
|
||||
/* USB OHCI */
|
||||
#if defined(CONFIG_USB_OHCI_LPC32XX)
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci"
|
||||
#endif
|
||||
|
||||
#endif /* _LPC32XX_CONFIG_H */
|
||||
54
u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h
Normal file
54
u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h
Normal file
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_CPU_H
|
||||
#define _LPC32XX_CPU_H
|
||||
|
||||
/* LPC32XX Memory map */
|
||||
|
||||
/* AHB physical base addresses */
|
||||
#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
|
||||
#define SSP0_BASE 0x20084000 /* SSP0 registers base */
|
||||
#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
|
||||
#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
|
||||
#define DMA_BASE 0x31000000 /* DMA controller registers base */
|
||||
#define USB_BASE 0x31020000 /* USB registers base */
|
||||
#define LCD_BASE 0x31040000 /* LCD registers base */
|
||||
#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
|
||||
#define EMC_BASE 0x31080000 /* EMC configuration registers base */
|
||||
|
||||
/* FAB peripherals base addresses */
|
||||
#define CLK_PM_BASE 0x40004000 /* System control registers base */
|
||||
#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */
|
||||
#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */
|
||||
#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */
|
||||
#define RTC_BASE 0x40024000 /* RTC registers base */
|
||||
#define GPIO_BASE 0x40028000 /* GPIO registers base */
|
||||
#define MUX_BASE 0x40028000 /* MUX registers base */
|
||||
#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */
|
||||
#define TIMER0_BASE 0x40044000 /* Timer0 registers base */
|
||||
#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */
|
||||
#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */
|
||||
|
||||
/* APB peripherals base addresses */
|
||||
#define UART3_BASE 0x40080000 /* UART 3 registers base */
|
||||
#define UART4_BASE 0x40088000 /* UART 4 registers base */
|
||||
#define UART5_BASE 0x40090000 /* UART 5 registers base */
|
||||
#define UART6_BASE 0x40098000 /* UART 6 registers base */
|
||||
#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */
|
||||
#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */
|
||||
|
||||
/* External SDRAM Memory Bank base addresses */
|
||||
#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */
|
||||
#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */
|
||||
|
||||
/* External Static Memory Bank base addresses */
|
||||
#define EMC_CS0_BASE 0xE0000000
|
||||
#define EMC_CS1_BASE 0xE1000000
|
||||
#define EMC_CS2_BASE 0xE2000000
|
||||
#define EMC_CS3_BASE 0xE3000000
|
||||
|
||||
#endif /* _LPC32XX_CPU_H */
|
||||
67
u-boot/arch/arm/include/asm/arch-lpc32xx/dma.h
Normal file
67
u-boot/arch/arm/include/asm/arch-lpc32xx/dma.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* LPC32xx DMA Controller Interface
|
||||
*
|
||||
* Copyright (C) 2008 by NXP Semiconductors
|
||||
* @Author: Kevin Wells
|
||||
* @Descr: Definitions for LPC3250 chip
|
||||
* @References: NXP LPC3250 User's Guide
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_DMA_H
|
||||
#define _LPC32XX_DMA_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
/*
|
||||
* DMA linked list structure used with a channel's LLI register;
|
||||
* refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3
|
||||
* tables 84, 85, 86 & 87 for details.
|
||||
*/
|
||||
struct lpc32xx_dmac_ll {
|
||||
u32 dma_src;
|
||||
u32 dma_dest;
|
||||
u32 next_lli;
|
||||
u32 next_ctrl;
|
||||
};
|
||||
|
||||
/* control register definitions */
|
||||
#define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */
|
||||
#define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */
|
||||
#define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */
|
||||
#define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */
|
||||
#define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */
|
||||
#define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */
|
||||
#define DMAC_CHAN_DEST_BURST_1 0
|
||||
#define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */
|
||||
#define DMAC_CHAN_SRC_BURST_1 0
|
||||
#define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */
|
||||
|
||||
/*
|
||||
* config_ch register definitions
|
||||
* DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller
|
||||
* DMAC_DEST_PERIP: Macro for loading destination peripheral
|
||||
* DMAC_SRC_PERIP: Macro for loading source peripheral
|
||||
*/
|
||||
#define DMAC_CHAN_FLOW_D_M2P (0x1 << 11)
|
||||
#define DMAC_CHAN_FLOW_D_P2M (0x2 << 11)
|
||||
#define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6)
|
||||
#define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1)
|
||||
|
||||
/*
|
||||
* config_ch register definitions
|
||||
* (source and destination peripheral ID numbers).
|
||||
* These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros.
|
||||
*/
|
||||
#define DMA_PERID_NAND1 1
|
||||
|
||||
/* Channel enable bit */
|
||||
#define DMAC_CHAN_ENABLE (1 << 0)
|
||||
|
||||
int lpc32xx_dma_get_channel(void);
|
||||
int lpc32xx_dma_start_xfer(unsigned int channel,
|
||||
const struct lpc32xx_dmac_ll *desc, u32 config);
|
||||
int lpc32xx_dma_wait_status(unsigned int channel);
|
||||
|
||||
#endif /* _LPC32XX_DMA_H */
|
||||
100
u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h
Normal file
100
u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h
Normal file
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_EMC_H
|
||||
#define _LPC32XX_EMC_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/* EMC Registers */
|
||||
struct emc_regs {
|
||||
u32 ctrl; /* Controls operation of the EMC */
|
||||
u32 status; /* Provides EMC status information */
|
||||
u32 config; /* Configures operation of the EMC */
|
||||
u32 reserved0[5];
|
||||
u32 control; /* Controls dyn memory operation */
|
||||
u32 refresh; /* Configures dyn memory refresh operation */
|
||||
u32 read_config; /* Configures the dyn memory read strategy */
|
||||
u32 reserved1;
|
||||
u32 t_rp; /* Precharge command period */
|
||||
u32 t_ras; /* Active to precharge command period */
|
||||
u32 t_srex; /* Self-refresh exit time */
|
||||
u32 reserved2[2];
|
||||
u32 t_wr; /* Write recovery time */
|
||||
u32 t_rc; /* Active to active command period */
|
||||
u32 t_rfc; /* Auto-refresh period */
|
||||
u32 t_xsr; /* Exit self-refresh to active command time */
|
||||
u32 t_rrd; /* Active bank A to active bank B latency */
|
||||
u32 t_mrd; /* Load mode register to active command time */
|
||||
u32 t_cdlr; /* Last data in to read command time */
|
||||
u32 reserved3[8];
|
||||
u32 extended_wait; /* time for static memory rd/wr transfers */
|
||||
u32 reserved4[31];
|
||||
u32 config0; /* Configuration information for the SDRAM */
|
||||
u32 rascas0; /* RAS and CAS latencies for the SDRAM */
|
||||
u32 reserved5[6];
|
||||
u32 config1; /* Configuration information for the SDRAM */
|
||||
u32 rascas1; /* RAS and CAS latencies for the SDRAM */
|
||||
u32 reserved6[54];
|
||||
struct emc_stat_t {
|
||||
u32 config; /* Static memory configuration */
|
||||
u32 waitwen; /* Delay from chip select to write enable */
|
||||
u32 waitoen; /* Delay to output enable */
|
||||
u32 waitrd; /* Delay to a read access */
|
||||
u32 waitpage; /* Delay for async page mode read */
|
||||
u32 waitwr; /* Delay to a write access */
|
||||
u32 waitturn; /* Number of bus turnaround cycles */
|
||||
u32 reserved;
|
||||
} stat[4];
|
||||
u32 reserved7[96];
|
||||
struct emc_ahb_t {
|
||||
u32 control; /* Control register for AHB */
|
||||
u32 status; /* Status register for AHB */
|
||||
u32 timeout; /* Timeout register for AHB */
|
||||
u32 reserved[5];
|
||||
} ahb[5];
|
||||
};
|
||||
|
||||
/* Static Memory Configuration Register bits */
|
||||
#define EMC_STAT_CONFIG_WP (1 << 20)
|
||||
#define EMC_STAT_CONFIG_EW (1 << 8)
|
||||
#define EMC_STAT_CONFIG_PB (1 << 7)
|
||||
#define EMC_STAT_CONFIG_PC (1 << 6)
|
||||
#define EMC_STAT_CONFIG_PM (1 << 3)
|
||||
#define EMC_STAT_CONFIG_32BIT (2 << 0)
|
||||
#define EMC_STAT_CONFIG_16BIT (1 << 0)
|
||||
#define EMC_STAT_CONFIG_8BIT (0 << 0)
|
||||
|
||||
/* Static Memory Delay Registers */
|
||||
#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
|
||||
#define EMC_STAT_WAITOEN(n) ((n) & 0x0F)
|
||||
#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
|
||||
#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
|
||||
#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
|
||||
#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)
|
||||
|
||||
/* EMC settings for DRAM */
|
||||
struct emc_dram_settings {
|
||||
u32 cmddelay;
|
||||
u32 config0;
|
||||
u32 rascas0;
|
||||
u32 rdconfig;
|
||||
u32 trp;
|
||||
u32 tras;
|
||||
u32 tsrex;
|
||||
u32 twr;
|
||||
u32 trc;
|
||||
u32 trfc;
|
||||
u32 txsr;
|
||||
u32 trrd;
|
||||
u32 tmrd;
|
||||
u32 tcdlr;
|
||||
u32 refresh;
|
||||
u32 mode;
|
||||
u32 emode;
|
||||
};
|
||||
|
||||
#endif /* _LPC32XX_EMC_H */
|
||||
43
u-boot/arch/arm/include/asm/arch-lpc32xx/gpio.h
Normal file
43
u-boot/arch/arm/include/asm/arch-lpc32xx/gpio.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* LPC32xx GPIO interface
|
||||
*
|
||||
* (C) Copyright 2014 DENX Software Engineering GmbH
|
||||
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/**
|
||||
* GPIO Register map for LPC32xx
|
||||
*/
|
||||
|
||||
struct gpio_regs {
|
||||
u32 p3_inp_state;
|
||||
u32 p3_outp_set;
|
||||
u32 p3_outp_clr;
|
||||
u32 p3_outp_state;
|
||||
/* Watch out! the following are shared between p2 and p3 */
|
||||
u32 p2_p3_dir_set;
|
||||
u32 p2_p3_dir_clr;
|
||||
u32 p2_p3_dir_state;
|
||||
/* Now back to 'one register for one port' */
|
||||
u32 p2_inp_state;
|
||||
u32 p2_outp_set;
|
||||
u32 p2_outp_clr;
|
||||
u32 reserved1[6];
|
||||
u32 p0_inp_state;
|
||||
u32 p0_outp_set;
|
||||
u32 p0_outp_clr;
|
||||
u32 p0_outp_state;
|
||||
u32 p0_dir_set;
|
||||
u32 p0_dir_clr;
|
||||
u32 p0_dir_state;
|
||||
u32 reserved2;
|
||||
u32 p1_inp_state;
|
||||
u32 p1_outp_set;
|
||||
u32 p1_outp_clr;
|
||||
u32 p1_outp_state;
|
||||
u32 p1_dir_set;
|
||||
u32 p1_dir_clr;
|
||||
u32 p1_dir_state;
|
||||
};
|
||||
40
u-boot/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
Normal file
40
u-boot/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
Normal file
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* LPC32xx GPIO interface macro for pin mapping.
|
||||
*
|
||||
* (C) Copyright 2015 DENX Software Engineering GmbH
|
||||
* Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_GPIO_GRP_H
|
||||
#define _LPC32XX_GPIO_GRP_H
|
||||
|
||||
/*
|
||||
* Macro to map the pin for the lpc32xx_gpio driver.
|
||||
* Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
|
||||
* mapping is done per register, as group of 32.
|
||||
* (see drivers/gpio/lpc32xx_gpio.c for details).
|
||||
* - macros can be use with the following pins:
|
||||
* P0.0 - P0.7
|
||||
* P1.0 - P1.23
|
||||
* P2.0 - P2.12
|
||||
* P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
|
||||
* P3 GPO_0 - GPO_23
|
||||
* P3 GPIO_0 - GPIO_5 (output register only)
|
||||
*/
|
||||
#define LPC32XX_GPIO_P0_GRP 0
|
||||
#define LPC32XX_GPIO_P1_GRP 32
|
||||
#define LPC32XX_GPIO_P2_GRP 64
|
||||
#define LPC32XX_GPO_P3_GRP 96
|
||||
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
|
||||
#define LPC32XX_GPI_P3_GRP 128
|
||||
|
||||
/*
|
||||
* A specific GPIO can be selected with this macro
|
||||
* ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
|
||||
* See the LPC32x0 User's guide for GPIO group numbers
|
||||
*/
|
||||
#define LPC32XX_GPIO(x, y) ((x) + (y))
|
||||
|
||||
#endif /* _LPC32XX_GPIO_GRP_H */
|
||||
35
u-boot/arch/arm/include/asm/arch-lpc32xx/mux.h
Normal file
35
u-boot/arch/arm/include/asm/arch-lpc32xx/mux.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* LPC32xx MUX interface
|
||||
*
|
||||
* (C) Copyright 2015 DENX Software Engineering GmbH
|
||||
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/**
|
||||
* MUX register map for LPC32xx
|
||||
*/
|
||||
|
||||
struct mux_regs {
|
||||
u32 reserved1[10];
|
||||
u32 p2_mux_set;
|
||||
u32 p2_mux_clr;
|
||||
u32 p2_mux_state;
|
||||
u32 reserved2[51];
|
||||
u32 p_mux_set;
|
||||
u32 p_mux_clr;
|
||||
u32 p_mux_state;
|
||||
u32 reserved3;
|
||||
u32 p3_mux_set;
|
||||
u32 p3_mux_clr;
|
||||
u32 p3_mux_state;
|
||||
u32 reserved4;
|
||||
u32 p0_mux_set;
|
||||
u32 p0_mux_clr;
|
||||
u32 p0_mux_state;
|
||||
u32 reserved5;
|
||||
u32 p1_mux_set;
|
||||
u32 p1_mux_clr;
|
||||
u32 p1_mux_state;
|
||||
};
|
||||
23
u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
Normal file
23
u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_SYS_PROTO_H
|
||||
#define _LPC32XX_SYS_PROTO_H
|
||||
|
||||
#include <asm/arch/emc.h>
|
||||
|
||||
void lpc32xx_uart_init(unsigned int uart_id);
|
||||
void lpc32xx_dma_init(void);
|
||||
void lpc32xx_mac_init(void);
|
||||
void lpc32xx_mlc_nand_init(void);
|
||||
void lpc32xx_slc_nand_init(void);
|
||||
void lpc32xx_i2c_init(unsigned int devnum);
|
||||
void lpc32xx_ssp_init(void);
|
||||
void lpc32xx_usb_init(void);
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
void ddr_init(const struct emc_dram_settings *dram);
|
||||
#endif
|
||||
#endif /* _LPC32XX_SYS_PROTO_H */
|
||||
61
u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h
Normal file
61
u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h
Normal file
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_TIMER_H
|
||||
#define _LPC32XX_TIMER_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/* Timer/Counter Registers */
|
||||
struct timer_regs {
|
||||
u32 ir; /* Interrupt Register */
|
||||
u32 tcr; /* Timer Control Register */
|
||||
u32 tc; /* Timer Counter */
|
||||
u32 pr; /* Prescale Register */
|
||||
u32 pc; /* Prescale Counter */
|
||||
u32 mcr; /* Match Control Register */
|
||||
u32 mr[4]; /* Match Registers */
|
||||
u32 ccr; /* Capture Control Register */
|
||||
u32 cr[4]; /* Capture Registers */
|
||||
u32 emr; /* External Match Register */
|
||||
u32 reserved[12];
|
||||
u32 ctcr; /* Count Control Register */
|
||||
};
|
||||
|
||||
/* Timer/Counter Interrupt Register bits */
|
||||
#define TIMER_IR_CR(n) (1 << ((n) + 4))
|
||||
#define TIMER_IR_MR(n) (1 << (n))
|
||||
|
||||
/* Timer/Counter Timer Control Register bits */
|
||||
#define TIMER_TCR_COUNTER_RESET (1 << 1)
|
||||
#define TIMER_TCR_COUNTER_ENABLE (1 << 0)
|
||||
#define TIMER_TCR_COUNTER_DISABLE (0 << 0)
|
||||
|
||||
/* Timer/Counter Match Control Register bits */
|
||||
#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2))
|
||||
#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1))
|
||||
#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n)))
|
||||
|
||||
/* Timer/Counter Capture Control Register bits */
|
||||
#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2))
|
||||
#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1))
|
||||
#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n)))
|
||||
|
||||
/* Timer/Counter External Match Register bits */
|
||||
#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4))
|
||||
#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4))
|
||||
#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4))
|
||||
#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4))
|
||||
#define TIMER_EMR_EM(n) (1 << (n))
|
||||
|
||||
/* Timer/Counter Count Control Register bits */
|
||||
#define TIMER_CTCR_INPUT(n) ((n) << 2)
|
||||
#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
|
||||
#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
|
||||
#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
|
||||
#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
|
||||
|
||||
#endif /* _LPC32XX_TIMER_H */
|
||||
101
u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h
Normal file
101
u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h
Normal file
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_UART_H
|
||||
#define _LPC32XX_UART_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/* 14-clock UART Registers */
|
||||
struct hsuart_regs {
|
||||
union {
|
||||
u32 rx; /* Receiver FIFO */
|
||||
u32 tx; /* Transmitter FIFO */
|
||||
};
|
||||
u32 level; /* FIFO Level Register */
|
||||
u32 iir; /* Interrupt ID Register */
|
||||
u32 ctrl; /* Control Register */
|
||||
u32 rate; /* Rate Control Register */
|
||||
};
|
||||
|
||||
/* 14-clock UART Receiver FIFO Register bits */
|
||||
#define HSUART_RX_BREAK (1 << 10)
|
||||
#define HSUART_RX_ERROR (1 << 9)
|
||||
#define HSUART_RX_EMPTY (1 << 8)
|
||||
#define HSUART_RX_DATA (0xff << 0)
|
||||
|
||||
/* 14-clock UART Level Register bits */
|
||||
#define HSUART_LEVEL_TX (0xff << 8)
|
||||
#define HSUART_LEVEL_RX (0xff << 0)
|
||||
|
||||
/* 14-clock UART Interrupt Identification Register bits */
|
||||
#define HSUART_IIR_TX_INT_SET (1 << 6)
|
||||
#define HSUART_IIR_RX_OE (1 << 5)
|
||||
#define HSUART_IIR_BRK (1 << 4)
|
||||
#define HSUART_IIR_FE (1 << 3)
|
||||
#define HSUART_IIR_RX_TIMEOUT (1 << 2)
|
||||
#define HSUART_IIR_RX_TRIG (1 << 1)
|
||||
#define HSUART_IIR_TX (1 << 0)
|
||||
|
||||
/* 14-clock UART Control Register bits */
|
||||
#define HSUART_CTRL_HRTS_INV (1 << 21)
|
||||
#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19)
|
||||
#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19)
|
||||
#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19)
|
||||
#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19)
|
||||
#define HSUART_CTRL_HRTS_EN (1 << 18)
|
||||
#define HSUART_CTRL_TMO_16 (0x3 << 16)
|
||||
#define HSUART_CTRL_TMO_8 (0x2 << 16)
|
||||
#define HSUART_CTRL_TMO_4 (0x1 << 16)
|
||||
#define HSUART_CTRL_TMO_DISABLED (0x0 << 16)
|
||||
#define HSUART_CTRL_HCTS_INV (1 << 15)
|
||||
#define HSUART_CTRL_HCTS_EN (1 << 14)
|
||||
#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9)
|
||||
#define HSUART_CTRL_HSU_BREAK (1 << 8)
|
||||
#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7)
|
||||
#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6)
|
||||
#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5)
|
||||
#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2)
|
||||
#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2)
|
||||
#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2)
|
||||
#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2)
|
||||
#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2)
|
||||
#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2)
|
||||
#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0)
|
||||
#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0)
|
||||
#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0)
|
||||
#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0)
|
||||
|
||||
/* UART Control Registers */
|
||||
struct uart_ctrl_regs {
|
||||
u32 ctrl; /* Control Register */
|
||||
u32 clkmode; /* Clock Mode Register */
|
||||
u32 loop; /* Loopback Control Register */
|
||||
};
|
||||
|
||||
/* UART Control Register bits */
|
||||
#define UART_CTRL_UART3_MD_CTRL (1 << 11)
|
||||
#define UART_CTRL_HDPX_INV (1 << 10)
|
||||
#define UART_CTRL_HDPX_EN (1 << 9)
|
||||
#define UART_CTRL_UART6_IRDA (1 << 5)
|
||||
#define UART_CTRL_IR_TX6_INV (1 << 4)
|
||||
#define UART_CTRL_IR_RX6_INV (1 << 3)
|
||||
#define UART_CTRL_IR_RX_LENGTH (1 << 2)
|
||||
#define UART_CTRL_IR_TX_LENGTH (1 << 1)
|
||||
#define UART_CTRL_UART5_USB_MODE (1 << 0)
|
||||
|
||||
/* UART Clock Mode Register bits */
|
||||
#define UART_CLKMODE_STATX(n) (1 << ((n) + 16))
|
||||
#define UART_CLKMODE_STAT (1 << 14)
|
||||
#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2))
|
||||
#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2))
|
||||
#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2))
|
||||
#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2))
|
||||
|
||||
/* UART Loopback Control Register bits */
|
||||
#define UART_LOOPBACK(n) (1 << ((n) - 1))
|
||||
|
||||
#endif /* _LPC32XX_UART_H */
|
||||
38
u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h
Normal file
38
u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_WDT_H
|
||||
#define _LPC32XX_WDT_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/* Watchdog Timer Registers */
|
||||
struct wdt_regs {
|
||||
u32 isr; /* Interrupt Status Register */
|
||||
u32 ctrl; /* Control Register */
|
||||
u32 counter; /* Counter Value Register */
|
||||
u32 mctrl; /* Match Control Register */
|
||||
u32 match0; /* Match 0 Register */
|
||||
u32 emr; /* External Match Control Register */
|
||||
u32 pulse; /* Reset Pulse Length Register */
|
||||
u32 res; /* Reset Source Register */
|
||||
};
|
||||
|
||||
/* Watchdog Timer Control Register bits */
|
||||
#define WDTIM_CTRL_PAUSE_EN (1 << 2)
|
||||
#define WDTIM_CTRL_RESET_COUNT (1 << 1)
|
||||
#define WDTIM_CTRL_COUNT_ENAB (1 << 0)
|
||||
|
||||
/* Watchdog Timer Match Control Register bits */
|
||||
#define WDTIM_MCTRL_RESFRC2 (1 << 6)
|
||||
#define WDTIM_MCTRL_RESFRC1 (1 << 5)
|
||||
#define WDTIM_MCTRL_M_RES2 (1 << 4)
|
||||
#define WDTIM_MCTRL_M_RES1 (1 << 3)
|
||||
#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2)
|
||||
#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1)
|
||||
#define WDTIM_MCTRL_MR0_INT (1 << 0)
|
||||
|
||||
#endif /* _LPC32XX_WDT_H */
|
||||
23
u-boot/arch/arm/include/asm/arch-ls102xa/clock.h
Normal file
23
u-boot/arch/arm/include/asm/arch-ls102xa/clock.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
|
||||
#define __ASM_ARCH_LS102XA_CLOCK_H_
|
||||
|
||||
#include <common.h>
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_UART_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_DSPI_CLK,
|
||||
};
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */
|
||||
144
u-boot/arch/arm/include/asm/arch-ls102xa/config.h
Normal file
144
u-boot/arch/arm/include/asm/arch-ls102xa/config.h
Normal file
@@ -0,0 +1,144 @@
|
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV7_LS102XA_CONFIG_
|
||||
#define _ASM_ARMV7_LS102XA_CONFIG_
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
#define OCRAM_BASE_ADDR 0x10000000
|
||||
#define OCRAM_SIZE 0x00020000
|
||||
#define OCRAM_BASE_S_ADDR 0x10010000
|
||||
#define OCRAM_S_SIZE 0x00010000
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_DCSRBAR 0x20000000
|
||||
|
||||
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
|
||||
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
|
||||
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
|
||||
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
|
||||
#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_LS102XA_USB1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
|
||||
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
|
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
|
||||
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
|
||||
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
|
||||
|
||||
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
|
||||
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
|
||||
|
||||
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
|
||||
|
||||
#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
|
||||
|
||||
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
|
||||
|
||||
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
|
||||
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
|
||||
#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
|
||||
#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
|
||||
#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
|
||||
#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
|
||||
/*
|
||||
* TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
|
||||
* So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
|
||||
*/
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
|
||||
CONFIG_SYS_PCIE1_VIRT_ADDR)
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
|
||||
CONFIG_SYS_PCIE2_VIRT_ADDR)
|
||||
|
||||
/* SATA */
|
||||
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
#define CONFIG_SCSI
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_SCSI_AHCI
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
CONFIG_SYS_SCSI_MAX_LUN)
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008407
|
||||
|
||||
#ifdef CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_FSL_DDR_BE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
#define CONFIG_SYS_FSL_QSPI_BE
|
||||
#define CONFIG_SYS_FSL_DCU_BE
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
#define CONFIG_SYS_FSL_SEC_LE
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
#define DCU_LAYER_MAX_NUM 16
|
||||
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
|
||||
#ifdef CONFIG_LS102XA
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008378
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009663
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
||||
#define FSL_IFC_COMPAT "fsl,ifc"
|
||||
#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi"
|
||||
#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi"
|
||||
|
||||
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
|
||||
33
u-boot/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
Normal file
33
u-boot/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H
|
||||
#define __FSL_SERDES_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
SATA1,
|
||||
SGMII_TSEC1,
|
||||
SGMII_TSEC2,
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
void fsl_serdes_init(void);
|
||||
const char *serdes_clock_to_string(u32 clock);
|
||||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
|
||||
|
||||
#endif /* __FSL_SERDES_H */
|
||||
17
u-boot/arch/arm/include/asm/arch-ls102xa/gpio.h
Normal file
17
u-boot/arch/arm/include/asm/arch-ls102xa/gpio.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* Dummy header file to enable CONFIG_OF_CONTROL.
|
||||
* If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
|
||||
* It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
|
||||
* OF_CONTROL must have arch/gpio.h.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_LS102XA_GPIO_H_
|
||||
#define __ASM_ARCH_LS102XA_GPIO_H_
|
||||
|
||||
#endif
|
||||
438
u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
Normal file
438
u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
Normal file
@@ -0,0 +1,438 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
|
||||
#define __ASM_ARCH_LS102XA_IMMAP_H_
|
||||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
|
||||
#define IS_E_PROCESSOR(svr) (svr & 0x80000)
|
||||
#define IS_SVR_REV(svr, maj, min) \
|
||||
((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
|
||||
|
||||
#define SOC_VER_SLS1020 0x00
|
||||
#define SOC_VER_LS1020 0x10
|
||||
#define SOC_VER_LS1021 0x11
|
||||
#define SOC_VER_LS1022 0x12
|
||||
|
||||
#define SOC_MAJOR_VER_1_0 0x1
|
||||
#define SOC_MAJOR_VER_2_0 0x2
|
||||
|
||||
#define CCSR_BRR_OFFSET 0xe4
|
||||
#define CCSR_SCRATCHRW1_OFFSET 0x200
|
||||
|
||||
#define RCWSR0_SYS_PLL_RAT_SHIFT 25
|
||||
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
|
||||
#define RCWSR0_MEM_PLL_RAT_SHIFT 16
|
||||
#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
|
||||
#define RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
|
||||
|
||||
#define TIMER_COMP_VAL 0xffffffffffffffffull
|
||||
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
|
||||
#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
|
||||
|
||||
#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
|
||||
#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
|
||||
|
||||
#define DCFG_DCSR_PORCR1 0
|
||||
|
||||
/*
|
||||
* Define default values for some CCSR macros to make header files cleaner
|
||||
*
|
||||
* To completely disable CCSR relocation in a board header file, define
|
||||
* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
|
||||
* to a value that is the same as CONFIG_SYS_CCSRBAR.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_CCSRBAR_PHYS
|
||||
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
|
||||
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
||||
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR
|
||||
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
|
||||
#else
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
|
||||
CONFIG_SYS_CCSRBAR_PHYS_LOW)
|
||||
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
unsigned long freq_localbus;
|
||||
};
|
||||
|
||||
/* Device Configuration and Pin Control */
|
||||
struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2;
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
u8 res_02c[0x70-0x2c];
|
||||
u32 devdisr; /* Device disable control */
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
u32 devdisr4; /* Device disable control 4 */
|
||||
u32 devdisr5; /* Device disable control 5 */
|
||||
u8 res_084[0x94-0x84];
|
||||
u32 coredisru; /* uppper portion for support of 64 cores */
|
||||
u32 coredisrl; /* lower portion for support of 64 cores */
|
||||
u8 res_09c[0xa4-0x9c];
|
||||
u32 svr; /* System version */
|
||||
u8 res_0a8[0xb0-0xa8];
|
||||
u32 rstcr; /* Reset control */
|
||||
u32 rstrqpblsr; /* Reset request preboot loader status */
|
||||
u8 res_0b8[0xc0-0xb8];
|
||||
u32 rstrqmr1; /* Reset request mask */
|
||||
u8 res_0c4[0xc8-0xc4];
|
||||
u32 rstrqsr1; /* Reset request status */
|
||||
u8 res_0cc[0xd4-0xcc];
|
||||
u32 rstrqwdtmrl; /* Reset request WDT mask */
|
||||
u8 res_0d8[0xdc-0xd8];
|
||||
u32 rstrqwdtsrl; /* Reset request WDT status */
|
||||
u8 res_0e0[0xe4-0xe0];
|
||||
u32 brrl; /* Boot release */
|
||||
u8 res_0e8[0x100-0xe8];
|
||||
u32 rcwsr[16]; /* Reset control word status */
|
||||
#define RCW_SB_EN_REG_INDEX 7
|
||||
#define RCW_SB_EN_MASK 0x00200000
|
||||
u8 res_140[0x200-0x140];
|
||||
u32 scratchrw[4]; /* Scratch Read/Write */
|
||||
u8 res_210[0x300-0x210];
|
||||
u32 scratchw1r[4]; /* Scratch Read (Write once) */
|
||||
u8 res_310[0x400-0x310];
|
||||
u32 crstsr;
|
||||
u8 res_404[0x550-0x404];
|
||||
u32 sataliodnr;
|
||||
u8 res_554[0x604-0x554];
|
||||
u32 pamubypenr;
|
||||
u32 dmacr1;
|
||||
u8 res_60c[0x740-0x60c]; /* add more registers when needed */
|
||||
u32 tp_ityp[64]; /* Topology Initiator Type Register */
|
||||
struct {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
} tp_cluster[1]; /* Core Cluster n Topology Register */
|
||||
u8 res_848[0xe60-0x848];
|
||||
u32 ddrclkdr;
|
||||
u8 res_e60[0xe68-0xe64];
|
||||
u32 ifcclkdr;
|
||||
u8 res_e68[0xe80-0xe6c];
|
||||
u32 sdhcpcr;
|
||||
};
|
||||
|
||||
#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
|
||||
#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
|
||||
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
|
||||
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
|
||||
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
|
||||
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
|
||||
#define SCFG_QSPI_CLKSEL 0xc0100000
|
||||
#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
|
||||
#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000
|
||||
#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000
|
||||
#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000
|
||||
#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000
|
||||
#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000
|
||||
#define SCFG_ENDIANCR_LE 0x80000000
|
||||
|
||||
/* Supplemental Configuration Unit */
|
||||
struct ccsr_scfg {
|
||||
u32 dpslpcr;
|
||||
u32 resv0[2];
|
||||
u32 etsecclkdpslpcr;
|
||||
u32 resv1[5];
|
||||
u32 fuseovrdcr;
|
||||
u32 pixclkcr;
|
||||
u32 resv2[5];
|
||||
u32 spimsicr;
|
||||
u32 resv3[6];
|
||||
u32 pex1pmwrcr;
|
||||
u32 pex1pmrdsr;
|
||||
u32 resv4[3];
|
||||
u32 usb3prm1cr;
|
||||
u32 usb4prm2cr;
|
||||
u32 pex1rdmsgpldlsbsr;
|
||||
u32 pex1rdmsgpldmsbsr;
|
||||
u32 pex2rdmsgpldlsbsr;
|
||||
u32 pex2rdmsgpldmsbsr;
|
||||
u32 pex1rdmmsgrqsr;
|
||||
u32 pex2rdmmsgrqsr;
|
||||
u32 spimsiclrcr;
|
||||
u32 pexmscportsr[2];
|
||||
u32 pex2pmwrcr;
|
||||
u32 resv5[24];
|
||||
u32 mac1_streamid;
|
||||
u32 mac2_streamid;
|
||||
u32 mac3_streamid;
|
||||
u32 pex1_streamid;
|
||||
u32 pex2_streamid;
|
||||
u32 dma_streamid;
|
||||
u32 sata_streamid;
|
||||
u32 usb3_streamid;
|
||||
u32 qe_streamid;
|
||||
u32 sdhc_streamid;
|
||||
u32 adma_streamid;
|
||||
u32 letechsftrstcr;
|
||||
u32 core0_sft_rst;
|
||||
u32 core1_sft_rst;
|
||||
u32 resv6[1];
|
||||
u32 usb_hi_addr;
|
||||
u32 etsecclkadjcr;
|
||||
u32 sai_clk;
|
||||
u32 resv7[1];
|
||||
u32 dcu_streamid;
|
||||
u32 usb2_streamid;
|
||||
u32 ftm_reset;
|
||||
u32 altcbar;
|
||||
u32 qspi_cfg;
|
||||
u32 pmcintecr;
|
||||
u32 pmcintlecr;
|
||||
u32 pmcintsr;
|
||||
u32 qos1;
|
||||
u32 qos2;
|
||||
u32 qos3;
|
||||
u32 cci_cfg;
|
||||
u32 endiancr;
|
||||
u32 etsecdmamcr;
|
||||
u32 usb3prm3cr;
|
||||
u32 resv9[1];
|
||||
u32 debug_streamid;
|
||||
u32 resv10[5];
|
||||
u32 snpcnfgcr;
|
||||
u32 resv11[1];
|
||||
u32 intpcr;
|
||||
u32 resv12[20];
|
||||
u32 scfgrevcr;
|
||||
u32 coresrencr;
|
||||
u32 pex2pmrdsr;
|
||||
u32 eddrtqcfg;
|
||||
u32 ddrc2cr;
|
||||
u32 ddrc3cr;
|
||||
u32 ddrc4cr;
|
||||
u32 ddrgcr;
|
||||
u32 resv13[120];
|
||||
u32 qeioclkcr;
|
||||
u32 etsecmcr;
|
||||
u32 sdhciovserlcr;
|
||||
u32 resv14[61];
|
||||
u32 sparecr[8];
|
||||
};
|
||||
|
||||
/* Clocking */
|
||||
struct ccsr_clk {
|
||||
struct {
|
||||
u32 clkcncsr; /* core cluster n clock control status */
|
||||
u8 res_004[0x1c];
|
||||
} clkcsr[2];
|
||||
u8 res_040[0x7c0]; /* 0x100 */
|
||||
struct {
|
||||
u32 pllcngsr;
|
||||
u8 res_804[0x1c];
|
||||
} pllcgsr[2];
|
||||
u8 res_840[0x1c0];
|
||||
u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
|
||||
u8 res_a04[0x1fc];
|
||||
u32 pllpgsr; /* 0xc00 Platform PLL General Status */
|
||||
u8 res_c04[0x1c];
|
||||
u32 plldgsr; /* 0xc20 DDR PLL General Status */
|
||||
u8 res_c24[0x3dc];
|
||||
};
|
||||
|
||||
/* System Counter */
|
||||
struct sctr_regs {
|
||||
u32 cntcr;
|
||||
u32 cntsr;
|
||||
u32 cntcv1;
|
||||
u32 cntcv2;
|
||||
u32 resv1[4];
|
||||
u32 cntfid0;
|
||||
u32 cntfid1;
|
||||
u32 resv2[1002];
|
||||
u32 counterid[12];
|
||||
};
|
||||
|
||||
#define MAX_SERDES 1
|
||||
#define SRDS_MAX_LANES 4
|
||||
#define SRDS_MAX_BANK 2
|
||||
|
||||
#define SRDS_RSTCTL_RST 0x80000000
|
||||
#define SRDS_RSTCTL_RSTDONE 0x40000000
|
||||
#define SRDS_RSTCTL_RSTERR 0x20000000
|
||||
#define SRDS_RSTCTL_SWRST 0x10000000
|
||||
#define SRDS_RSTCTL_SDEN 0x00000020
|
||||
#define SRDS_RSTCTL_SDRST_B 0x00000040
|
||||
#define SRDS_RSTCTL_PLLRST_B 0x00000080
|
||||
#define SRDS_PLLCR0_POFF 0x80000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
|
||||
#define SRDS_PLLCR0_PLL_LCK 0x00800000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
|
||||
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
|
||||
|
||||
struct ccsr_serdes {
|
||||
struct {
|
||||
u32 rstctl; /* Reset Control Register */
|
||||
|
||||
u32 pllcr0; /* PLL Control Register 0 */
|
||||
|
||||
u32 pllcr1; /* PLL Control Register 1 */
|
||||
u32 res_0c; /* 0x00c */
|
||||
u32 pllcr3;
|
||||
u32 pllcr4;
|
||||
u8 res_18[0x20-0x18];
|
||||
} bank[2];
|
||||
u8 res_40[0x90-0x40];
|
||||
u32 srdstcalcr; /* 0x90 TX Calibration Control */
|
||||
u8 res_94[0xa0-0x94];
|
||||
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
|
||||
u8 res_a4[0xb0-0xa4];
|
||||
u32 srdsgr0; /* 0xb0 General Register 0 */
|
||||
u8 res_b4[0xe0-0xb4];
|
||||
u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
|
||||
u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
|
||||
u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
|
||||
u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
|
||||
u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
|
||||
u8 res_f4[0x100-0xf4];
|
||||
struct {
|
||||
u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
|
||||
u8 res_104[0x120-0x104];
|
||||
} srdslnpssr[4];
|
||||
u8 res_180[0x300-0x180];
|
||||
u32 srdspexeqcr;
|
||||
u32 srdspexeqpcr[11];
|
||||
u8 res_330[0x400-0x330];
|
||||
u32 srdspexapcr;
|
||||
u8 res_404[0x440-0x404];
|
||||
u32 srdspexbpcr;
|
||||
u8 res_444[0x800-0x444];
|
||||
struct {
|
||||
u32 gcr0; /* 0x800 General Control Register 0 */
|
||||
u32 gcr1; /* 0x804 General Control Register 1 */
|
||||
u32 gcr2; /* 0x808 General Control Register 2 */
|
||||
u32 sscr0;
|
||||
u32 recr0; /* 0x810 Receive Equalization Control */
|
||||
u32 recr1;
|
||||
u32 tecr0; /* 0x818 Transmit Equalization Control */
|
||||
u32 sscr1;
|
||||
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
|
||||
u8 res_824[0x83c-0x824];
|
||||
u32 tcsr3;
|
||||
} lane[4]; /* Lane A, B, C, D, E, F, G, H */
|
||||
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
|
||||
};
|
||||
|
||||
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
|
||||
#define CCI400_CTRLORD_EN_BARRIER 0
|
||||
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
|
||||
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
|
||||
#define CCI400_SNOOP_REQ_EN 0x00000001
|
||||
|
||||
/* CCI-400 registers */
|
||||
struct ccsr_cci400 {
|
||||
u32 ctrl_ord; /* Control Override */
|
||||
u32 spec_ctrl; /* Speculation Control */
|
||||
u32 secure_access; /* Secure Access */
|
||||
u32 status; /* Status */
|
||||
u32 impr_err; /* Imprecise Error */
|
||||
u8 res_14[0x100 - 0x14];
|
||||
u32 pmcr; /* Performance Monitor Control */
|
||||
u8 res_104[0xfd0 - 0x104];
|
||||
u32 pid[8]; /* Peripheral ID */
|
||||
u32 cid[4]; /* Component ID */
|
||||
struct {
|
||||
u32 snoop_ctrl; /* Snoop Control */
|
||||
u32 sha_ord; /* Shareable Override */
|
||||
u8 res_1008[0x1100 - 0x1008];
|
||||
u32 rc_qos_ord; /* read channel QoS Value Override */
|
||||
u32 wc_qos_ord; /* read channel QoS Value Override */
|
||||
u8 res_1108[0x110c - 0x1108];
|
||||
u32 qos_ctrl; /* QoS Control */
|
||||
u32 max_ot; /* Max OT */
|
||||
u8 res_1114[0x1130 - 0x1114];
|
||||
u32 target_lat; /* Target Latency */
|
||||
u32 latency_regu; /* Latency Regulation */
|
||||
u32 qos_range; /* QoS Range */
|
||||
u8 res_113c[0x2000 - 0x113c];
|
||||
} slave[5]; /* Slave Interface */
|
||||
u8 res_6000[0x9004 - 0x6000];
|
||||
u32 cycle_counter; /* Cycle counter */
|
||||
u32 count_ctrl; /* Count Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_9010[0xa000 - 0x9010];
|
||||
struct {
|
||||
u32 event_select; /* Event Select */
|
||||
u32 event_count; /* Event Count */
|
||||
u32 counter_ctrl; /* Counter Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_a010[0xb000 - 0xa010];
|
||||
} pcounter[4]; /* Performance Counter */
|
||||
u8 res_e004[0x10000 - 0xe004];
|
||||
};
|
||||
|
||||
/* AHCI (sata) register map */
|
||||
struct ccsr_ahci {
|
||||
u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
|
||||
u32 pcfg; /* port config */
|
||||
u32 ppcfg; /* port phy1 config */
|
||||
u32 pp2c; /* port phy2 config */
|
||||
u32 pp3c; /* port phy3 config */
|
||||
u32 pp4c; /* port phy4 config */
|
||||
u32 pp5c; /* port phy5 config */
|
||||
u32 paxic; /* port AXI config */
|
||||
u32 axicc; /* AXI cache control */
|
||||
u32 axipc; /* AXI PROT control */
|
||||
u32 ptc; /* port Trans Config */
|
||||
u32 pts; /* port Trans Status */
|
||||
u32 plc; /* port link config */
|
||||
u32 plc1; /* port link config1 */
|
||||
u32 plc2; /* port link config2 */
|
||||
u32 pls; /* port link status */
|
||||
u32 pls1; /* port link status1 */
|
||||
u32 pcmdc; /* port CMD config */
|
||||
u32 ppcs; /* port phy control status */
|
||||
u32 pberr; /* port 0/1 BIST error */
|
||||
u32 cmds; /* port 0/1 CMD status error */
|
||||
};
|
||||
|
||||
uint get_svr(void);
|
||||
|
||||
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
|
||||
53
u-boot/arch/arm/include/asm/arch-ls102xa/imx-regs.h
Normal file
53
u-boot/arch/arm/include/asm/arch-ls102xa/imx-regs.h
Normal file
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX_REGS_H__
|
||||
#define __ASM_ARCH_IMX_REGS_H__
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#ifdef CONFIG_LPUART_32B_REG
|
||||
struct lpuart_fsl {
|
||||
u32 baud;
|
||||
u32 stat;
|
||||
u32 ctrl;
|
||||
u32 data;
|
||||
u32 match;
|
||||
u32 modir;
|
||||
u32 fifo;
|
||||
u32 water;
|
||||
};
|
||||
#else
|
||||
struct lpuart_fsl {
|
||||
u8 ubdh;
|
||||
u8 ubdl;
|
||||
u8 uc1;
|
||||
u8 uc2;
|
||||
u8 us1;
|
||||
u8 us2;
|
||||
u8 uc3;
|
||||
u8 ud;
|
||||
u8 uma1;
|
||||
u8 uma2;
|
||||
u8 uc4;
|
||||
u8 uc5;
|
||||
u8 ued;
|
||||
u8 umodem;
|
||||
u8 uir;
|
||||
u8 reserved;
|
||||
u8 upfifo;
|
||||
u8 ucfifo;
|
||||
u8 usfifo;
|
||||
u8 utwfifo;
|
||||
u8 utcfifo;
|
||||
u8 urwfifo;
|
||||
u8 urcfifo;
|
||||
u8 rsvd[28];
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_IMX_REGS_H__ */
|
||||
52
u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h
Normal file
52
u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h
Normal file
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_LS102XA_DEVDIS_H_
|
||||
#define __FSL_LS102XA_DEVDIS_H_
|
||||
|
||||
#include <fsl_devdis.h>
|
||||
|
||||
const struct devdis_table devdis_tbl[] = {
|
||||
{ "pbl", 0x0, 0x80000000 }, /* PBL */
|
||||
{ "esdhc", 0x0, 0x20000000 }, /* eSDHC */
|
||||
{ "qdma", 0x0, 0x800000 }, /* qDMA */
|
||||
{ "edma", 0x0, 0x400000 }, /* eDMA */
|
||||
{ "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/
|
||||
{ "usb2", 0x0, 0x40000 }, /* USB2.0 controller */
|
||||
{ "sata", 0x0, 0x8000 }, /* SATA */
|
||||
{ "sec", 0x0, 0x200 }, /* SEC */
|
||||
{ "dcu", 0x0, 0x2 }, /* Display controller Unit */
|
||||
{ "qe", 0x0, 0x1 }, /* QUICC Engine */
|
||||
{ "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */
|
||||
{ "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */
|
||||
{ "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */
|
||||
{ "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */
|
||||
{ "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */
|
||||
{ "duart1", 0x3, 0x20000000 }, /* DUART1 */
|
||||
{ "duart2", 0x3, 0x10000000 }, /* DUART2 */
|
||||
{ "qspi", 0x3, 0x8000000 }, /* QSPI */
|
||||
{ "ddr", 0x4, 0x80000000 }, /* DDR */
|
||||
{ "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */
|
||||
{ "ifc", 0x4, 0x800000 }, /* IFC */
|
||||
{ "gpio", 0x4, 0x400000 }, /* GPIO */
|
||||
{ "dbg", 0x4, 0x200000 }, /* DBG */
|
||||
{ "can1", 0x4, 0x80000 }, /* FlexCAN1 */
|
||||
{ "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */
|
||||
{ "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */
|
||||
{ "secmon", 0x4, 0x4000 }, /* Security Monitor */
|
||||
{ "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */
|
||||
{ "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */
|
||||
{ "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */
|
||||
{ "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */
|
||||
{ "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */
|
||||
{ "asrc", 0x4, 0x20 }, /* ASRC */
|
||||
{ "spdif", 0x4, 0x10 }, /* SPDIF */
|
||||
{ "i2c1", 0x4, 0x4 }, /* I2C1 */
|
||||
{ "lpuart1", 0x4, 0x2 }, /* LPUART1 */
|
||||
{ "ftm1", 0x4, 0x1 }, /* FlexTimer1 */
|
||||
};
|
||||
|
||||
#endif
|
||||
11
u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
Normal file
11
u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
Normal file
@@ -0,0 +1,11 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SATA_H_
|
||||
#define __FSL_SATA_H_
|
||||
|
||||
int ls1021a_sata_init(void);
|
||||
#endif
|
||||
14
u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
Normal file
14
u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
Normal file
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_LS102XA_SOC_H
|
||||
#define __FSL_LS102XA_SOC_H
|
||||
|
||||
unsigned int get_soc_major_rev(void);
|
||||
int arch_soc_init(void);
|
||||
int ls102xa_smmu_stream_id_init(void);
|
||||
|
||||
#endif /* __FSL_LS102XA_SOC_H */
|
||||
74
u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
Normal file
74
u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
Normal file
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_LS102XA_STREAM_ID_H_
|
||||
#define __FSL_LS102XA_STREAM_ID_H_
|
||||
|
||||
#include <fsl_sec.h>
|
||||
|
||||
#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
|
||||
{ .compat = name, \
|
||||
.id = { idA }, .num_ids = 1, \
|
||||
.reg_offset = off + CONFIG_SYS_IMMR, \
|
||||
.compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
|
||||
}
|
||||
|
||||
#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
|
||||
{ .compat = name, \
|
||||
.id = { idA, idB }, .num_ids = 2, \
|
||||
.reg_offset = off + CONFIG_SYS_IMMR, \
|
||||
.compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
|
||||
}
|
||||
|
||||
/*
|
||||
* handle both old and new versioned SEC properties:
|
||||
* "fsl,secX.Y" became "fsl,sec-vX.Y" during development
|
||||
*/
|
||||
#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
|
||||
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
|
||||
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
|
||||
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
|
||||
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
|
||||
|
||||
/* This is a bit evil since we treat rtic param as both a string & hex value */
|
||||
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
|
||||
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
|
||||
liodnA, \
|
||||
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
|
||||
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
|
||||
liodnA, \
|
||||
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
|
||||
|
||||
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
|
||||
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
|
||||
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, 0)
|
||||
|
||||
struct liodn_id_table {
|
||||
const char *compat;
|
||||
u32 id[2];
|
||||
u8 num_ids;
|
||||
phys_addr_t compat_offset;
|
||||
unsigned long reg_offset;
|
||||
};
|
||||
|
||||
struct smmu_stream_id {
|
||||
uint16_t offset;
|
||||
uint16_t stream_id;
|
||||
char dev_name[32];
|
||||
};
|
||||
|
||||
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
|
||||
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
|
||||
#endif
|
||||
179
u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h
Normal file
179
u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h
Normal file
@@ -0,0 +1,179 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_NS_ACCESS_H_
|
||||
#define __FSL_NS_ACCESS_H_
|
||||
|
||||
enum csu_cslx_ind {
|
||||
CSU_CSLX_PCIE2_IO = 0,
|
||||
CSU_CSLX_PCIE1_IO,
|
||||
CSU_CSLX_MG2TPR_IP,
|
||||
CSU_CSLX_IFC_MEM,
|
||||
CSU_CSLX_OCRAM,
|
||||
CSU_CSLX_GIC,
|
||||
CSU_CSLX_PCIE1,
|
||||
CSU_CSLX_OCRAM2,
|
||||
CSU_CSLX_QSPI_MEM,
|
||||
CSU_CSLX_PCIE2,
|
||||
CSU_CSLX_SATA,
|
||||
CSU_CSLX_USB3,
|
||||
CSU_CSLX_SERDES = 32,
|
||||
CSU_CSLX_QDMA,
|
||||
CSU_CSLX_LPUART2,
|
||||
CSU_CSLX_LPUART1,
|
||||
CSU_CSLX_LPUART4,
|
||||
CSU_CSLX_LPUART3,
|
||||
CSU_CSLX_LPUART6,
|
||||
CSU_CSLX_LPUART5,
|
||||
CSU_CSLX_DSPI2 = 40,
|
||||
CSU_CSLX_DSPI1,
|
||||
CSU_CSLX_QSPI,
|
||||
CSU_CSLX_ESDHC,
|
||||
CSU_CSLX_2D_ACE,
|
||||
CSU_CSLX_IFC,
|
||||
CSU_CSLX_I2C1,
|
||||
CSU_CSLX_USB2,
|
||||
CSU_CSLX_I2C3,
|
||||
CSU_CSLX_I2C2,
|
||||
CSU_CSLX_DUART2 = 50,
|
||||
CSU_CSLX_DUART1,
|
||||
CSU_CSLX_WDT2,
|
||||
CSU_CSLX_WDT1,
|
||||
CSU_CSLX_EDMA,
|
||||
CSU_CSLX_SYS_CNT,
|
||||
CSU_CSLX_DMA_MUX2,
|
||||
CSU_CSLX_DMA_MUX1,
|
||||
CSU_CSLX_DDR,
|
||||
CSU_CSLX_QUICC,
|
||||
CSU_CSLX_DCFG_CCU_RCPM = 60,
|
||||
CSU_CSLX_SECURE_BOOTROM,
|
||||
CSU_CSLX_SFP,
|
||||
CSU_CSLX_TMU,
|
||||
CSU_CSLX_SECURE_MONITOR,
|
||||
CSU_CSLX_RESERVED0,
|
||||
CSU_CSLX_ETSEC1,
|
||||
CSU_CSLX_SEC5_5,
|
||||
CSU_CSLX_ETSEC3,
|
||||
CSU_CSLX_ETSEC2,
|
||||
CSU_CSLX_GPIO2 = 70,
|
||||
CSU_CSLX_GPIO1,
|
||||
CSU_CSLX_GPIO4,
|
||||
CSU_CSLX_GPIO3,
|
||||
CSU_CSLX_PLATFORM_CONT,
|
||||
CSU_CSLX_CSU,
|
||||
CSU_CSLX_ASRC,
|
||||
CSU_CSLX_SPDIF,
|
||||
CSU_CSLX_FLEXCAN2,
|
||||
CSU_CSLX_FLEXCAN1,
|
||||
CSU_CSLX_FLEXCAN4 = 80,
|
||||
CSU_CSLX_FLEXCAN3,
|
||||
CSU_CSLX_SAI2,
|
||||
CSU_CSLX_SAI1,
|
||||
CSU_CSLX_SAI4,
|
||||
CSU_CSLX_SAI3,
|
||||
CSU_CSLX_FTM2,
|
||||
CSU_CSLX_FTM1,
|
||||
CSU_CSLX_FTM4,
|
||||
CSU_CSLX_FTM3,
|
||||
CSU_CSLX_FTM6 = 90,
|
||||
CSU_CSLX_FTM5,
|
||||
CSU_CSLX_FTM8,
|
||||
CSU_CSLX_FTM7,
|
||||
CSU_CSLX_EPU,
|
||||
CSU_CSLX_COP_DCSR,
|
||||
CSU_CSLX_DDI,
|
||||
CSU_CSLX_GDI,
|
||||
CSU_CSLX_RESERVED1,
|
||||
CSU_CSLX_USB3_PHY = 116,
|
||||
CSU_CSLX_RESERVED2,
|
||||
CSU_CSLX_MAX,
|
||||
};
|
||||
|
||||
static struct csu_ns_dev ns_dev[] = {
|
||||
{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
|
||||
{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
|
||||
{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_OCRAM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GIC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PCIE1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PCIE2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SATA, CSU_ALL_RW },
|
||||
{ CSU_CSLX_USB3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SERDES, CSU_ALL_RW },
|
||||
{ CSU_CSLX_QDMA, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART6, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART5, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DSPI2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DSPI1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_QSPI, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ESDHC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
|
||||
{ CSU_CSLX_IFC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_I2C1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_USB2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_I2C3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_I2C2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DUART2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DUART1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_WDT2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_WDT1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_EDMA, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DDR, CSU_ALL_RW },
|
||||
{ CSU_CSLX_QUICC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SFP, CSU_ALL_RW },
|
||||
{ CSU_CSLX_TMU, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
|
||||
{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GPIO2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GPIO1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GPIO4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GPIO3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
|
||||
{ CSU_CSLX_CSU, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ASRC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SPDIF, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM6, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM5, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM8, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM7, CSU_ALL_RW },
|
||||
{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
|
||||
{ CSU_CSLX_EPU, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GDI, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DDI, CSU_ALL_RW },
|
||||
{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
|
||||
{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
|
||||
};
|
||||
|
||||
#endif
|
||||
20
u-boot/arch/arm/include/asm/arch-ls102xa/spl.h
Normal file
20
u-boot/arch/arm/include/asm/arch-ls102xa/spl.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SPL_H__
|
||||
#define __ASM_ARCH_SPL_H__
|
||||
|
||||
#define BOOT_DEVICE_NONE 0
|
||||
#define BOOT_DEVICE_XIP 1
|
||||
#define BOOT_DEVICE_XIPWAIT 2
|
||||
#define BOOT_DEVICE_NAND 3
|
||||
#define BOOT_DEVICE_ONENAND 4
|
||||
#define BOOT_DEVICE_MMC1 5
|
||||
#define BOOT_DEVICE_MMC2 6
|
||||
#define BOOT_DEVICE_MMC2_2 7
|
||||
#define BOOT_DEVICE_SPI 10
|
||||
|
||||
#endif /* __ASM_ARCH_SPL_H__ */
|
||||
52
u-boot/arch/arm/include/asm/arch-meson/gxbb.h
Normal file
52
u-boot/arch/arm/include/asm/arch-meson/gxbb.h
Normal file
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __GXBB_H__
|
||||
#define __GXBB_H__
|
||||
|
||||
#define GXBB_PERIPHS_BASE 0xc8834400
|
||||
#define GXBB_HIU_BASE 0xc883c000
|
||||
#define GXBB_ETH_BASE 0xc9410000
|
||||
|
||||
/* Peripherals registers */
|
||||
#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
|
||||
|
||||
/* GPIO registers 0 to 6 */
|
||||
#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
|
||||
#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
|
||||
#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
|
||||
#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
|
||||
|
||||
/* Pinmux registers 0 to 12 */
|
||||
#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n))
|
||||
|
||||
#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
|
||||
#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
|
||||
|
||||
#define GXBB_ETH_REG_0_PHY_INTF BIT(0)
|
||||
#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
|
||||
#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
|
||||
#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10)
|
||||
#define GXBB_ETH_REG_0_CLK_EN BIT(12)
|
||||
|
||||
/* HIU registers */
|
||||
#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2))
|
||||
|
||||
#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)
|
||||
|
||||
/* Ethernet memory power domain */
|
||||
#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
|
||||
|
||||
/* Clock gates */
|
||||
#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50)
|
||||
#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51)
|
||||
#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52)
|
||||
#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
|
||||
#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
|
||||
|
||||
#define GXBB_GCLK_MPEG_1_ETH BIT(3)
|
||||
|
||||
#endif /* __GXBB_H__ */
|
||||
12
u-boot/arch/arm/include/asm/arch-meson/sm.h
Normal file
12
u-boot/arch/arm/include/asm/arch-meson/sm.h
Normal file
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MESON_SM_H__
|
||||
#define __MESON_SM_H__
|
||||
|
||||
ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
|
||||
|
||||
#endif /* __MESON_SM_H__ */
|
||||
62
u-boot/arch/arm/include/asm/arch-mvebu/spi.h
Normal file
62
u-boot/arch/arm/include/asm/arch-mvebu/spi.h
Normal file
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*
|
||||
* Derived from drivers/spi/mpc8xxx_spi.c
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __KW_SPI_H__
|
||||
#define __KW_SPI_H__
|
||||
|
||||
/* SPI Registers on kirkwood SOC */
|
||||
struct kwspi_registers {
|
||||
u32 ctrl; /* 0x10600 */
|
||||
u32 cfg; /* 0x10604 */
|
||||
u32 dout; /* 0x10608 */
|
||||
u32 din; /* 0x1060c */
|
||||
u32 irq_cause; /* 0x10610 */
|
||||
u32 irq_mask; /* 0x10614 */
|
||||
u32 timing1; /* 0x10618 */
|
||||
u32 timing2; /* 0x1061c */
|
||||
u32 dw_cfg; /* 0x10620 - Direct Write Configuration */
|
||||
};
|
||||
|
||||
/* They are used to define CONFIG_SYS_KW_SPI_MPP
|
||||
* each of the below #defines selects which mpp is
|
||||
* configured for each SPI signal in spi_claim_bus
|
||||
* bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1)
|
||||
* bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1)
|
||||
* bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1)
|
||||
*/
|
||||
#define MOSI_MPP6 (1 << 0)
|
||||
#define SCK_MPP10 (1 << 1)
|
||||
#define MISO_MPP11 (1 << 2)
|
||||
|
||||
/* Control Register */
|
||||
#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */
|
||||
#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */
|
||||
#define KWSPI_CS_SHIFT 2 /* chip select shift */
|
||||
#define KWSPI_CS_MASK 0x7 /* chip select mask */
|
||||
|
||||
/* Configuration Register */
|
||||
#define KWSPI_CLKPRESCL_MASK 0x1f
|
||||
#define KWSPI_CLKPRESCL_MIN 0x12
|
||||
#define KWSPI_XFERLEN_1BYTE 0
|
||||
#define KWSPI_XFERLEN_2BYTE (1 << 5)
|
||||
#define KWSPI_XFERLEN_MASK (1 << 5)
|
||||
#define KWSPI_ADRLEN_1BYTE 0
|
||||
#define KWSPI_ADRLEN_2BYTE (1 << 8)
|
||||
#define KWSPI_ADRLEN_3BYTE (2 << 8)
|
||||
#define KWSPI_ADRLEN_4BYTE (3 << 8)
|
||||
#define KWSPI_ADRLEN_MASK (3 << 8)
|
||||
|
||||
#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
|
||||
#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
|
||||
#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
|
||||
|
||||
#define KWSPI_TIMEOUT 10000
|
||||
|
||||
#endif /* __KW_SPI_H__ */
|
||||
59
u-boot/arch/arm/include/asm/arch-mx25/clock.h
Normal file
59
u-boot/arch/arm/include/asm/arch-mx25/clock.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
*
|
||||
* (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
|
||||
*
|
||||
* Modified for mx25 by John Rigby <jrigby@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_MX25_HCLK_FREQ
|
||||
#define MXC_HCLK CONFIG_MX25_HCLK_FREQ
|
||||
#else
|
||||
#define MXC_HCLK 24000000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MX25_CLK32
|
||||
#define MXC_CLK32 CONFIG_MX25_CLK32
|
||||
#else
|
||||
#define MXC_CLK32 32768
|
||||
#endif
|
||||
|
||||
enum mxc_clock {
|
||||
/* PER clocks (do not change order) */
|
||||
MXC_CSI_CLK,
|
||||
MXC_EPIT_CLK,
|
||||
MXC_ESAI_CLK,
|
||||
MXC_ESDHC1_CLK,
|
||||
MXC_ESDHC2_CLK,
|
||||
MXC_GPT_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_LCDC_CLK,
|
||||
MXC_NFC_CLK,
|
||||
MXC_OWIRE_CLK,
|
||||
MXC_PWM_CLK,
|
||||
MXC_SIM1_CLK,
|
||||
MXC_SIM2_CLK,
|
||||
MXC_SSI1_CLK,
|
||||
MXC_SSI2_CLK,
|
||||
MXC_UART_CLK,
|
||||
/* Other clocks */
|
||||
MXC_ARM_CLK,
|
||||
MXC_AHB_CLK,
|
||||
MXC_IPG_CLK,
|
||||
MXC_CSPI_CLK,
|
||||
MXC_FEC_CLK,
|
||||
MXC_CLK_NUM
|
||||
};
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
|
||||
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
14
u-boot/arch/arm/include/asm/arch-mx25/gpio.h
Normal file
14
u-boot/arch/arm/include/asm/arch-mx25/gpio.h
Normal file
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright (C) 2011
|
||||
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ASM_ARCH_MX25_GPIO_H
|
||||
#define __ASM_ARCH_MX25_GPIO_H
|
||||
|
||||
#include <asm/imx-common/gpio.h>
|
||||
|
||||
#endif
|
||||
529
u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h
Normal file
529
u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h
Normal file
@@ -0,0 +1,529 @@
|
||||
/*
|
||||
* Copyright (C) 2009, DENX Software Engineering
|
||||
* Author: John Rigby <jcrigby@gmail.com
|
||||
*
|
||||
* Based on arch-mx31/imx-regs.h
|
||||
* Copyright (C) 2009 Ilya Yanok,
|
||||
* Emcraft Systems <yanok@emcraft.com>
|
||||
* and arch-mx27/imx-regs.h
|
||||
* Copyright (C) 2007 Pengutronix,
|
||||
* Sascha Hauer <s.hauer@pengutronix.de>
|
||||
* Copyright (C) 2009 Ilya Yanok,
|
||||
* Emcraft Systems <yanok@emcraft.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _IMX_REGS_H
|
||||
#define _IMX_REGS_H
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
|
||||
/* Clock Control Module (CCM) registers */
|
||||
struct ccm_regs {
|
||||
u32 mpctl; /* Core PLL Control */
|
||||
u32 upctl; /* USB PLL Control */
|
||||
u32 cctl; /* Clock Control */
|
||||
u32 cgr0; /* Clock Gating Control 0 */
|
||||
u32 cgr1; /* Clock Gating Control 1 */
|
||||
u32 cgr2; /* Clock Gating Control 2 */
|
||||
u32 pcdr[4]; /* PER Clock Dividers */
|
||||
u32 rcsr; /* CCM Status */
|
||||
u32 crdr; /* CCM Reset and Debug */
|
||||
u32 dcvr0; /* DPTC Comparator Value 0 */
|
||||
u32 dcvr1; /* DPTC Comparator Value 1 */
|
||||
u32 dcvr2; /* DPTC Comparator Value 2 */
|
||||
u32 dcvr3; /* DPTC Comparator Value 3 */
|
||||
u32 ltr0; /* Load Tracking 0 */
|
||||
u32 ltr1; /* Load Tracking 1 */
|
||||
u32 ltr2; /* Load Tracking 2 */
|
||||
u32 ltr3; /* Load Tracking 3 */
|
||||
u32 ltbr0; /* Load Tracking Buffer 0 */
|
||||
u32 ltbr1; /* Load Tracking Buffer 1 */
|
||||
u32 pcmr0; /* Power Management Control 0 */
|
||||
u32 pcmr1; /* Power Management Control 1 */
|
||||
u32 pcmr2; /* Power Management Control 2 */
|
||||
u32 mcr; /* Miscellaneous Control */
|
||||
u32 lpimr0; /* Low Power Interrupt Mask 0 */
|
||||
u32 lpimr1; /* Low Power Interrupt Mask 1 */
|
||||
};
|
||||
|
||||
/* Enhanced SDRAM Controller (ESDRAMC) registers */
|
||||
struct esdramc_regs {
|
||||
u32 ctl0; /* control 0 */
|
||||
u32 cfg0; /* configuration 0 */
|
||||
u32 ctl1; /* control 1 */
|
||||
u32 cfg1; /* configuration 1 */
|
||||
u32 misc; /* miscellaneous */
|
||||
u32 pad[3];
|
||||
u32 cdly1; /* Delay Line 1 configuration debug */
|
||||
u32 cdly2; /* delay line 2 configuration debug */
|
||||
u32 cdly3; /* delay line 3 configuration debug */
|
||||
u32 cdly4; /* delay line 4 configuration debug */
|
||||
u32 cdly5; /* delay line 5 configuration debug */
|
||||
u32 cdlyl; /* delay line cycle length debug */
|
||||
};
|
||||
|
||||
/* General Purpose Timer (GPT) registers */
|
||||
struct gpt_regs {
|
||||
u32 ctrl; /* control */
|
||||
u32 pre; /* prescaler */
|
||||
u32 stat; /* status */
|
||||
u32 intr; /* interrupt */
|
||||
u32 cmp[3]; /* output compare 1-3 */
|
||||
u32 capt[2]; /* input capture 1-2 */
|
||||
u32 counter; /* counter */
|
||||
};
|
||||
|
||||
/* Watchdog Timer (WDOG) registers */
|
||||
struct wdog_regs {
|
||||
u16 wcr; /* Control */
|
||||
u16 wsr; /* Service */
|
||||
u16 wrsr; /* Reset Status */
|
||||
u16 wicr; /* Interrupt Control */
|
||||
u16 wmcr; /* Misc Control */
|
||||
};
|
||||
|
||||
/* IIM control registers */
|
||||
struct iim_regs {
|
||||
u32 iim_stat;
|
||||
u32 iim_statm;
|
||||
u32 iim_err;
|
||||
u32 iim_emask;
|
||||
u32 iim_fctl;
|
||||
u32 iim_ua;
|
||||
u32 iim_la;
|
||||
u32 iim_sdat;
|
||||
u32 iim_prev;
|
||||
u32 iim_srev;
|
||||
u32 iim_prg_p;
|
||||
u32 iim_scs0;
|
||||
u32 iim_scs1;
|
||||
u32 iim_scs2;
|
||||
u32 iim_scs3;
|
||||
u32 res1[0x1f1];
|
||||
struct fuse_bank {
|
||||
u32 fuse_regs[0x20];
|
||||
u32 fuse_rsvd[0xe0];
|
||||
} bank[3];
|
||||
};
|
||||
|
||||
struct fuse_bank0_regs {
|
||||
u32 fuse0_7[8];
|
||||
u32 uid[8];
|
||||
u32 fuse16_25[0xa];
|
||||
u32 mac_addr[6];
|
||||
};
|
||||
|
||||
struct fuse_bank1_regs {
|
||||
u32 fuse0_21[0x16];
|
||||
u32 usr5;
|
||||
u32 fuse23_29[7];
|
||||
u32 usr6[2];
|
||||
};
|
||||
|
||||
/* Multi-Layer AHB Crossbar Switch (MAX) registers */
|
||||
struct max_regs {
|
||||
u32 mpr0;
|
||||
u32 pad00[3];
|
||||
u32 sgpcr0;
|
||||
u32 pad01[59];
|
||||
u32 mpr1;
|
||||
u32 pad02[3];
|
||||
u32 sgpcr1;
|
||||
u32 pad03[59];
|
||||
u32 mpr2;
|
||||
u32 pad04[3];
|
||||
u32 sgpcr2;
|
||||
u32 pad05[59];
|
||||
u32 mpr3;
|
||||
u32 pad06[3];
|
||||
u32 sgpcr3;
|
||||
u32 pad07[59];
|
||||
u32 mpr4;
|
||||
u32 pad08[3];
|
||||
u32 sgpcr4;
|
||||
u32 pad09[251];
|
||||
u32 mgpcr0;
|
||||
u32 pad10[63];
|
||||
u32 mgpcr1;
|
||||
u32 pad11[63];
|
||||
u32 mgpcr2;
|
||||
u32 pad12[63];
|
||||
u32 mgpcr3;
|
||||
u32 pad13[63];
|
||||
u32 mgpcr4;
|
||||
};
|
||||
|
||||
/* AHB <-> IP-Bus Interface (AIPS) */
|
||||
struct aips_regs {
|
||||
u32 mpr_0_7;
|
||||
u32 mpr_8_15;
|
||||
};
|
||||
/* LCD controller registers */
|
||||
struct lcdc_regs {
|
||||
u32 lssar; /* Screen Start Address */
|
||||
u32 lsr; /* Size */
|
||||
u32 lvpwr; /* Virtual Page Width */
|
||||
u32 lcpr; /* Cursor Position */
|
||||
u32 lcwhb; /* Cursor Width Height and Blink */
|
||||
u32 lccmr; /* Color Cursor Mapping */
|
||||
u32 lpcr; /* Panel Configuration */
|
||||
u32 lhcr; /* Horizontal Configuration */
|
||||
u32 lvcr; /* Vertical Configuration */
|
||||
u32 lpor; /* Panning Offset */
|
||||
u32 lscr; /* Sharp Configuration */
|
||||
u32 lpccr; /* PWM Contrast Control */
|
||||
u32 ldcr; /* DMA Control */
|
||||
u32 lrmcr; /* Refresh Mode Control */
|
||||
u32 licr; /* Interrupt Configuration */
|
||||
u32 lier; /* Interrupt Enable */
|
||||
u32 lisr; /* Interrupt Status */
|
||||
u32 res0[3];
|
||||
u32 lgwsar; /* Graphic Window Start Address */
|
||||
u32 lgwsr; /* Graphic Window Size */
|
||||
u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */
|
||||
u32 lgwpor; /* Graphic Window Panning Offset */
|
||||
u32 lgwpr; /* Graphic Window Position */
|
||||
u32 lgwcr; /* Graphic Window Control */
|
||||
u32 lgwdcr; /* Graphic Window DMA Control */
|
||||
u32 res1[5];
|
||||
u32 lauscr; /* AUS Mode Control */
|
||||
u32 lausccr; /* AUS mode Cursor Control */
|
||||
u32 res2[31 + 64*7];
|
||||
u32 bglut; /* Background Lookup Table */
|
||||
u32 gwlut; /* Graphic Window Lookup Table */
|
||||
};
|
||||
|
||||
/* Wireless External Interface Module Registers */
|
||||
struct weim_regs {
|
||||
u32 cscr0u; /* Chip Select 0 Upper Register */
|
||||
u32 cscr0l; /* Chip Select 0 Lower Register */
|
||||
u32 cscr0a; /* Chip Select 0 Addition Register */
|
||||
u32 pad0;
|
||||
u32 cscr1u; /* Chip Select 1 Upper Register */
|
||||
u32 cscr1l; /* Chip Select 1 Lower Register */
|
||||
u32 cscr1a; /* Chip Select 1 Addition Register */
|
||||
u32 pad1;
|
||||
u32 cscr2u; /* Chip Select 2 Upper Register */
|
||||
u32 cscr2l; /* Chip Select 2 Lower Register */
|
||||
u32 cscr2a; /* Chip Select 2 Addition Register */
|
||||
u32 pad2;
|
||||
u32 cscr3u; /* Chip Select 3 Upper Register */
|
||||
u32 cscr3l; /* Chip Select 3 Lower Register */
|
||||
u32 cscr3a; /* Chip Select 3 Addition Register */
|
||||
u32 pad3;
|
||||
u32 cscr4u; /* Chip Select 4 Upper Register */
|
||||
u32 cscr4l; /* Chip Select 4 Lower Register */
|
||||
u32 cscr4a; /* Chip Select 4 Addition Register */
|
||||
u32 pad4;
|
||||
u32 cscr5u; /* Chip Select 5 Upper Register */
|
||||
u32 cscr5l; /* Chip Select 5 Lower Register */
|
||||
u32 cscr5a; /* Chip Select 5 Addition Register */
|
||||
u32 pad5;
|
||||
u32 wcr; /* WEIM Configuration Register */
|
||||
};
|
||||
|
||||
/* Multi-Master Memory Interface */
|
||||
struct m3if_regs {
|
||||
u32 ctl; /* Control Register */
|
||||
u32 wcfg0; /* Watermark Configuration Register 0 */
|
||||
u32 wcfg1; /* Watermark Configuration Register1 */
|
||||
u32 wcfg2; /* Watermark Configuration Register2 */
|
||||
u32 wcfg3; /* Watermark Configuration Register 3 */
|
||||
u32 wcfg4; /* Watermark Configuration Register 4 */
|
||||
u32 wcfg5; /* Watermark Configuration Register 5 */
|
||||
u32 wcfg6; /* Watermark Configuration Register 6 */
|
||||
u32 wcfg7; /* Watermark Configuration Register 7 */
|
||||
u32 wcsr; /* Watermark Control and Status Register */
|
||||
u32 scfg0; /* Snooping Configuration Register 0 */
|
||||
u32 scfg1; /* Snooping Configuration Register 1 */
|
||||
u32 scfg2; /* Snooping Configuration Register 2 */
|
||||
u32 ssr0; /* Snooping Status Register 0 */
|
||||
u32 ssr1; /* Snooping Status Register 1 */
|
||||
u32 res0;
|
||||
u32 mlwe0; /* Master Lock WEIM CS0 Register */
|
||||
u32 mlwe1; /* Master Lock WEIM CS1 Register */
|
||||
u32 mlwe2; /* Master Lock WEIM CS2 Register */
|
||||
u32 mlwe3; /* Master Lock WEIM CS3 Register */
|
||||
u32 mlwe4; /* Master Lock WEIM CS4 Register */
|
||||
u32 mlwe5; /* Master Lock WEIM CS5 Register */
|
||||
};
|
||||
|
||||
/* Pulse width modulation */
|
||||
struct pwm_regs {
|
||||
u32 cr; /* Control Register */
|
||||
u32 sr; /* Status Register */
|
||||
u32 ir; /* Interrupt Register */
|
||||
u32 sar; /* Sample Register */
|
||||
u32 pr; /* Period Register */
|
||||
u32 cnr; /* Counter Register */
|
||||
};
|
||||
|
||||
/* Enhanced Periodic Interrupt Timer */
|
||||
struct epit_regs {
|
||||
u32 cr; /* Control register */
|
||||
u32 sr; /* Status register */
|
||||
u32 lr; /* Load register */
|
||||
u32 cmpr; /* Compare register */
|
||||
u32 cnr; /* Counter register */
|
||||
};
|
||||
|
||||
/* CSPI registers */
|
||||
struct cspi_regs {
|
||||
u32 rxdata;
|
||||
u32 txdata;
|
||||
u32 ctrl;
|
||||
u32 intr;
|
||||
u32 dma;
|
||||
u32 stat;
|
||||
u32 period;
|
||||
u32 test;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#define ARCH_MXC
|
||||
|
||||
/* AIPS 1 */
|
||||
#define IMX_AIPS1_BASE (0x43F00000)
|
||||
#define IMX_MAX_BASE (0x43F04000)
|
||||
#define IMX_CLKCTL_BASE (0x43F08000)
|
||||
#define IMX_ETB_SLOT4_BASE (0x43F0C000)
|
||||
#define IMX_ETB_SLOT5_BASE (0x43F10000)
|
||||
#define IMX_ECT_CTIO_BASE (0x43F18000)
|
||||
#define I2C1_BASE_ADDR (0x43F80000)
|
||||
#define I2C3_BASE_ADDR (0x43F84000)
|
||||
#define IMX_CAN1_BASE (0x43F88000)
|
||||
#define IMX_CAN2_BASE (0x43F8C000)
|
||||
#define UART1_BASE (0x43F90000)
|
||||
#define UART2_BASE (0x43F94000)
|
||||
#define I2C2_BASE_ADDR (0x43F98000)
|
||||
#define IMX_OWIRE_BASE (0x43F9C000)
|
||||
#define IMX_CSPI1_BASE (0x43FA4000)
|
||||
#define IMX_KPP_BASE (0x43FA8000)
|
||||
#define IMX_IOPADMUX_BASE (0x43FAC000)
|
||||
#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE
|
||||
#define IMX_IOPADCTL_BASE (0x43FAC22C)
|
||||
#define IMX_IOPADGRPCTL_BASE (0x43FAC418)
|
||||
#define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
|
||||
#define IMX_AUDMUX_BASE (0x43FB0000)
|
||||
#define IMX_ECT_IP1_BASE (0x43FB8000)
|
||||
#define IMX_ECT_IP2_BASE (0x43FBC000)
|
||||
|
||||
/* SPBA */
|
||||
#define IMX_SPBA_BASE (0x50000000)
|
||||
#define IMX_CSPI3_BASE (0x50004000)
|
||||
#define UART4_BASE (0x50008000)
|
||||
#define UART3_BASE (0x5000C000)
|
||||
#define IMX_CSPI2_BASE (0x50010000)
|
||||
#define IMX_SSI2_BASE (0x50014000)
|
||||
#define IMX_ESAI_BASE (0x50018000)
|
||||
#define IMX_ATA_DMA_BASE (0x50020000)
|
||||
#define IMX_SIM1_BASE (0x50024000)
|
||||
#define IMX_SIM2_BASE (0x50028000)
|
||||
#define UART5_BASE (0x5002C000)
|
||||
#define IMX_TSC_BASE (0x50030000)
|
||||
#define IMX_SSI1_BASE (0x50034000)
|
||||
#define IMX_FEC_BASE (0x50038000)
|
||||
#define IMX_SPBA_CTRL_BASE (0x5003C000)
|
||||
|
||||
/* AIPS 2 */
|
||||
#define IMX_AIPS2_BASE (0x53F00000)
|
||||
#define IMX_CCM_BASE (0x53F80000)
|
||||
#define IMX_GPT4_BASE (0x53F84000)
|
||||
#define IMX_GPT3_BASE (0x53F88000)
|
||||
#define IMX_GPT2_BASE (0x53F8C000)
|
||||
#define IMX_GPT1_BASE (0x53F90000)
|
||||
#define IMX_EPIT1_BASE (0x53F94000)
|
||||
#define IMX_EPIT2_BASE (0x53F98000)
|
||||
#define IMX_GPIO4_BASE (0x53F9C000)
|
||||
#define IMX_PWM2_BASE (0x53FA0000)
|
||||
#define IMX_GPIO3_BASE (0x53FA4000)
|
||||
#define IMX_PWM3_BASE (0x53FA8000)
|
||||
#define IMX_SCC_BASE (0x53FAC000)
|
||||
#define IMX_SCM_BASE (0x53FAE000)
|
||||
#define IMX_SMN_BASE (0x53FAF000)
|
||||
#define IMX_RNGD_BASE (0x53FB0000)
|
||||
#define IMX_MMC_SDHC1_BASE (0x53FB4000)
|
||||
#define IMX_MMC_SDHC2_BASE (0x53FB8000)
|
||||
#define IMX_LCDC_BASE (0x53FBC000)
|
||||
#define IMX_SLCDC_BASE (0x53FC0000)
|
||||
#define IMX_PWM4_BASE (0x53FC8000)
|
||||
#define IMX_GPIO1_BASE (0x53FCC000)
|
||||
#define IMX_GPIO2_BASE (0x53FD0000)
|
||||
#define IMX_SDMA_BASE (0x53FD4000)
|
||||
#define IMX_WDT_BASE (0x53FDC000)
|
||||
#define IMX_PWM1_BASE (0x53FE0000)
|
||||
#define IMX_RTIC_BASE (0x53FEC000)
|
||||
#define IMX_IIM_BASE (0x53FF0000)
|
||||
#define IIM_BASE_ADDR IMX_IIM_BASE
|
||||
#define IMX_USB_BASE (0x53FF4000)
|
||||
#define IMX_USB_PORT_OFFSET 0x200
|
||||
#define IMX_CSI_BASE (0x53FF8000)
|
||||
#define IMX_DRYICE_BASE (0x53FFC000)
|
||||
|
||||
#define IMX_ARM926_ROMPATCH (0x60000000)
|
||||
#define IMX_ARM926_ASIC (0x68000000)
|
||||
|
||||
/* 128K Internal Static RAM */
|
||||
#define IMX_RAM_BASE (0x78000000)
|
||||
#define IMX_RAM_SIZE (128 * 1024)
|
||||
|
||||
/* SDRAM BANKS */
|
||||
#define IMX_SDRAM_BANK0_BASE (0x80000000)
|
||||
#define IMX_SDRAM_BANK1_BASE (0x90000000)
|
||||
|
||||
#define IMX_WEIM_CS0 (0xA0000000)
|
||||
#define IMX_WEIM_CS1 (0xA8000000)
|
||||
#define IMX_WEIM_CS2 (0xB0000000)
|
||||
#define IMX_WEIM_CS3 (0xB2000000)
|
||||
#define IMX_WEIM_CS4 (0xB4000000)
|
||||
#define IMX_ESDRAMC_BASE (0xB8001000)
|
||||
#define IMX_WEIM_CTRL_BASE (0xB8002000)
|
||||
#define IMX_M3IF_CTRL_BASE (0xB8003000)
|
||||
#define IMX_EMI_CTRL_BASE (0xB8004000)
|
||||
|
||||
/* NAND Flash Controller */
|
||||
#define IMX_NFC_BASE (0xBB000000)
|
||||
#define NFC_BASE_ADDR IMX_NFC_BASE
|
||||
|
||||
/* CCM bitfields */
|
||||
#define CCM_PLL_MFI_SHIFT 10
|
||||
#define CCM_PLL_MFI_MASK 0xf
|
||||
#define CCM_PLL_MFN_SHIFT 0
|
||||
#define CCM_PLL_MFN_MASK 0x3ff
|
||||
#define CCM_PLL_MFD_SHIFT 16
|
||||
#define CCM_PLL_MFD_MASK 0x3ff
|
||||
#define CCM_PLL_PD_SHIFT 26
|
||||
#define CCM_PLL_PD_MASK 0xf
|
||||
#define CCM_CCTL_ARM_DIV_SHIFT 30
|
||||
#define CCM_CCTL_ARM_DIV_MASK 3
|
||||
#define CCM_CCTL_AHB_DIV_SHIFT 28
|
||||
#define CCM_CCTL_AHB_DIV_MASK 3
|
||||
#define CCM_CCTL_ARM_SRC (1 << 14)
|
||||
#define CCM_CGR1_GPT1 (1 << 19)
|
||||
#define CCM_PERCLK_REG(clk) (clk / 4)
|
||||
#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4))
|
||||
#define CCM_PERCLK_MASK 0x3f
|
||||
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
|
||||
#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
|
||||
#define CCM_CRDR_BT_UART_SRC_SHIFT 29
|
||||
#define CCM_CRDR_BT_UART_SRC_MASK 7
|
||||
|
||||
/* ESDRAM Controller register bitfields */
|
||||
#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
|
||||
#define ESDCTL_BL (1 << 7)
|
||||
#define ESDCTL_FP (1 << 8)
|
||||
#define ESDCTL_PWDT(x) (((x) & 3) << 10)
|
||||
#define ESDCTL_SREFR(x) (((x) & 7) << 13)
|
||||
#define ESDCTL_DSIZ_16_UPPER (0 << 16)
|
||||
#define ESDCTL_DSIZ_16_LOWER (1 << 16)
|
||||
#define ESDCTL_DSIZ_32 (2 << 16)
|
||||
#define ESDCTL_COL8 (0 << 20)
|
||||
#define ESDCTL_COL9 (1 << 20)
|
||||
#define ESDCTL_COL10 (2 << 20)
|
||||
#define ESDCTL_ROW11 (0 << 24)
|
||||
#define ESDCTL_ROW12 (1 << 24)
|
||||
#define ESDCTL_ROW13 (2 << 24)
|
||||
#define ESDCTL_ROW14 (3 << 24)
|
||||
#define ESDCTL_ROW15 (4 << 24)
|
||||
#define ESDCTL_SP (1 << 27)
|
||||
#define ESDCTL_SMODE_NORMAL (0 << 28)
|
||||
#define ESDCTL_SMODE_PRECHARGE (1 << 28)
|
||||
#define ESDCTL_SMODE_AUTO_REF (2 << 28)
|
||||
#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
|
||||
#define ESDCTL_SMODE_MAN_REF (4 << 28)
|
||||
#define ESDCTL_SDE (1 << 31)
|
||||
|
||||
#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
|
||||
#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
|
||||
#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
|
||||
#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
|
||||
#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
|
||||
#define ESDCFG_TWR (1 << 15)
|
||||
#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
|
||||
#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
|
||||
#define ESDCFG_TWTR (1 << 20)
|
||||
#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
|
||||
|
||||
#define ESDMISC_RST (1 << 1)
|
||||
#define ESDMISC_MDDREN (1 << 2)
|
||||
#define ESDMISC_MDDR_DL_RST (1 << 3)
|
||||
#define ESDMISC_MDDR_MDIS (1 << 4)
|
||||
#define ESDMISC_LHD (1 << 5)
|
||||
#define ESDMISC_MA10_SHARE (1 << 6)
|
||||
#define ESDMISC_SDRAM_RDY (1 << 31)
|
||||
|
||||
/* GPT bits */
|
||||
#define GPT_CTRL_SWR (1 << 15) /* Software reset */
|
||||
#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */
|
||||
#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */
|
||||
#define GPT_CTRL_TEN 1 /* Timer enable */
|
||||
|
||||
/* WDOG enable */
|
||||
#define WCR_WDE 0x04
|
||||
#define WSR_UNLOCK1 0x5555
|
||||
#define WSR_UNLOCK2 0xAAAA
|
||||
|
||||
/* MAX bits */
|
||||
#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0)
|
||||
|
||||
/* M3IF bits */
|
||||
#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0)
|
||||
|
||||
/* WEIM bits */
|
||||
/* 13 fields of the upper CS control register */
|
||||
#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
|
||||
cnc, wsc, ew, wws, edc) \
|
||||
((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
|
||||
(psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
|
||||
(cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
|
||||
/* 12 fields of the lower CS control register */
|
||||
#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
|
||||
csa, ebc, dsz, csn, psr, cre, wrap, csen) \
|
||||
((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
|
||||
(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
|
||||
(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
|
||||
/* 14 fields of the additional CS control register */
|
||||
#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
|
||||
wwu, age, cnc2, fce) \
|
||||
((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
|
||||
(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
|
||||
(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
|
||||
(age) << 2 | (cnc2) << 1 | (fce) << 0)
|
||||
|
||||
/* Names used in GPIO driver */
|
||||
#define GPIO1_BASE_ADDR IMX_GPIO1_BASE
|
||||
#define GPIO2_BASE_ADDR IMX_GPIO2_BASE
|
||||
#define GPIO3_BASE_ADDR IMX_GPIO3_BASE
|
||||
#define GPIO4_BASE_ADDR IMX_GPIO4_BASE
|
||||
|
||||
/*
|
||||
* CSPI register definitions
|
||||
*/
|
||||
#define MXC_CSPI
|
||||
#define MXC_CSPICTRL_EN (1 << 0)
|
||||
#define MXC_CSPICTRL_MODE (1 << 1)
|
||||
#define MXC_CSPICTRL_XCH (1 << 2)
|
||||
#define MXC_CSPICTRL_SMC (1 << 3)
|
||||
#define MXC_CSPICTRL_POL (1 << 4)
|
||||
#define MXC_CSPICTRL_PHA (1 << 5)
|
||||
#define MXC_CSPICTRL_SSCTL (1 << 6)
|
||||
#define MXC_CSPICTRL_SSPOL (1 << 7)
|
||||
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
|
||||
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
|
||||
#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
|
||||
#define MXC_CSPICTRL_TC (1 << 7)
|
||||
#define MXC_CSPICTRL_RXOVF (1 << 6)
|
||||
#define MXC_CSPICTRL_MAXBITS 0xfff
|
||||
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
|
||||
#define MAX_SPI_BYTES 4
|
||||
|
||||
#define MXC_SPI_BASE_ADDRESSES \
|
||||
IMX_CSPI1_BASE, \
|
||||
IMX_CSPI2_BASE, \
|
||||
IMX_CSPI3_BASE
|
||||
|
||||
#endif /* _IMX_REGS_H */
|
||||
529
u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h
Normal file
529
u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h
Normal file
@@ -0,0 +1,529 @@
|
||||
/*
|
||||
* (C) Copyright 2013 ADVANSEE
|
||||
* Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
|
||||
*
|
||||
* Based on mainline Linux i.MX iomux-mx25.h file:
|
||||
* Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* Based on Linux arch/arm/mach-mx25/mx25_pins.h:
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
|
||||
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __IOMUX_MX25_H__
|
||||
#define __IOMUX_MX25_H__
|
||||
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
|
||||
/* Pad control groupings */
|
||||
#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
|
||||
#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
|
||||
|
||||
/*
|
||||
* The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
|
||||
* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
|
||||
* See also iomux-v3.h
|
||||
*/
|
||||
|
||||
/* PAD MUX ALT INPSE PATH PADCTRL */
|
||||
enum {
|
||||
MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE),
|
||||
MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
|
||||
|
||||
MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
|
||||
|
||||
MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
|
||||
|
||||
MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP),
|
||||
|
||||
MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE),
|
||||
MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE),
|
||||
|
||||
MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP),
|
||||
|
||||
MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
|
||||
|
||||
MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
|
||||
|
||||
MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#endif /* __IOMUX_MX25_H__ */
|
||||
91
u-boot/arch/arm/include/asm/arch-mx25/macro.h
Normal file
91
u-boot/arch/arm/include/asm/arch-mx25/macro.h
Normal file
@@ -0,0 +1,91 @@
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Matthias Weisser <weisserm@arcor.de>
|
||||
*
|
||||
* (C) Copyright 2009 DENX Software Engineering
|
||||
* Author: John Rigby <jrigby@gmail.com>
|
||||
*
|
||||
* Common asm macros for imx25
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_MACRO_H__
|
||||
#define __ASM_ARM_ARCH_MACRO_H__
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <generated/asm-offsets.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
/*
|
||||
* AIPS setup - Only setup MPROTx registers.
|
||||
* The PACR default values are good.
|
||||
*
|
||||
* Default argument values:
|
||||
* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
|
||||
* user-mode.
|
||||
*/
|
||||
.macro init_aips mpr=0x77777777
|
||||
ldr r0, =IMX_AIPS1_BASE
|
||||
ldr r1, =\mpr
|
||||
str r1, [r0, #AIPS_MPR_0_7]
|
||||
str r1, [r0, #AIPS_MPR_8_15]
|
||||
ldr r2, =IMX_AIPS2_BASE
|
||||
str r1, [r2, #AIPS_MPR_0_7]
|
||||
str r1, [r2, #AIPS_MPR_8_15]
|
||||
.endm
|
||||
|
||||
/*
|
||||
* MAX (Multi-Layer AHB Crossbar Switch) setup
|
||||
*
|
||||
* Default argument values:
|
||||
* - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
|
||||
* - SGPCR: always park on last master
|
||||
* - MGPCR: restore default values
|
||||
*/
|
||||
.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
|
||||
ldr r0, =IMX_MAX_BASE
|
||||
ldr r1, =\mpr
|
||||
str r1, [r0, #MAX_MPR0] /* for S0 */
|
||||
str r1, [r0, #MAX_MPR1] /* for S1 */
|
||||
str r1, [r0, #MAX_MPR2] /* for S2 */
|
||||
str r1, [r0, #MAX_MPR3] /* for S3 */
|
||||
str r1, [r0, #MAX_MPR4] /* for S4 */
|
||||
ldr r1, =\sgpcr
|
||||
str r1, [r0, #MAX_SGPCR0] /* for S0 */
|
||||
str r1, [r0, #MAX_SGPCR1] /* for S1 */
|
||||
str r1, [r0, #MAX_SGPCR2] /* for S2 */
|
||||
str r1, [r0, #MAX_SGPCR3] /* for S3 */
|
||||
str r1, [r0, #MAX_SGPCR4] /* for S4 */
|
||||
ldr r1, =\mgpcr
|
||||
str r1, [r0, #MAX_MGPCR0] /* for M0 */
|
||||
str r1, [r0, #MAX_MGPCR1] /* for M1 */
|
||||
str r1, [r0, #MAX_MGPCR2] /* for M2 */
|
||||
str r1, [r0, #MAX_MGPCR3] /* for M3 */
|
||||
str r1, [r0, #MAX_MGPCR4] /* for M4 */
|
||||
.endm
|
||||
|
||||
/*
|
||||
* M3IF setup
|
||||
*
|
||||
* Default argument values:
|
||||
* - CTL:
|
||||
* MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
|
||||
* MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
|
||||
* MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
|
||||
* MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
|
||||
* MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000
|
||||
* MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000
|
||||
* MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000001
|
||||
*/
|
||||
.macro init_m3if ctl=0x00000001
|
||||
/* M3IF Control Register (M3IFCTL) */
|
||||
write32 IMX_M3IF_CTRL_BASE, \ctl
|
||||
.endm
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_ARM_ARCH_MACRO_H__ */
|
||||
23
u-boot/arch/arm/include/asm/arch-mx27/clock.h
Normal file
23
u-boot/arch/arm/include/asm/arch-mx27/clock.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
*
|
||||
* (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_FEC_CLK,
|
||||
};
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
|
||||
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
59
u-boot/arch/arm/include/asm/arch-mx27/gpio.h
Normal file
59
u-boot/arch/arm/include/asm/arch-mx27/gpio.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (C) 2012
|
||||
* Philippe Reynes <tremyfr@yahoo.fr>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ASM_ARCH_MX27_GPIO_H
|
||||
#define __ASM_ARCH_MX27_GPIO_H
|
||||
|
||||
/* GPIO registers */
|
||||
struct gpio_regs {
|
||||
u32 gpio_dir; /* DDIR */
|
||||
u32 ocr1;
|
||||
u32 ocr2;
|
||||
u32 iconfa1;
|
||||
u32 iconfa2;
|
||||
u32 iconfb1;
|
||||
u32 iconfb2;
|
||||
u32 gpio_dr; /* DR */
|
||||
u32 gius;
|
||||
u32 gpio_psr; /* SSR */
|
||||
u32 icr1;
|
||||
u32 icr2;
|
||||
u32 imr;
|
||||
u32 isr;
|
||||
u32 gpr;
|
||||
u32 swr;
|
||||
u32 puen;
|
||||
u32 res[0x2f];
|
||||
};
|
||||
|
||||
/* This structure is used by the function imx_gpio_mode */
|
||||
struct gpio_port_regs {
|
||||
struct gpio_regs port[6];
|
||||
};
|
||||
|
||||
/*
|
||||
* GPIO Module and I/O Multiplexer
|
||||
*/
|
||||
#define PORTA 0
|
||||
#define PORTB 1
|
||||
#define PORTC 2
|
||||
#define PORTD 3
|
||||
#define PORTE 4
|
||||
#define PORTF 5
|
||||
|
||||
#define GPIO_PIN_MASK 0x1f
|
||||
#define GPIO_PORT_SHIFT 5
|
||||
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user