avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
8
u-boot/arch/arm/cpu/armv8/hisilicon/Makefile
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8
u-boot/arch/arm/cpu/armv8/hisilicon/Makefile
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#
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# (C) Copyright 2015 Linaro
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# Peter Griffin <peter.griffin@linaro.org>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += pinmux.o
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184
u-boot/arch/arm/cpu/armv8/hisilicon/pinmux.c
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184
u-boot/arch/arm/cpu/armv8/hisilicon/pinmux.c
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/*
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* Copyright (C) 2015 Linaro.
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* Peter Griffin <peter.griffin@linaro.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/pinmux.h>
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struct hi6220_pinmux0_regs *pmx0 =
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(struct hi6220_pinmux0_regs *)HI6220_PINMUX0_BASE;
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struct hi6220_pinmux1_regs *pmx1 =
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(struct hi6220_pinmux1_regs *)HI6220_PINMUX1_BASE;
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static void hi6220_uart_config(int peripheral)
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{
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switch (peripheral) {
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case PERIPH_ID_UART0:
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writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */
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writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */
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writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */
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writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */
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break;
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case PERIPH_ID_UART1:
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writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */
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writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */
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writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */
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writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */
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writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/
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writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */
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writel(DRIVE1_02MA, &pmx1->iocfg[52]); /* UART1_RTS_N */
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writel(DRIVE1_02MA, &pmx1->iocfg[54]); /* UART1_TXD */
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break;
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case PERIPH_ID_UART2:
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writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */
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writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */
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writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */
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writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */
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writel(DRIVE1_02MA, &pmx1->iocfg[55]); /* UART2_CTS_N */
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writel(DRIVE1_02MA, &pmx1->iocfg[56]); /* UART2_RTS_N */
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writel(DRIVE1_02MA, &pmx1->iocfg[57]); /* UART2_RXD */
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writel(DRIVE1_02MA, &pmx1->iocfg[58]); /* UART2_TXD */
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break;
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case PERIPH_ID_UART3:
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writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */
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writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */
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writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */
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writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */
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/* UART3_TXD */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[100]);
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/* UART3_RTS_N */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[101]);
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/* UART3_RXD */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[102]);
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/* UART3_TXD */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[103]);
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break;
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case PERIPH_ID_UART4:
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writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */
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writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */
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writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */
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writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */
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/* UART4_CTS_N */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[120]);
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/* UART4_RTS_N */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[121]);
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/* UART4_RXD */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[122]);
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/* UART4_TXD */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[123]);
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break;
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case PERIPH_ID_UART5:
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writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */
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writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */
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/* UART5_RXD */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[118]);
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/* UART5_TXD */
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writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[119]);
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break;
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default:
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debug("%s: invalid peripheral %d", __func__, peripheral);
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return;
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}
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}
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static int hi6220_mmc_config(int peripheral)
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{
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u32 tmp;
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switch (peripheral) {
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case PERIPH_ID_SDMMC0:
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/* eMMC pinmux config */
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writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */
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writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */
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writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */
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writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */
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writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */
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writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */
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writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */
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writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */
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writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */
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writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */
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/*eMMC configure up/down/drive */
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writel(DRIVE1_08MA, &pmx1->iocfg[65]); /* EMMC_CLK */
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tmp = DRIVE1_04MA | PULL_UP;
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writel(tmp, &pmx1->iocfg[65]); /* EMMC_CMD */
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writel(tmp, &pmx1->iocfg[66]); /* EMMC_DATA0 */
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writel(tmp, &pmx1->iocfg[67]); /* EMMC_DATA1 */
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writel(tmp, &pmx1->iocfg[68]); /* EMMC_DATA2 */
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writel(tmp, &pmx1->iocfg[69]); /* EMMC_DATA3 */
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writel(tmp, &pmx1->iocfg[70]); /* EMMC_DATA4 */
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writel(tmp, &pmx1->iocfg[71]); /* EMMC_DATA5 */
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writel(tmp, &pmx1->iocfg[72]); /* EMMC_DATA6 */
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writel(tmp, &pmx1->iocfg[73]); /* EMMC_DATA7 */
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writel(DRIVE1_04MA, &pmx1->iocfg[73]); /* EMMC_RST_N */
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break;
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case PERIPH_ID_SDMMC1:
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writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */
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writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */
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writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */
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writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */
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writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */
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writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */
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writel(DRIVE1_10MA | BIT(2), &pmx1->iocfg[3]); /*SD_CLK*/
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writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[4]); /*SD_CMD*/
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writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[5]); /*SD_DATA0*/
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writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[6]); /*SD_DATA1*/
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writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[7]); /*SD_DATA2*/
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writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[8]); /*SD_DATA3*/
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break;
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default:
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debug("%s: invalid peripheral %d", __func__, peripheral);
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return -1;
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}
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return 0;
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}
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int hi6220_pinmux_config(int peripheral)
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{
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switch (peripheral) {
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART2:
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case PERIPH_ID_UART3:
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hi6220_uart_config(peripheral);
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break;
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case PERIPH_ID_SDMMC0:
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case PERIPH_ID_SDMMC1:
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return hi6220_mmc_config(peripheral);
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default:
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debug("%s: invalid peripheral %d", __func__, peripheral);
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return -1;
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}
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return 0;
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}
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