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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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31
u-boot/arch/arm/cpu/armv7/omap5/Kconfig Normal file
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if OMAP54XX
choice
prompt "OMAP5 board select"
optional
config TARGET_CM_T54
bool "CompuLab CM-T54"
config TARGET_OMAP5_UEVM
bool "TI OMAP5 uEVM board"
config TARGET_DRA7XX_EVM
bool "TI DRA7XX"
select TI_I2C_BOARD_DETECT
config TARGET_AM57XX_EVM
bool "AM57XX"
select TI_I2C_BOARD_DETECT
endchoice
config SYS_SOC
default "omap5"
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
source "board/ti/am57xx/Kconfig"
endif

16
u-boot/arch/arm/cpu/armv7/omap5/Makefile Normal file
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#
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += boot.o
obj-y += hwinit.o
obj-y += emif.o
obj-y += sdram.o
obj-y += prcm-regs.o
obj-y += hw_data.o
obj-y += abb.o
obj-y += fdt.o
obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o

57
u-boot/arch/arm/cpu/armv7/omap5/abb.c Normal file
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/*
* Adaptive Body Bias programming sequence for OMAP5 family
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/omap_common.h>
#include <asm/io.h>
/*
* Setup LDOVBB for OMAP5.
* On OMAP5+ some ABB settings are fused. They are handled
* in the following way:
*
* 1. corresponding EFUSE register contains ABB enable bit
* and VSET value
* 2. If ABB enable bit is set to 1, than ABB should be
* enabled, otherwise ABB should be disabled
* 3. If ABB is enabled, than VSET value should be copied
* to corresponding MUX control register
*/
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
{
u32 vset;
u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
if (!is_omap54xx()) {
/* DRA7 */
fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
}
/*
* ABB parameters must be properly fused
* otherwise ABB should be disabled
*/
vset = readl(fuse);
if (!(vset & fuse_enable_mask))
return -1;
/* prepare VSET value for LDOVBB mux register */
vset &= fuse_vset_mask;
vset >>= ffs(fuse_vset_mask) - 1;
vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
/* setup LDOVBB using fused value */
clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
return 0;
}

46
u-boot/arch/arm/cpu/armv7/omap5/boot.c Normal file
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/*
* OMAP5 boot
*
* Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/omap_common.h>
#include <spl.h>
static u32 boot_devices[] = {
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
BOOT_DEVICE_MMC2,
BOOT_DEVICE_NAND,
BOOT_DEVICE_MMC1,
BOOT_DEVICE_SATA,
BOOT_DEVICE_XIP,
BOOT_DEVICE_XIP,
BOOT_DEVICE_SPI,
BOOT_DEVICE_SPI,
#else
BOOT_DEVICE_MMC2,
BOOT_DEVICE_NAND,
BOOT_DEVICE_MMC1,
BOOT_DEVICE_SATA,
BOOT_DEVICE_XIP,
BOOT_DEVICE_MMC2,
BOOT_DEVICE_XIPWAIT,
#endif
};
u32 omap_sys_boot_device(void)
{
u32 sys_boot;
/* Grab the first 4 bits of the status register for SYS_BOOT. */
sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 4) - 1);
if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
return BOOT_DEVICE_NONE;
return boot_devices[sys_boot];
}

19
u-boot/arch/arm/cpu/armv7/omap5/config.mk Normal file
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#
# Copyright 2011 Linaro Limited
#
# Aneesh V <annesh@ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
ifdef CONFIG_SPL_BUILD
ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
ALL-y += u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER
else
ALL-y += MLO
endif
else
ALL-y += u-boot.img
endif

274
u-boot/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c Normal file
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/*
* (C) Copyright 2015
* Texas Instruments Incorporated, <www.ti.com>
*
* Lokesh Vutla <lokeshvutla@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/utils.h>
#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/arch/mux_dra7xx.h>
#include <asm/omap_common.h>
static int isolate_io(u32 isolate)
{
if (isolate) {
clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ,
SDCARD_PWRDNZ);
clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ,
SDCARD_BIAS_PWRDNZ);
}
/* Override control on ISOCLKIN signal to IO pad ring. */
clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
PMCTRL_ISOCLK_OVERRIDE_CTRL);
if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK,
(u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
return ERR_DEISOLATE_IO << isolate;
/* Isolate/Deisolate IO */
clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK,
isolate << CTRL_ISOLATE_SHIFT);
/* Dummy read to add delay t > 10ns */
readl((*ctrl)->ctrl_core_sma_sw_0);
/* Return control on ISOCLKIN to hardware */
clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL);
if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK,
0 << PMCTRL_ISOCLK_STATUS_SHIFT,
(u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
return ERR_DEISOLATE_IO << isolate;
return 0;
}
static int calibrate_iodelay(u32 base)
{
u32 reg;
/* Configure REFCLK period */
reg = readl(base + CFG_REG_2_OFFSET);
reg &= ~CFG_REG_REFCLK_PERIOD_MASK;
reg |= CFG_REG_REFCLK_PERIOD;
writel(reg, base + CFG_REG_2_OFFSET);
/* Initiate Calibration */
clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK,
CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT);
if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END,
(u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
return ERR_CALIBRATE_IODELAY;
return 0;
}
static int update_delay_mechanism(u32 base)
{
/* Initiate the reload of calibrated values. */
clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,
CFG_REG_ROM_READ_START);
if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END,
(u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
return ERR_UPDATE_DELAY;
return 0;
}
static u32 calculate_delay(u32 base, u16 offset, u16 den)
{
u16 refclk_period, dly_cnt, ref_cnt;
u32 reg, q, r;
refclk_period = readl(base + CFG_REG_2_OFFSET) &
CFG_REG_REFCLK_PERIOD_MASK;
reg = readl(base + offset);
dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT;
ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT;
if (!dly_cnt || !den)
return 0;
/*
* To avoid overflow and integer truncation, delay value
* is calculated as quotient + remainder.
*/
q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den));
r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) /
(2 * dly_cnt * den);
return q + r;
}
static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
{
u32 g_delay_coarse, g_delay_fine;
u32 a_delay_coarse, a_delay_fine;
u32 c_elements, f_elements;
u32 total_delay, reg = 0;
g_delay_coarse = g_delay / 920;
g_delay_fine = ((g_delay % 920) * 10) / 60;
a_delay_coarse = a_delay / cpde;
a_delay_fine = ((a_delay % cpde) * 10) / fpde;
c_elements = g_delay_coarse + a_delay_coarse;
f_elements = (g_delay_fine + a_delay_fine) / 10;
if (f_elements > 22) {
total_delay = c_elements * cpde + f_elements * fpde;
c_elements = total_delay / cpde;
f_elements = (total_delay % cpde) / fpde;
}
reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK;
reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK;
reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT;
reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT;
return reg;
}
int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
int niodelays)
{
struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
u32 reg, cpde, fpde, i;
if (!niodelays)
return 0;
cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET,
88);
if (!cpde)
return ERR_CPDE;
fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET,
264);
if (!fpde)
return ERR_FPDE;
for (i = 0; i < niodelays; i++, iodelay++) {
reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde,
fpde);
writel(reg, base + iodelay->offset);
}
return 0;
}
int __recalibrate_iodelay_start(void)
{
int ret = 0;
/* IO recalibration should be done only from SRAM */
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
return -1;
}
/* unlock IODELAY CONFIG registers */
writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
CFG_REG_8_OFFSET);
ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
if (ret)
goto err;
ret = isolate_io(ISOLATE_IO);
if (ret)
goto err;
ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
err:
return ret;
}
void __recalibrate_iodelay_end(int ret)
{
/* IO recalibration should be done only from SRAM */
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
return;
}
if (!ret)
ret = isolate_io(DEISOLATE_IO);
/* lock IODELAY CONFIG registers */
writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
CFG_REG_8_OFFSET);
/*
* UART cannot be used during IO recalibration sequence as IOs are in
* isolation. So error handling and debug prints are done after
* complete IO delay recalibration sequence
*/
switch (ret) {
case ERR_CALIBRATE_IODELAY:
puts("IODELAY: IO delay calibration sequence failed\n");
break;
case ERR_ISOLATE_IO:
puts("IODELAY: Isolation of Device IOs failed\n");
break;
case ERR_UPDATE_DELAY:
puts("IODELAY: Delay mechanism update with new calibrated values failed\n");
break;
case ERR_DEISOLATE_IO:
puts("IODELAY: De-isolation of Device IOs failed\n");
break;
case ERR_CPDE:
puts("IODELAY: CPDE calculation failed\n");
break;
case ERR_FPDE:
puts("IODELAY: FPDE calculation failed\n");
break;
case -1:
puts("IODELAY: Wrong Context call?\n");
break;
default:
debug("IODELAY: IO delay recalibration successfully completed\n");
}
return;
}
void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
struct iodelay_cfg_entry const *iodelay,
int niodelays)
{
int ret = 0;
/* IO recalibration should be done only from SRAM */
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
return;
}
ret = __recalibrate_iodelay_start();
if (ret)
goto err;
/* Configure Mux settings */
do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
/* Configure Manual IO timing modes */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
if (ret)
goto err;
err:
__recalibrate_iodelay_end(ret);
}

88
u-boot/arch/arm/cpu/armv7/omap5/emif.c Normal file
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/*
* EMIF programming
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com> for OMAP4
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* Base AC Timing values specified by JESD209-2 for 532MHz operation */
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
.max_freq = 532000000,
.RL = 8,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 15,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
/*
* Min tCK values specified by JESD209-2
* Min tCK specifies the minimum duration of some AC timing parameters in terms
* of the number of cycles. If the calculated number of cycles based on the
* absolute time value is less than the min tCK value, min tCK value should
* be used instead. This typically happens at low frequencies.
*/
static const struct lpddr2_min_tck min_tck_jedec = {
.tRL = 3,
.tRP_AB = 3,
.tRCD = 3,
.tWR = 3,
.tRAS_MIN = 3,
.tRRD = 2,
.tWTR = 2,
.tXP = 2,
.tRTP = 2,
.tCKE = 3,
.tCKESR = 3,
.tFAW = 8
};
static const struct lpddr2_ac_timings const*
jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
&timings_jedec_532_mhz
};
static const struct lpddr2_device_timings jedec_default_timings = {
.ac_timings = jedec_ac_timings,
.min_tck = &min_tck_jedec
};
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
{
/* Assume Identical devices on EMIF1 & EMIF2 */
*cs0_device_timings = &jedec_default_timings;
*cs1_device_timings = NULL;
}
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */

184
u-boot/arch/arm/cpu/armv7/omap5/fdt.c Normal file
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/*
* Copyright 2016 Texas Instruments, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <malloc.h>
#include <asm/omap_common.h>
#include <asm/arch-omap5/sys_proto.h>
#ifdef CONFIG_TI_SECURE_DEVICE
/* Give zero values if not already defined */
#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
#endif
#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
#endif
static u32 hs_irq_skip[] = {
8, /* Secure violation reporting interrupt */
15, /* One interrupt for SDMA by secure world */
118 /* One interrupt for Crypto DMA by secure world */
};
static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
{
const char *path;
int offs;
int ret;
int len, i, old_cnt, new_cnt;
u32 *temp;
const u32 *p_data;
/*
* Increase the size of the fdt
* so we have some breathing room
*/
ret = fdt_increase_size(fdt, 512);
if (ret < 0) {
printf("Could not increase size of device tree: %s\n",
fdt_strerror(ret));
return ret;
}
/* Reserve IRQs that are used/needed by secure world */
path = "/ocp/crossbar";
offs = fdt_path_offset(fdt, path);
if (offs < 0) {
debug("Node %s not found.\n", path);
return 0;
}
/* Get current entries */
p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
if (p_data)
old_cnt = len / sizeof(u32);
else
old_cnt = 0;
new_cnt = sizeof(hs_irq_skip) /
sizeof(hs_irq_skip[0]);
/* Create new/updated skip list for HS parts */
temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
for (i = 0; i < new_cnt; i++)
temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
for (i = 0; i < old_cnt; i++)
temp[i + new_cnt] = p_data[i];
/* Blow away old data and set new data */
fdt_delprop(fdt, offs, "ti,irqs-skip");
ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
temp,
(old_cnt + new_cnt) * sizeof(u32));
free(temp);
/* Check if the update worked */
if (ret < 0) {
printf("Could not add ti,irqs-skip property to node %s: %s\n",
path, fdt_strerror(ret));
return ret;
}
return 0;
}
static int ft_hs_disable_rng(void *fdt, bd_t *bd)
{
const char *path;
int offs;
int ret;
/* Make HW RNG reserved for secure world use */
path = "/ocp/rng";
offs = fdt_path_offset(fdt, path);
if (offs < 0) {
debug("Node %s not found.\n", path);
return 0;
}
ret = fdt_setprop_string(fdt, offs,
"status", "disabled");
if (ret < 0) {
printf("Could not add status property to node %s: %s\n",
path, fdt_strerror(ret));
return ret;
}
return 0;
}
#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
(CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
{
const char *path;
int offs;
int ret;
u32 temp[2];
/*
* Update SRAM reservations on secure devices. The OCMC RAM
* is always reserved for secure use from the start of that
* memory region
*/
path = "/ocp/ocmcram@40300000/sram-hs";
offs = fdt_path_offset(fdt, path);
if (offs < 0) {
debug("Node %s not found.\n", path);
return 0;
}
/* relative start offset */
temp[0] = cpu_to_fdt32(0);
/* reservation size */
temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
fdt_delprop(fdt, offs, "reg");
ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
if (ret < 0) {
printf("Could not add reg property to node %s: %s\n",
path, fdt_strerror(ret));
return ret;
}
return 0;
}
#else
static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
#endif
static void ft_hs_fixups(void *fdt, bd_t *bd)
{
/* Check we are running on an HS/EMU device type */
if (GP_DEVICE != get_device_type()) {
if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
(ft_hs_disable_rng(fdt, bd) == 0) &&
(ft_hs_fixup_sram(fdt, bd) == 0))
return;
} else {
printf("ERROR: Incorrect device type (GP) detected!");
}
/* Fixup failed or wrong device type */
hang();
}
#else
static void ft_hs_fixups(void *fdt, bd_t *bd)
{
}
#endif
/*
* Place for general cpu/SoC FDT fixups. Board specific
* fixups should remain in the board files which is where
* this function should be called from.
*/
void ft_cpu_setup(void *fdt, bd_t *bd)
{
ft_hs_fixups(fdt, bd);
}

774
u-boot/arch/arm/cpu/armv7/omap5/hw_data.c Normal file
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@@ -0,0 +1,774 @@
/*
*
* HW data initialization for OMAP5
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <palmas.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
#include <asm/emif.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
/* OPP HIGH FREQUENCY for ES2.0 */
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP NOM FREQUENCY for ES1.0 */
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP LOW FREQUENCY for ES1.0 */
static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP LOW FREQUENCY for ES2.0 */
static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
{499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
{266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
{266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
{443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
{277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
{368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
{277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
{368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
{1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};
/* ABE M & N values with sysclk2(22.5792 MHz) as input */
static const struct dpll_params
abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
{111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
{250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
{250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
{119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
struct dplls omap5_dplls_es1 = {
.mpu = mpu_dpll_params_800mhz,
.core = core_dpll_params_2128mhz_ddr532,
.per = per_dpll_params_768mhz,
.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap5_dplls_es2 = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_ddr532_es2,
.per = per_dpll_params_768mhz_es2,
.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2128mhz,
.gmac = gmac_dpll_params_2000mhz,
};
struct dplls dra72x_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2664mhz,
.gmac = gmac_dpll_params_2000mhz,
};
struct pmic_data palmas = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
.pmic_bus_init = sri2c_init,
.pmic_write = omap_vc_bypass_send_value,
};
/* The TPS659038 and TPS65917 are software-compatible, use common struct */
struct pmic_data tps659038 = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
.i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
.pmic_bus_init = gpi2c_init,
.pmic_write = palmas_i2c_write_u8,
};
struct vcores_data omap5430_volts = {
.mpu.value = VDD_MPU,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.core.value = VDD_CORE,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
.mm.value = VDD_MM,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
};
struct vcores_data omap5430_volts_es2 = {
.mpu.value = VDD_MPU_ES2,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.core.value = VDD_CORE_ES2,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
.mm.value = VDD_MM_ES2,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)->cm_gmac_clkstctrl,
#endif
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
(*prcm)->cm_l4per_gpio7_clkctrl,
(*prcm)->cm_l4per_gpio8_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)->cm_gmac_gmac_clkctrl,
#endif
#ifdef CONFIG_TI_QSPI
(*prcm)->cm_l4per_qspi_clkctrl,
#endif
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Set the correct clock dividers for mmc */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
#ifdef CONFIG_TI_QSPI
setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
#endif
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_CORE_MASK);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
(*prcm)->cm_ipu_clkstctrl,
#endif
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
(*prcm)->cm_ipu_i2c5_clkctrl,
#else
(*prcm)->cm_l4per_i2c5_clkctrl,
#endif
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
#ifdef CONFIG_TI_EDMA3
void enable_edma3_clocks(void)
{
u32 const clk_domains_edma3[] = {
0
};
u32 const clk_modules_hw_auto_edma3[] = {
(*prcm)->cm_l3main1_tptc1_clkctrl,
(*prcm)->cm_l3main1_tptc2_clkctrl,
0
};
u32 const clk_modules_explicit_en_edma3[] = {
0
};
do_enable_clocks(clk_domains_edma3,
clk_modules_hw_auto_edma3,
clk_modules_explicit_en_edma3,
1);
}
void disable_edma3_clocks(void)
{
u32 const clk_domains_edma3[] = {
0
};
u32 const clk_modules_disable_edma3[] = {
(*prcm)->cm_l3main1_tptc1_clkctrl,
(*prcm)->cm_l3main1_tptc2_clkctrl,
0
};
do_disable_clocks(clk_domains_edma3,
clk_modules_disable_edma3,
1);
}
#endif
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
void enable_usb_clocks(int index)
{
u32 cm_l3init_usb_otg_ss_clkctrl = 0;
if (index == 0) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
/* Enable 960 MHz clock for dwc3 */
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Enable 32 KHz clock for USB_PHY1 */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Enable 32 KHz clock for USB_PHY3 */
if (is_dra7xx())
setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
/* Enable 960 MHz clock for dwc3 */
setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Enable 32 KHz clock for dwc3 */
setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Enable 60 MHz clock for USB2PHY2 */
setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
}
u32 const clk_domains_usb[] = {
0
};
u32 const clk_modules_hw_auto_usb[] = {
(*prcm)->cm_l3init_ocp2scp1_clkctrl,
cm_l3init_usb_otg_ss_clkctrl,
0
};
u32 const clk_modules_explicit_en_usb[] = {
0
};
do_enable_clocks(clk_domains_usb,
clk_modules_hw_auto_usb,
clk_modules_explicit_en_usb,
1);
}
void disable_usb_clocks(int index)
{
u32 cm_l3init_usb_otg_ss_clkctrl = 0;
if (index == 0) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
/* Disable 960 MHz clock for dwc3 */
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Disable 32 KHz clock for USB_PHY1 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Disable 32 KHz clock for USB_PHY3 */
if (is_dra7xx())
clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
/* Disable 960 MHz clock for dwc3 */
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Disable 32 KHz clock for dwc3 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Disable 60 MHz clock for USB2PHY2 */
clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
}
u32 const clk_domains_usb[] = {
0
};
u32 const clk_modules_disable[] = {
(*prcm)->cm_l3init_ocp2scp1_clkctrl,
cm_l3init_usb_otg_ss_clkctrl,
0
};
do_disable_clocks(clk_domains_usb,
clk_modules_disable,
1);
}
#endif
const struct ctrl_ioregs ioregs_omap5430 = {
.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
.ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
.ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
.ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
};
const struct ctrl_ioregs ioregs_omap5432_es1 = {
.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
.ctrl_lpddr2ch = 0x0,
.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
};
const struct ctrl_ioregs ioregs_omap5432_es2 = {
.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
.ctrl_lpddr2ch = 0x0,
.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
};
const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
const struct ctrl_ioregs ioregs_dra72x_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x60606080,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
const struct ctrl_ioregs ioregs_dra72x_es2 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x60606060,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x00000000,
.ctrl_ddrio_2 = 0x00000000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
void __weak hw_data_init(void)
{
u32 omap_rev = omap_revision();
switch (omap_rev) {
case OMAP5430_ES1_0:
case OMAP5432_ES1_0:
*prcm = &omap5_es1_prcm;
*dplls_data = &omap5_dplls_es1;
*omap_vcores = &omap5430_volts;
*ctrl = &omap5_ctrl;
break;
case OMAP5430_ES2_0:
case OMAP5432_ES2_0:
*prcm = &omap5_es2_prcm;
*dplls_data = &omap5_dplls_es2;
*omap_vcores = &omap5430_volts_es2;
*ctrl = &omap5_ctrl;
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
*ctrl = &dra7xx_ctrl;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
}
void get_ioregs(const struct ctrl_ioregs **regs)
{
u32 omap_rev = omap_revision();
switch (omap_rev) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = &ioregs_omap5430;
break;
case OMAP5432_ES1_0:
*regs = &ioregs_omap5432_es1;
break;
case OMAP5432_ES2_0:
*regs = &ioregs_omap5432_es2;
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
*regs = &ioregs_dra7xx_es1;
break;
case DRA722_ES1_0:
*regs = &ioregs_dra72x_es1;
break;
case DRA722_ES2_0:
*regs = &ioregs_dra72x_es2;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
}

453
u-boot/arch/arm/cpu/armv7/omap5/hwinit.c Normal file
View File

@@ -0,0 +1,453 @@
/*
*
* Functions for omap5 based boards.
*
* (C) Copyright 2011
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
* Sricharan <r.sricharan@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <linux/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
#ifndef CONFIG_DM_GPIO
static struct gpio_bank gpio_bank_54xx[8] = {
{ (void *)OMAP54XX_GPIO1_BASE },
{ (void *)OMAP54XX_GPIO2_BASE },
{ (void *)OMAP54XX_GPIO3_BASE },
{ (void *)OMAP54XX_GPIO4_BASE },
{ (void *)OMAP54XX_GPIO5_BASE },
{ (void *)OMAP54XX_GPIO6_BASE },
{ (void *)OMAP54XX_GPIO7_BASE },
{ (void *)OMAP54XX_GPIO8_BASE },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#endif
void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
{
int i;
struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
for (i = 0; i < size; i++, pad++)
writel(pad->val, base + pad->offset);
}
#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
if (!is_dra7xx()) {
writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
}
/* omap5432 does not use lpddr2 */
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif1_sdram_config_ext);
if (!is_dra72x())
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif2_sdram_config_ext);
if (is_omap54xx()) {
/* Disable DLL select */
io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
(*ctrl)->control_port_emif1_sdram_config);
io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
(*ctrl)->control_port_emif2_sdram_config);
} else {
writel(ioregs->ctrl_ddr_ctrl_ext_0,
(*ctrl)->control_ddr_control_ext_0);
}
}
/*
* Some tuning of IOs for optimal power and performance
*/
void do_io_settings(void)
{
u32 io_settings = 0, mask = 0;
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) |
(ds_mask << 16) | (ds_mask << 18);
io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
(~mask);
io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
(ds_45_ohm << 18) | (ds_60_ohm << 2);
writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
/* Impedance settings Mcspi2 */
mask = (ds_mask << 30);
io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 30);
writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
/* Impedance settings C2C 3,4 */
mask = (ds_mask << 14) | (ds_mask << 16);
io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
(~mask);
io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
/* Slew rate settings EMMC, C2C 1,2 */
mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
(~mask);
io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
/* Slew rate settings hsi2, Mcspi2 */
mask = (sc_mask << 24) | (sc_mask << 28);
io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
(~mask);
io_settings |= (sc_fast << 28) | (sc_fast << 24);
writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
/* Slew rate settings C2C 3,4 */
mask = (sc_mask << 16) | (sc_mask << 18);
io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
(~mask);
io_settings |= (sc_na << 16) | (sc_na << 18);
writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
/* impedance and slew rate settings for usb */
mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
(ds_60_ohm << 23) | (sc_fast << 20) |
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();
}
static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
{0x45, 0x1}, /* 12 MHz */
{-1, -1}, /* 13 MHz */
{0x63, 0x2}, /* 16.8 MHz */
{0x57, 0x2}, /* 19.2 MHz */
{0x20, 0x1}, /* 26 MHz */
{-1, -1}, /* 27 MHz */
{0x41, 0x3} /* 38.4 MHz */
};
void srcomp_enable(void)
{
u32 srcomp_value, mul_factor, div_factor, clk_val, i;
u32 sysclk_ind = get_sys_clk_index();
u32 omap_rev = omap_revision();
if (!is_omap54xx())
return;
mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
div_factor = srcomp_parameters[sysclk_ind].divide_factor;
for (i = 0; i < 4; i++) {
srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &=
~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
(div_factor << DIVIDE_FACTOR_XS_SHIFT);
writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
}
if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
for (i = 0; i < 4; i++) {
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~PWRDWN_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
while (((readl((*ctrl)->control_srcomp_north_side + i*4)
& SRCODE_READ_XS_MASK) >>
SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
} else {
srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
DIVIDE_FACTOR_XS_MASK);
srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
(div_factor << DIVIDE_FACTOR_XS_SHIFT);
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
for (i = 0; i < 4; i++) {
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
for (i = 0; i < 4; i++) {
while (((readl((*ctrl)->control_srcomp_north_side + i*4)
& SRCODE_READ_XS_MASK) >>
SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
}
}
#endif
void config_data_eye_leveling_samples(u32 emif_base)
{
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(ioregs->ctrl_emif_sdram_config_ext_final,
(*ctrl)->control_emif1_sdram_config_ext);
else if (emif_base == EMIF2_BASE)
writel(ioregs->ctrl_emif_sdram_config_ext_final,
(*ctrl)->control_emif2_sdram_config_ext);
}
void init_cpu_configuration(void)
{
u32 l2actlr;
asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
/*
* L2ACTLR: Ensure to enable the following:
* 3: Disable clean/evict push to external
* 4: Disable WriteUnique and WriteLineUnique transactions from master
* 8: Disable DVM/CMO message broadcast
*/
l2actlr |= 0x118;
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
}
void init_omap_revision(void)
{
/*
* For some of the ES2/ES1 boards ID_CODE is not reliable:
* Also, ES1 and ES2 have different ARM revisions
* So use ARM revision for identification
*/
unsigned int rev = cortex_rev();
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP5430_ES1_0;
if (rev == MIDR_CORTEX_A15_R2P2)
*omap_si_rev = OMAP5430_ES2_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP5432_ES1_0;
if (rev == MIDR_CORTEX_A15_R2P2)
*omap_si_rev = OMAP5432_ES2_0;
break;
case OMAP5430_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5430_ES2_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5432_ES2_0;
break;
case DRA752_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA752_ES1_0;
break;
case DRA752_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = DRA752_ES1_1;
break;
case DRA752_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = DRA752_ES2_0;
break;
case DRA722_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA722_ES1_0;
break;
case DRA722_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = DRA722_ES2_0;
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
init_cpu_configuration();
}
void omap_die_id(unsigned int *die_id)
{
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
}
void reset_cpu(ulong ignored)
{
u32 omap_rev = omap_revision();
/*
* WARM reset is not functional in case of OMAP5430 ES1.0 soc.
* So use cold reset in case instead.
*/
if (omap_rev == OMAP5430_ES1_0)
writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
else
writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
}
u32 warm_reset(void)
{
return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}
void setup_warmreset_time(void)
{
u32 rst_time, rst_val;
#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
#else
rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
#endif
rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
if (rst_time > RSTTIME1_MASK)
rst_time = RSTTIME1_MASK;
rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
rst_val |= rst_time;
writel(rst_val, (*prcm)->prm_rsttime);
}
void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
u32 cpu_rev_comb, u32 cpu_variant,
u32 cpu_rev)
{
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
}
void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
u32 cpu_variant, u32 cpu_rev)
{
#ifdef CONFIG_ARM_ERRATA_801819
/*
* DRA72x processors are uniprocessors and DONOT have
* ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
* Extensions) Hence the erratum workaround is not applicable for
* DRA72x processors.
*/
if (is_dra72x())
acr &= ~((0x3 << 23) | (0x3 << 25));
#endif
omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
}

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u-boot/arch/arm/cpu/armv7/omap5/prcm-regs.c Normal file
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/*
* Timing and Organization details of the ddr device parts used in OMAP5
* EVM
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
* Sricharan R <r.sricharan@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
/*
* This file provides details of the LPDDR2 SDRAM parts used on OMAP5
* EVM. Since the parts used and geometry are identical for
* evm for a given OMAP5 revision, this information is kept
* here instead of being in board directory. However the key functions
* exported are weakly linked so that they can be over-ridden in the board
* directory if there is a OMAP5 board in the future that uses a different
* memory device or geometry.
*
* For any new board with different memory devices over-ride one or more
* of the following functions as per the CONFIG flags you intend to enable:
* - emif_get_reg_dump()
* - emif_get_dmm_regs()
* - emif_get_device_details()
* - emif_get_device_timings()
*/
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
const struct emif_regs emif_regs_532_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
.ref_ctrl = 0x0000081A,
.sdram_tim1 = 0x772F6873,
.sdram_tim2 = 0x304a129a,
.sdram_tim3 = 0x02f7e45f,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x000b3215,
.temp_alert_config = 0x08000a05,
.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
.emif_ddr_phy_ctlr_1 = 0x0E28420d,
.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
.ref_ctrl = 0x0000081A,
.sdram_tim1 = 0x772F6873,
.sdram_tim2 = 0x304a129a,
.sdram_tim3 = 0x02f7e45f,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x100b3215,
.temp_alert_config = 0x08000a05,
.emif_ddr_phy_ctlr_1_init = 0x0E30400d,
.emif_ddr_phy_ctlr_1 = 0x0E30400d,
.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
.emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
};
const struct emif_regs emif_regs_266_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
.ref_ctrl = 0x0000040D,
.sdram_tim1 = 0x2A86B419,
.sdram_tim2 = 0x1025094A,
.sdram_tim3 = 0x026BA22F,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x000b3215,
.temp_alert_config = 0x08000a05,
.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
.emif_ddr_phy_ctlr_1 = 0x0E28420d,
.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
.emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
.emif_ddr_ext_phy_ctrl_3 = 0x14829052,
.emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0020420A,
.emif_ddr_phy_ctlr_1 = 0x0024420A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
.emif_ddr_ext_phy_ctrl_5 = 0x04010040,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x1007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0030400A,
.emif_ddr_phy_ctlr_1 = 0x0034400A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
.emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x40000305
};
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
*regs = &emif_regs_532_mhz_2cs;
break;
case OMAP5432_ES1_0:
*regs = &emif_regs_ddr3_532_mhz_1cs;
break;
case OMAP5430_ES2_0:
*regs = &emif_regs_532_mhz_2cs_es2;
break;
case OMAP5432_ES2_0:
default:
*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
break;
}
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
**dmm_lisa_regs)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
case OMAP5432_ES1_0:
case OMAP5432_ES2_0:
default:
*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
break;
}
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
#else
static const struct lpddr2_device_details dev_4G_S4_details = {
.type = LPDDR2_TYPE_S4,
.density = LPDDR2_DENSITY_4Gb,
.io_width = LPDDR2_IO_WIDTH_32,
.manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
};
static void emif_get_device_details_sdp(u32 emif_nr,
struct lpddr2_device_details *cs0_device_details,
struct lpddr2_device_details *cs1_device_details)
{
/* EMIF1 & EMIF2 have identical configuration */
*cs0_device_details = dev_4G_S4_details;
*cs1_device_details = dev_4G_S4_details;
}
void emif_get_device_details(u32 emif_nr,
struct lpddr2_device_details *cs0_device_details,
struct lpddr2_device_details *cs1_device_details)
__attribute__((weak, alias("emif_get_device_details_sdp")));
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
const u32 ext_phy_ctrl_const_base[] = {
0x01004010,
0x00001004,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000001,
0x540A8150,
0xA81502a0,
0x002A0540,
0x00000000,
0x00000000,
0x00000000,
0x00000077,
0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
0x01004010,
0x00001004,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000002,
0x0,
0x0,
0x0,
0x00000000,
0x00000000,
0x00000000,
0x00000057,
0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
0x50D4350D,
0x00000D43,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000002,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000057,
0x0
};
/* Ext phy ctrl 1-35 regs */
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
0x10040100,
0x00910091,
0x00950095,
0x009B009B,
0x009E009E,
0x00980098,
0x00340034,
0x00350035,
0x00340034,
0x00310031,
0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00480048,
0x004A004A,
0x00520052,
0x00550055,
0x00500050,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0
};
/* Ext phy ctrl 1-35 regs */
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x10040100,
0x00910091,
0x00950095,
0x009B009B,
0x009E009E,
0x00980098,
0x00330033,
0x00330033,
0x002F002F,
0x00320032,
0x00310031,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00520052,
0x00520052,
0x00470047,
0x00490049,
0x00500050,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0
};
/* Ext phy ctrl 1-35 regs */
const u32
dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
0x10040100,
0x00A400A4,
0x00A900A9,
0x00B000B0,
0x00B000B0,
0x00A400A4,
0x00390039,
0x00320032,
0x00320032,
0x00320032,
0x00440044,
0x00550055,
0x00550055,
0x00550055,
0x00550055,
0x007F007F,
0x004D004D,
0x00430043,
0x00560056,
0x00540054,
0x00600060,
0x0,
0x00600020,
0x40010080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0
};
const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
0x04040100,
0x006B009F,
0x006B00A2,
0x006B00A8,
0x006B00A8,
0x006B00B2,
0x002F002F,
0x002F002F,
0x002F002F,
0x002F002F,
0x002F002F,
0x00600073,
0x00600071,
0x0060007C,
0x0060007E,
0x00600084,
0x00400053,
0x00400051,
0x0040005C,
0x0040005E,
0x00400064,
0x00800080,
0x00800080,
0x40010080,
0x08102040,
0x005B008F,
0x005B0092,
0x005B0098,
0x005B0098,
0x005B00A2,
0x00300043,
0x00300041,
0x0030004C,
0x0030004E,
0x00300054,
0x00000077
};
const struct lpddr2_mr_regs mr_regs = {
.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
.mr2 = 0x6,
.mr3 = 0x1,
.mr10 = MR10_ZQ_ZQINIT,
.mr16 = MR16_REF_FULL_ARRAY
};
void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
const u32 **regs,
u32 *size)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = ext_phy_ctrl_const_base;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
break;
case OMAP5432_ES1_0:
*regs = ddr3_ext_phy_ctrl_const_base_es1;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
break;
case OMAP5432_ES2_0:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
if (emif_nr == 1) {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
*size =
ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
} else {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
*size =
ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
}
break;
case DRA722_ES1_0:
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
break;
case DRA722_ES2_0:
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
}
}
void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
*regs = &mr_regs;
}
static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
u32 size;
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
/* Configure external phy control timing registers */
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
}
/*
* external phy 6-24 registers do not change with
* ddr frequency
*/
emif_get_ext_phy_ctrl_const_regs(emif_nr,
&ext_phy_ctrl_const_regs, &size);
for (i = 0; i < size; i++) {
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
}
}
static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 *emif_ext_phy_ctrl_base = 0;
u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i, hw_leveling, size, phy;
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
phy = regs->emif_ddr_phy_ctlr_1_init;
emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
emif_get_ext_phy_ctrl_const_regs(emif_nr,
&ext_phy_ctrl_const_regs, &size);
writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
/*
* Copy the predefined PHY register values
* if leveling is disabled.
*/
if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
for (i = 1; i < 6; i++) {
writel(ext_phy_ctrl_const_regs[i],
&emif_ext_phy_ctrl_base[i * 2]);
writel(ext_phy_ctrl_const_regs[i],
&emif_ext_phy_ctrl_base[i * 2 + 1]);
}
if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
for (i = 6; i < 11; i++) {
writel(ext_phy_ctrl_const_regs[i],
&emif_ext_phy_ctrl_base[i * 2]);
writel(ext_phy_ctrl_const_regs[i],
&emif_ext_phy_ctrl_base[i * 2 + 1]);
}
if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
for (i = 11; i < 25; i++) {
writel(ext_phy_ctrl_const_regs[i],
&emif_ext_phy_ctrl_base[i * 2]);
writel(ext_phy_ctrl_const_regs[i],
&emif_ext_phy_ctrl_base[i * 2 + 1]);
}
if (hw_leveling) {
/*
* Write the init value for HW levling to occur
*/
for (i = 21; i < 35; i++) {
writel(ext_phy_ctrl_const_regs[i],
&emif_ext_phy_ctrl_base[i * 2]);
writel(ext_phy_ctrl_const_regs[i],
&emif_ext_phy_ctrl_base[i * 2 + 1]);
}
}
}
void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
if (is_omap54xx())
do_ext_phy_settings_omap5(base, regs);
else
do_ext_phy_settings_dra7(base, regs);
}
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
.max_freq = 532000000,
.RL = 8,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 15,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
static const struct lpddr2_min_tck min_tck = {
.tRL = 3,
.tRP_AB = 3,
.tRCD = 3,
.tWR = 3,
.tRAS_MIN = 3,
.tRRD = 2,
.tWTR = 2,
.tXP = 2,
.tRTP = 2,
.tCKE = 3,
.tCKESR = 3,
.tFAW = 8
};
static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
&timings_jedec_532_mhz
};
static const struct lpddr2_device_timings dev_4G_S4_timings = {
.ac_timings = ac_timings,
.min_tck = &min_tck,
};
/*
* List of status registers to be controlled back to control registers
* after initial leveling
* readreg, writereg
*/
const struct read_write_regs omap5_bug_00339_regs[] = {
{ 8, 5 },
{ 9, 6 },
{ 10, 7 },
{ 14, 8 },
{ 15, 9 },
{ 16, 10 },
{ 11, 2 },
{ 12, 3 },
{ 13, 4 },
{ 17, 11 },
{ 18, 12 },
{ 19, 13 },
};
const struct read_write_regs dra_bug_00339_regs[] = {
{ 7, 7 },
{ 8, 8 },
{ 9, 9 },
{ 10, 10 },
{ 11, 11 },
{ 12, 2 },
{ 13, 3 },
{ 14, 4 },
{ 15, 5 },
{ 16, 6 },
{ 17, 12 },
{ 18, 13 },
{ 19, 14 },
{ 20, 15 },
{ 21, 16 },
{ 22, 17 },
{ 23, 18 },
{ 24, 19 },
{ 25, 20 },
{ 26, 21}
};
const struct read_write_regs *get_bug_regs(u32 *iterations)
{
const struct read_write_regs *bug_00339_regs_ptr = NULL;
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
case OMAP5432_ES1_0:
case OMAP5432_ES2_0:
bug_00339_regs_ptr = omap5_bug_00339_regs;
*iterations = sizeof(omap5_bug_00339_regs)/
sizeof(omap5_bug_00339_regs[0]);
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA722_ES1_0:
case DRA722_ES2_0:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);
break;
default:
printf("\n Error: UnKnown SOC");
}
return bug_00339_regs_ptr;
}
void emif_get_device_timings_sdp(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
{
/* Identical devices on EMIF1 & EMIF2 */
*cs0_device_timings = &dev_4G_S4_timings;
*cs1_device_timings = &dev_4G_S4_timings;
}
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
__attribute__((weak, alias("emif_get_device_timings_sdp")));
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */