avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
434
u-boot/arch/arm/cpu/armv7/omap3/board.c
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434
u-boot/arch/arm/cpu/armv7/omap3/board.c
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@@ -0,0 +1,434 @@
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/*
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*
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* Common board functions for OMAP3 based boards.
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*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/cache.h>
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#include <asm/armv7.h>
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#include <asm/gpio.h>
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#include <asm/omap_common.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Declarations */
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extern omap3_sysinfo sysinfo;
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#ifndef CONFIG_SYS_L2CACHE_OFF
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static void omap3_invalidate_l2_cache_secure(void);
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#endif
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#ifdef CONFIG_DM_GPIO
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static const struct omap_gpio_platdata omap34xx_gpio[] = {
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{ 0, OMAP34XX_GPIO1_BASE },
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{ 1, OMAP34XX_GPIO2_BASE },
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{ 2, OMAP34XX_GPIO3_BASE },
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{ 3, OMAP34XX_GPIO4_BASE },
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{ 4, OMAP34XX_GPIO5_BASE },
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{ 5, OMAP34XX_GPIO6_BASE },
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};
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U_BOOT_DEVICES(am33xx_gpios) = {
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{ "gpio_omap", &omap34xx_gpio[0] },
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{ "gpio_omap", &omap34xx_gpio[1] },
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{ "gpio_omap", &omap34xx_gpio[2] },
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{ "gpio_omap", &omap34xx_gpio[3] },
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{ "gpio_omap", &omap34xx_gpio[4] },
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{ "gpio_omap", &omap34xx_gpio[5] },
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};
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#else
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static const struct gpio_bank gpio_bank_34xx[6] = {
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{ (void *)OMAP34XX_GPIO1_BASE },
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{ (void *)OMAP34XX_GPIO2_BASE },
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{ (void *)OMAP34XX_GPIO3_BASE },
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{ (void *)OMAP34XX_GPIO4_BASE },
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{ (void *)OMAP34XX_GPIO5_BASE },
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{ (void *)OMAP34XX_GPIO6_BASE },
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
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#endif
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/******************************************************************************
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* Routine: secure_unlock
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* Description: Setup security registers for access
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* (GP Device only)
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*****************************************************************************/
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void secure_unlock_mem(void)
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{
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struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
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struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
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struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
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struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
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struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
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/* Protection Module Register Target APE (PM_RT) */
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writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
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writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
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writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
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writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
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writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
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writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
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writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
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writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
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writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
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writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
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writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
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/* IVA Changes */
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writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
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writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
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writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
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/* SDRC region 0 public */
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writel(UNLOCK_1, &sms_base->rg_att0);
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}
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/******************************************************************************
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* Routine: secureworld_exit()
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* Description: If chip is EMU and boot type is external
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* configure secure registers and exit secure world
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* general use.
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*****************************************************************************/
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void secureworld_exit(void)
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{
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unsigned long i;
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/* configure non-secure access control register */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
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/* enabling co-processor CP10 and CP11 accesses in NS world */
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__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
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/*
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* allow allocation of locked TLBs and L2 lines in NS world
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* allow use of PLE registers in NS world also
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*/
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__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
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/* Enable ASA in ACR register */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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/* Exiting secure world */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
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}
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/******************************************************************************
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* Routine: try_unlock_sram()
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* Description: If chip is GP/EMU(special) type, unlock the SRAM for
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* general use.
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*****************************************************************************/
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void try_unlock_memory(void)
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{
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int mode;
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int in_sdram = is_running_in_sdram();
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/*
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* if GP device unlock device SRAM for general use
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* secure code breaks for Secure/Emulation device - HS/E/T
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*/
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mode = get_device_type();
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if (mode == GP_DEVICE)
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secure_unlock_mem();
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/*
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* If device is EMU and boot is XIP external booting
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* Unlock firewalls and disable L2 and put chip
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* out of secure world
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*
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* Assuming memories are unlocked by the demon who put us in SDRAM
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*/
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if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
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&& (!in_sdram)) {
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secure_unlock_mem();
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secureworld_exit();
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}
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return;
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}
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/******************************************************************************
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* Routine: s_init
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* Description: Does early system init of muxing and clocks.
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* - Called path is with SRAM stack.
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*****************************************************************************/
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void s_init(void)
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{
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watchdog_init();
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try_unlock_memory();
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#ifndef CONFIG_SYS_L2CACHE_OFF
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/* Invalidate L2-cache from secure mode */
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omap3_invalidate_l2_cache_secure();
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#endif
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set_muxconf_regs();
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sdelay(100);
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prcm_init();
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per_clocks_enable();
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#ifdef CONFIG_USB_EHCI_OMAP
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ehci_clocks_enable();
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#endif
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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mem_init();
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}
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#endif
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/*
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* Routine: misc_init_r
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* Description: A basic misc_init_r that just displays the die ID
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*/
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int __weak misc_init_r(void)
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{
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omap_die_id_display();
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return 0;
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}
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/******************************************************************************
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* Routine: wait_for_command_complete
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* Description: Wait for posting to finish on watchdog
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*****************************************************************************/
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static void wait_for_command_complete(struct watchdog *wd_base)
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{
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int pending = 1;
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do {
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pending = readl(&wd_base->wwps);
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} while (pending);
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}
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/******************************************************************************
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* Routine: watchdog_init
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* Description: Shut down watch dogs
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*****************************************************************************/
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void watchdog_init(void)
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{
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struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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/*
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* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
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* either taken care of by ROM (HS/EMU) or not accessible (GP).
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* We need to take care of WD2-MPU or take a PRCM reset. WD3
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* should not be running and does not generate a PRCM reset.
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*/
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setbits_le32(&prcm_base->fclken_wkup, 0x20);
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setbits_le32(&prcm_base->iclken_wkup, 0x20);
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wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
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writel(WD_UNLOCK1, &wd2_base->wspr);
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wait_for_command_complete(wd2_base);
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writel(WD_UNLOCK2, &wd2_base->wspr);
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}
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/******************************************************************************
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* Dummy function to handle errors for EABI incompatibility
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*****************************************************************************/
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void abort(void)
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{
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}
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#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
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/******************************************************************************
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* OMAP3 specific command to switch between NAND HW and SW ecc
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*****************************************************************************/
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static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc < 2 || argc > 3)
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goto usage;
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if (strncmp(argv[1], "hw", 2) == 0) {
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if (argc == 2) {
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omap_nand_switch_ecc(1, 1);
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} else {
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if (strncmp(argv[2], "hamming", 7) == 0)
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omap_nand_switch_ecc(1, 1);
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else if (strncmp(argv[2], "bch8", 4) == 0)
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omap_nand_switch_ecc(1, 8);
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else if (strncmp(argv[2], "bch16", 5) == 0)
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omap_nand_switch_ecc(1, 16);
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else
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goto usage;
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}
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} else if (strncmp(argv[1], "sw", 2) == 0) {
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if (argc == 2) {
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omap_nand_switch_ecc(0, 1);
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} else {
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if (strncmp(argv[2], "hamming", 7) == 0)
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omap_nand_switch_ecc(0, 1);
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else if (strncmp(argv[2], "bch8", 4) == 0)
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omap_nand_switch_ecc(0, 8);
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else
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goto usage;
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}
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} else {
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goto usage;
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}
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return 0;
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usage:
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printf ("Usage: nandecc %s\n", cmdtp->usage);
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return 1;
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}
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U_BOOT_CMD(
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nandecc, 3, 1, do_switch_ecc,
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"switch OMAP3 NAND ECC calculation algorithm",
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"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
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" and 8-bit/16-bit BCH\n"
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" ecc calculation (second parameter may"
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" be omitted).\n"
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"nandecc sw - Switch to NAND software ecc algorithm."
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);
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#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
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#ifdef CONFIG_DISPLAY_BOARDINFO
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/**
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* Print board information
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*/
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int checkboard (void)
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{
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char *mem_s ;
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if (is_mem_sdr())
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mem_s = "mSDR";
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else
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mem_s = "LPDDR";
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printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
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sysinfo.nand_string);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
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{
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u32 i, num_params = *parameters;
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u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
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/*
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* copy the parameters to an un-cached area to avoid coherency
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* issues
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*/
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for (i = 0; i < num_params; i++) {
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__raw_writel(*parameters, sram_scratch_space);
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parameters++;
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sram_scratch_space++;
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}
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/* Now make the PPA call */
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do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
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}
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void __weak omap3_set_aux_cr_secure(u32 acr)
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{
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struct emu_hal_params emu_romcode_params;
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emu_romcode_params.num_params = 1;
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emu_romcode_params.param1 = acr;
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omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
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(u32 *)&emu_romcode_params);
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}
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void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
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u32 cpu_variant, u32 cpu_rev)
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{
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/* Write ACR - affects secure banked bits */
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if (get_device_type() == GP_DEVICE)
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omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
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else
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omap3_set_aux_cr_secure(acr);
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/* Write ACR - affects non-secure banked bits - some erratas need it */
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asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
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}
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#ifndef CONFIG_SYS_L2CACHE_OFF
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static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
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{
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u32 acr;
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/* Read ACR */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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acr &= ~clear_bits;
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acr |= set_bits;
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v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
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}
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/* Invalidate the entire L2 cache from secure mode */
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static void omap3_invalidate_l2_cache_secure(void)
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{
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if (get_device_type() == GP_DEVICE) {
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omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
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} else {
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struct emu_hal_params emu_romcode_params;
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emu_romcode_params.num_params = 1;
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emu_romcode_params.param1 = 0;
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omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
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(u32 *)&emu_romcode_params);
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}
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}
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void v7_outer_cache_enable(void)
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{
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/*
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* Set L2EN
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* On some revisions L2EN bit is banked on some revisions it's not
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* No harm in setting both banked bits(in fact this is required
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* by an erratum)
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*/
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omap3_update_aux_cr(0x2, 0);
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}
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void omap3_outer_cache_disable(void)
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{
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/*
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* Clear L2EN
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* On some revisions L2EN bit is banked on some revisions it's not
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* No harm in clearing both banked bits(in fact this is required
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* by an erratum)
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*/
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omap3_update_aux_cr(0, 0x2);
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}
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#endif /* !CONFIG_SYS_L2CACHE_OFF */
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