103 lines
4.1 KiB
C
103 lines
4.1 KiB
C
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#ifndef _EMMC_H_
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#define _EMMC_H_
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/* SDMMC4 base address (eMMC) on Tegra T124 - at 0x700B0600, NOT 0x78000600 */
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#define SDMMC4_BASE 0x700B0600
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#define SDMMC4_VENDOR_CLK 0x700B0700
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#define SDMMC4_VENDOR_MISC 0x700B07C0
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#define SDMMC4_REG_SIZE 0x200
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/* SDHCI register offsets (from SDMMC4_BASE) */
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_CLOCK_CONTROL 0x2C
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_HOST_VERSION 0xFE
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/* Vendor register offsets (from SDMMC4_BASE) */
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#define SDMMC_VENDOR_CLK_CTRL 0x100 /* 0x700B0700 - Vendor Clock Control */
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#define SDMMC_VENDOR_MISC_CTRL 0x120 /* 0x700B0720 - Vendor Misc Control */
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/* VENDOR_CLK_CTRL bits */
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#define SDMMC_CLK_CTRL_PADPIPE 0x08 /* PADPIPE_CLKEN_OVERRIDE */
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#define SDMMC_CLK_CTRL_SPI_MODE 0x04 /* SPI_MODE_CLKEN_OVERRIDE */
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/* VENDOR_MISC_CTRL bits */
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#define SDMMC_MISC_CTRL_SPEC_300 0x20 /* Enable SDHCI Spec 3.0 mode */
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/* Auto-calibration registers (from SDMMC4_BASE) */
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#define SDMMC_SDMEMCOMP_PADCTRL 0x1E0 /* 0x700B07E0 - SDMEM comp pad control */
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#define SDMMC_AUTO_CAL_CONFIG 0x1E4 /* 0x700B07E4 - Auto-cal configuration */
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#define SDMMC_AUTO_CAL_STATUS 0x1EC /* 0x700B07EC - Auto-cal status */
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/* SDMEM_COMP_PADCTRL bits */
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#define SDMMC_COMP_PADCTRL_E_INPUT (1u << 31) /* Force E_INPUT for calibration */
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/* AUTO_CAL_CONFIG bits */
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#define SDMMC_AUTO_CAL_START (1u << 31) /* Start auto-calibration */
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#define SDMMC_AUTO_CAL_ENABLE (1u << 29) /* Enable auto-calibration */
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/* AUTO_CAL_STATUS bits */
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#define SDMMC_AUTO_CAL_ACTIVE (1u << 31) /* Auto-calibration in progress */
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/* Software Reset bits */
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DAT 0x04
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/* PRESENT_STATE bits */
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#define SDHCI_CMD_INHIBIT 0x00000001
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#define SDHCI_DAT_INHIBIT 0x00000002
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#define SDHCI_CARD_INSERTED 0x00010000
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/* INT_STATUS bits */
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#define SDHCI_INT_CMD_COMPLETE 0x0001
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#define SDHCI_INT_XFER_COMPLETE 0x0002
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#define SDHCI_INT_BUF_WR_READY 0x0010
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#define SDHCI_INT_BUF_RD_READY 0x0020
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#define SDHCI_INT_ERROR 0x8000
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/*
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* MMC Command register values (16-bit, placed in upper half of 0x0C write).
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* Format: (cmd_index << 8) | (type << 6) | (data_present << 5) |
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* (idx_check << 4) | (crc_check << 3) | response_type
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* Response types: 0x00=none, 0x01=136-bit(R2), 0x02=48-bit(R1), 0x03=48-bit+busy(R1b)
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*/
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#define MMC_CMD17_READ 0x113A /* READ_SINGLE_BLOCK: R1, data, CRC+index check */
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#define MMC_CMD24_WRITE 0x183A /* WRITE_BLOCK: R1, data, CRC+index check */
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#define MMC_CMD13_STATUS 0x0D1A /* SEND_STATUS: R1, no data, CRC+index check */
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/* Transfer Mode values (16-bit, lower half of 0x0C write) */
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#define XFER_MODE_READ 0x0010 /* Data direction = read, single block, PIO */
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#define XFER_MODE_WRITE 0x0000 /* Data direction = write, single block, PIO */
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/* Additional transfer mode bits */
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#define XFER_MODE_BLOCK_COUNT_ENABLE 0x0002 /* enable block count register */
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#define XFER_MODE_AUTO_CMD12 0x0004 /* autostop after multiblock transfer */
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#define XFER_MODE_MULTI_BLOCK 0x0020 /* the actuall multiblock transfer */
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#define XFER_MODE_READ_MULTI (XFER_MODE_READ | XFER_MODE_BLOCK_COUNT_ENABLE | XFER_MODE_AUTO_CMD12 | XFER_MODE_MULTI_BLOCK)
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#define XFER_MODE_WRITE_MULTI (XFER_MODE_WRITE | XFER_MODE_BLOCK_COUNT_ENABLE | XFER_MODE_AUTO_CMD12 | XFER_MODE_MULTI_BLOCK)
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/* CAR (Clock and Reset Controller) registers for SDMMC4 */
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#define CAR_BASE 0x60006000
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#define CAR_CLK_ENB_L_SET 0x320
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#define CAR_RST_DEV_L_CLR 0x304
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#define CAR_RST_DEV_L_SET 0x300
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#define CAR_SDMMC4_BIT (1 << 15)
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/* PMC I/O deep power down (PMC_BASE defined in t124.h) */
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#define PMC_IO_DPD2_REQ 0xC0
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#define PMC_IO_DPD2_STATUS 0xC4
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#endif
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